RTL Lead

Job Requirements

• SoC Top-Level Integration:

  Own the

  SoC Top RTL integration

  using

  System Verilog

  for complex multi-core, multi-voltage, and multi-clock domain architectures.

• Low Power Design & Verification:

  Implement and verify the Low Power intent using the

  Unified Power Format (UPF)

  and ensure the design adheres to the defined power strategy through comprehensive

  RTL VCLP (Voltage/Current Leakage Power) checks

  and low-power verification flows.

• Design Quality Sign-off:

  Execute and drive closure for critical pre-synthesis quality checks across the SoC.

  • Linting:

    Perform static design checks to ensure adherence to RTL coding guidelines and best practices.

  • CDC/RDC Checks:

    Implement, analyze, and resolve all violations related to

    Clock Domain Crossing (CDC)

    and

    Reset Domain Crossing (RDC)

    to ensure robust asynchronous interfaces.

• Methodology & Flow Development:

  Collaborate with the CAD/EDA team to enhance and maintain the SoC integration, low-power, and sign-off methodologies and tool flows.

• Cross-Functional Collaboration:

  Work closely with Micro-architecture, IP Design, Verification, Physical Design, and DFT teams to ensure a clean, on-time handoff for tape-out.

• Documentation:

  Develop and maintain technical specifications, sign-off reports, and methodology documents.