776 Physical Design Jobs

We are seeking a highly skilled Physical Design Engineer to own the RTL to GDS physical implementation flows for high-performance and low-power designs. You will be responsible for synthesis, floor-planning, place and route, clock tree synthesis, timing and power closure, EM/IR, PDV, and final PD sign-off. This role requires deep collaboration with micro-architects, expertise in physical design tools, and a strong understanding of modern sub-micron technology nodes. Roles and Responsibility: Own RTL to GDS physical implementation flows for synthesis, floor-planning, place and route, clock tree synthesis, timing & power closure, EM/IR, PDV, and final PD sign off. Own physical design & implementation of high-performance designs from block level to system level components. Deep collaboration with Micro-architects to explore performance, power and area (PPA) trade-offs for high performance and low power designs. Conduct physical implementation feasibility studies and provide design recommendations for best PPA. Develop methodologies and recipes for various stages of physical implementation. Perform various physical design validation (PDV) flows for Timing, Power, EM/IR, etc., to ensure physical design quality. Perform design rule checking (DRC), LVS (Layout Versus Schematic) checks , and other physical verification tasks. Qualifications and Preferred Skills: Experience in all aspects of physical design including synthesis, floor planning, place & route, timing & power closure, EM/IR, physical design validation, etc. Experience with synthesis, place & route, static timing analysis and PDV tools . Experience in implementing clock trees and power grids . Experience with scripting for physical design flow automation . Experience with Synopsys tools such as Design Compiler, Prime Time, ICC, Fusion Compiler , etc. Good knowledge of high-performance and low-power microarchitecture and logic design principles . Understanding of modern ( sub 7nm ) sub-micron technology nodes and device physics. Basic knowledge of System/SoC Architecture and System Verilog RTL coding. Strong communication and collaboration skills. QUALIFICATION: BS, MS in Electrical Engineering or Computer Engineering or related degree.

Job description About The Role Come join Intel's highly regarded Devices Development Group, responsible for creating Client SOCs. We envision the future of computing and design for the next generation of laptop and desktop computers. We are looking for a SoC Physical Design Engineer, who is ready to research, design, develop, and test lead Intel designs as we reimagine how to build SoCs at Intel and in the semiconductor industry. Our bold purpose as a company is to create world-changing technology that enriches the lives of every person on earth and this role is instrumental in furthering our mission to shape the future of technology. Your responsibilities may include but not be limited to: Performing physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Physical Synthesis, Floor planning, Place and Route, Clock Tree Synthesis with Synopsys and/or Cadence EDA tools. Multiple Power Domain analysis and handling using standard Power Formats UPF or CPF. Verification and Signoff including Formal Equivalence Verification, Static Timing Analysis, Reliability Verification, Static and Dynamic power integrity, Layout Verification, Electrical rule checking, Noise analysis and Structural Design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Participating in the development and improvement of physical design methodologies and flow automation. Driving performance optimization, including co-optimization, work with process teams, to create best-in-class designs. The ideal candidate should exhibit behavioral traits that indicate: Self-motivator with strong problem-solving skills. Excellent interpersonal skills, including written, verbal, and presentation communications. Attention to detail and organizational skills. Ability to work as part of a team and collaborate in a high-paced atmosphere.

Job description Conceptualizes, documents, and designs tools, flows, and methods (TFM) for use in the physical design implementation of IPs, SoCs, and the interaction/handoff/reuse between IPs and SoCs. Establishes regression flows, drives improvement in RTL to GDS flows, and creates and implements methodologies for improving robustness, power, performance, area, and timing for optimizing physical design constraints. Develops new physical design techniques through innovative scripts, checkers, flows, and other CAD based automation to simplify and expedite the design process. Analyzes retrospective data on current generation quality and efficiency gaps to identify proper incremental, evolutionary, or transformative changes to the existing physical design related TFM. Partners with physical design, circuits, CAD, RTL, tool/flow owners, and thirdparty vendor teams to continuously improve physical design methodologies and efficiencies.

Job description Job Description The Foundation IP Corporate Memory Organization is looking for an experienced Memory Layout Designer to join its team. Develop custom layout design for memory compilers (e.g., bit cells, SRAMs, Register Files). Perform detailed physical array planning, area optimization, critical wire analysis, and custom leaf cell layout. Conduct complete layout verification including design rule compliance, electromigration, voltage drop (IR), selfheat, and other reliability checks. May use custom autorouters and custom placers to efficiently construct layout. Provide feedback to circuit design engineers for new feature feasibility studies and implement circuit enhancement requests. Develop and drive new and innovative layout methods to improve productivity and quality. Troubleshoot a wide variety of issues up to and including design and tool/flow/methodology issues used for layout design. Qualifications Hands-on experience with layouts of critical memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array, decoders, etc., in compiler context. Solid experience with custom Memory (SRAM, RF, ROM) layout physical design Creates mask layouts of integrated circuits for a given specification and runs complete set of design verification tools for process design rules, electro migration, voltage drop (IR), ESD, and other reliability checks on the layouts. Develops custom layout design memory compilers (e.g., bit cells, SRAMs, Register Files), performs area impact assessment with updated PDKs. Performs detailed physical array planning, power planning, area optimization, critical wire analysis, custom leaf cell layout. Provides feedback to circuit design engineers for new feature feasibility studies and implements circuit enhancement requests. Knowledge of and experience with advanced FinFET processes in 5nm. Solid experience using Cadence Virtuoso for custom layout physical design Scripting knowledge/ SKILL coding is a plus. Years of Experience: Bachelors with 3 to 6 yrs of experience. Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.

Job description Job Description In this role, we are looking for an experienced SOC Analog Engineer to lead Analog Integration for chiplet designs for custom and domain specific products. The chiplets will be leveraged to enable modular design and support multiple products. As part of this team, the candidate will work with leading edge technologies and solutions across multiple domains including SoC multi-die implementations (2.5 and 3D), power delivery, leading edge memory technologies, innovate thermal solutions, and external vendors. The team will also look at options to enhance product power/performance/area/cost thru improved tools and methodologies. Responsibilities will include but are not limited to: Drive all aspects of analog integration domain, including analog route implementation/extraction/verification, AIP floor planning, PKG interactions w/ analog IOs, power framework simulations, ESD planning/verification, MIM, and GPIO planning Collaborate across multiple teams/stakeholders to create optimal solutions across Platform/PKG/SoC Create, run, and analyze simulations for design and verification of analog circuitry such as amplifiers, reference systems, ESD, and high-speed Rx/Tx circuitry Scope process technologies and enable integration of Analog IP and silicon supplied by external vendors Support post-silicon activities in debug and failure analysis for analog and power delivery The ideal candidate should exhibit the following behavioral traits/skills: Have expertise with domain specific signoff tools including: HV Openrail, Redhawk, LV/antenna checks. Have experience with IP design, packaging and delivery methodologies and flows as well as generation of IP integration documents and datasheets Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Bachelor's or Master's degree in Computer Science, Computer Engineering or Electrical Engineering. 6+ years of Analog design experience including Analog integration and AIP design 6+ years experience with SoC analog requirements, including analog distributions, and ESD. Preferred Qualifications: Experience with Design tools and methods. Full chip integration, die-to-die and package integration experience. 2.5/3D design experience and implications on analog design. Experience with power delivery design and flows

Job description Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high-quality integration and verification of the IP block. Drives quality assurance compliance for smooth IP SoC handoff. Key Responsibilities: Design and develop cache architectures, including L1, L2, and L3 caches. Optimize cache performance, power, and area through innovative design techniques. Work closely with backend (BE) engineers to achieve timing closure and resolve any issues. Conduct static timing analysis (STA) and optimize the design for timing. Utilize lint, CDC (Clock Domain Crossing), and other design tools to ensure design quality and robustness. Implement and adhere to best practices in RTL design Collaborate with microarchitecture, RTL, verification, and physical design teams to ensure seamless integration of cache subsystems. Document design specifications, implementation details, and verification results. Participate in design reviews and provide feedback on other team members designs. Qualifications Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field. 5-15 years of proven experience in design and micro-architecture. Strong understanding of memory hierarchy, cache coherence, and performance optimization techniques. Proficiency in hardware description languages (HDL) such as Verilog or VHDL. Experience integrating BIST and DFT features into RTL designs. Experience implementing Error Correction Code (ECC) mechanisms in cache designs. Knowledge of error detection, correction, and recovery techniques. Experience with simulation and verification tools (e.g., ModelSim, VCS). Experience using lint, CDC, and other design tools to ensure design quality. Proficiency in static timing analysis (STA) and timing closure techniques. Familiarity with physical design constraints and considerations. Excellent problem-solving skills and attention to detail. Strong communication and teamwork abilities.

Job description About The Role This position is for an experienced, motivated, and passionate circuit design engineer with expertise in the area of custom circuits memories, SSARF SRAM, Register File, ROM design for GHI CCG SAI Circuits Team. In this position you will be working in a team responsible for delivering high quality designs for graphics projects. You would also be involved in key decisions finalizing the memory architecture that best meets the design requirements of the program, technical readiness involving circuit simulations and responsibility for implementation as well as convergence of the design while meeting high circuit quality. The key responsibilities include ownership of tools, flows, methodologies as well as coming up with innovative design implementations with focus on power and area reduction. The role would require deep understanding of transistor and circuit behavior, strong communication, problem solving skills, time management and multitasking skills. The team members have also an opportunity to diversify their skills into other custom circuits as well as working with the client in integration of the custom circuits. Qualifications Minimum QualificationsMinimum 4-7 years of experience in designing and delivering of SRAM's/RF's/ROM's. Understanding of semiconductor device physics; VLSI Technology and VLSI circuits (analog/digital), Familiarity with spice simulations and Verilog and other tools for design and development of memory IP's like ESPCV, Nanotime, Nova, Totem etc. Knowledge of scripting (PERL/TCL/Python) is desirable, Preferred Educational QualificationsME/Mtech/MS in Microelectronics/VLSI Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Job description Work in a VLSI wireless team. Major subject VLSI, digital circuit, analog circuit. Project done on related topics preferably using CAD tools and familiar to ASIC design flow. Qualifications Degree:ME/M.TECH VLSI design, signal processing and machine learning, communication engineeringSchools: NIT/VIT Role: Physical Design / Layout Engineer Industry Type: Electronic Components / Semiconductors Department: Engineering - Hardware & Networks Employment Type: Full Time, Permanent Role Category: Hardware Education UG: Any Graduate PG: M.Tech in Any Specialization

As a senior leader in the central physical design team at Marvell, you will shape the long-term vision for physical design capabilities and infrastructure in alignment with the company-wide technology strategy. You will lead RTL-to-GDSII implementation for multiple SoC programs, overseeing synthesis, floorplanning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, and physical verification (DRC/LVS). Your role will involve providing strategic leadership and technical direction to physical design teams, ensuring successful and timely tapeouts of complex, high-performance SoCs. Mentoring and developing engineering talent will be a key aspect of your responsibilities, fostering a culture of innovation, collaboration, and continuous improvement within the team. You will oversee team structure, hiring, performance management, and career development to build and retain a high-performing physical design organization. Driving cross-functional collaboration with design teams to influence design decisions and ensure successful project execution will also be part of your role. You will navigate and resolve cross-functional conflicts effectively, fostering alignment and maintaining momentum across diverse teams. It will be your responsibility to drive the development and adoption of next-generation physical design methodologies, flows, and automation to improve productivity and design quality. Managing project schedules, resources, and risks to ensure alignment with business goals and customer requirements will also fall under your purview. Representing the physical design function in cross-org and executive-level discussions, contributing to long-term technology and product strategy will be expected. Collaborating with EDA vendors and internal CAD teams to evaluate and deploy new tools and technologies is also a crucial aspect of the role. We are looking for candidates with a Bachelors, Masters, or PhD degree in Electrical Engineering, Computer Engineering, or a related field, along with 18+ years of progressive experience in back-end physical design and verification, including significant leadership roles. A proven track record in leading and scaling physical design teams, managing complex SoC projects, and delivering high-quality tapeouts under aggressive schedules is essential. Deep expertise in hierarchical physical design strategies, methodologies, and advanced process node challenges is required. Additionally, familiarity with AI/ML-driven optimization in physical design tools is considered a plus. Strong communication and collaboration skills, along with the ability to influence cross-functional teams and executive stakeholders, are also important qualities for this role. Proficiency in automation and scripting using Makefile, Tcl, Python, or Perl to enhance design efficiency and flow robustness is expected. Marvell offers competitive compensation, great benefits, and a workstyle that promotes shared collaboration, transparency, and inclusivity. The company is dedicated to providing its employees with the tools and resources they need to succeed in meaningful work, grow, and develop within the organization. For more information on working at Marvell, visit our Careers page.,

Qualcomm India Private Limited is a leading technology innovator that drives digital transformation to create a smarter, connected future for all. As a Hardware Engineer at Qualcomm, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This includes working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. The ideal candidate should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 3+ years of experience in Hardware Engineering. Alternatively, a Master's degree with 2+ years of relevant experience or a PhD with 1+ year of experience is also acceptable. The desired experience range for this role is 7 to 10 years. Key responsibilities include the physical design of block levels with a full understanding of the PnR cycle, a good grasp of Physical design fundamentals, and hands-on experience with industry-standard pnr tools like ICC2/Innovus. Additionally, familiarity with signoff tools such as Prime Time, Redhawk, and calibre is necessary. The candidate should possess the ability to guide junior engineers in resolving technical issues. Proficiency in tools like ICC/Innovus, PT, StarRC, Redhawk, Calibre DRC/LVS, and scripting languages like TCL and Perl is required for this role. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. Reasonable accommodations can be requested by emailing disability-accommodations@qualcomm.com or calling Qualcomm's toll-free number. The company expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information and proprietary data. Please note that Qualcomm's Careers Site is intended for individuals seeking job opportunities at Qualcomm and is not to be used by staffing or recruiting agencies. Unsolicited submissions from agencies will not be accepted, and Qualcomm does not respond to requests for application updates or resume inquiries through the provided email address. For further information about this role, please reach out to Qualcomm Careers.,

You will be responsible for joining OnSemi's growing team in Bengaluru, India as a Sr. Principal Digital Design Engineer focused on New Product Development in Power Management. Your primary responsibilities will include working on the development of various Power Management products for consumer, industrial, and automotive applications such as DC-DC PMIC/POL, multiphase controllers, drivers, converters, LED drivers, SiC drivers, switches, and efuses. Your key responsibilities will involve collaborating with different product lines for RTL implementation of power convertor controller designs, working on digital design architecture, RTL, low power design, synthesis, and timing analysis. You will also interface with the Physical Design team for the power management chips using state-of-the-art RTL2GDS flows. As part of a large engineering team, you will collaborate effectively with design architects, digital verification, project management, and digital and analog design teams across various global locations. You will be involved in micro-architecture to RTL implementation, supporting system-level bring-up on pre-silicon platforms, and owning the technical outcome of Power Management ICs. Furthermore, you will be responsible for understanding project goals, executing with realistic schedules, reporting progress status, and supporting post-silicon validation activities. You will also lead and support customer issues, production issues, FW and system development, and failure analysis. Onsemi is a company driving disruptive innovations to create a better future, focusing on automotive and industrial end-markets. With a highly differentiated product portfolio, Onsemi aims to solve complex challenges and lead the way in creating a safer, cleaner, and smarter world. To qualify for this role, you should have a BS in Electrical Engineering or related field with 12 years of experience, or an MS with 10 years of experience in Digital Design, Architecture, and ASIC/Mixed signal chip developments. The ideal candidate will possess a thorough understanding of the end-to-end digital design flow, RTL design, CDC, ASIC synthesis, timing analysis, P&R, UPF, system Verilog, Verilog, TCL, and Perl/Python/XML programming languages.,

As a skilled professional in third party IP design and integration across multiple technology nodes such as 28nm, 65nm, and 130nm, you will play a crucial role in silicon realization of LC resonance-based energy recycling patented IP. You will be responsible for DSM Library development, including Fin FETs, tailored for adoption by customers into future System on Chip (SoC) solutions. Your expertise will be instrumental in the successful tape out of benchmark test chips and subsequent characterization to secure customer design wins. You are expected to deliver results within specified timelines aligned with Management By Objectives (MBOs) and contribute to the development of first silicon success methodologies. Your proactive approach will aid in achieving aggressive objectives outlined by the organization. Additionally, you will support global teams with flexibility in terms of working times and locations, as required. Your core responsibilities will involve designing, simulating, and verifying cutting-edge CMOS digital and analog circuits. You will provide hands-on supervision to IC circuit and mask designers, offering valuable insights into floorplan and layout guidelines. Furthermore, you will actively support technology transfer to product development teams and engage in the debugging and characterization of designs. To excel in this role, you should possess a minimum of 5 years of experience in CMOS Analog/Mixed Signal Circuit Design. A strong fundamental understanding of transistor devices and analog transistor-level design is essential. Your hands-on experience with Giga-bit circuits and subsystems, such as oscillators, biasing circuits, bandgap references, regulators, op-amps, and high-speed clocking circuits, will be highly beneficial. Familiarity with PLL, DLL, transmitters, receivers, and equalization techniques is advantageous. Proficiency in utilizing IC design tools like Synopsys/Cadence for Analog Circuit Design, along with expertise in circuit simulation, system simulation, layout design, physical design, physical verification, parasitic extraction, and full chip verification is expected. Additionally, scripting skills in Perl and proficiency in Verilog/Verilog AMS modeling and design are valuable assets for this role. Key Skills: Transistor Level Design, Circuit Simulation, Circuit Design, CMOS Analog/Mixed Signal Circuit Design, Physical Design, Scripting Skills (Perl), IC Design Tools like Synopsys/Cadence, Design, Layout Design, Verilog/Verilog AMS, System Simulation,

Eridu AI India Private Limited, a wholly owned subsidiary of Eridu Corporation, Saratoga, California, USA, is seeking highly motivated and talented professionals for its R&D center in Bengaluru. Eridu AI is a Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. The company introduces innovative solutions across semiconductors, software, and systems to enhance AI data center performance, increase GPU utilization, and reduce capex and power consumption. Led by a team of experienced Silicon Valley executives and engineers, Eridu AI's solution has been widely recognized by hyperscalers. We are currently looking for an RTL Design Director to lead our Networking IC team in Bengaluru. As a part of the Design Group, you will play a crucial role in defining, specifying, architecting, executing, and productizing cutting-edge Networking devices. This position offers a unique opportunity to shape the future of AI Networking and work on real-world problems. Responsibilities: - Lead the offshore RTL team and provide technical guidance. - Collaborate with Chip and System Architects to translate architecture requirements into microarchitecture and design implementation. - Conduct RTL coding, code reviews, and debugging. - Document microarchitecture and RTL subsystems. - Define development flows to enhance efficiency and quality. - Coordinate with other teams for successful RTL implementation. - Utilize domain experience in Ethernet, PCIe, and protocols for informed design decisions. Qualifications: - MS/BS degree with a minimum of 15+ years of experience. - Demonstrated success in tape-outs and productization, preferably in networking devices. - Ability to translate architecture-level descriptions into implementable designs with clear documentation. - Proficiency in addressing clock/reset/power domain challenges and safe design practices. - Experience in optimizing hardware for product performance. - Strong knowledge of industry tools and best practices for RTL development. - Understanding of networking protocols and ASIC design flow. - Familiarity with DFT and physical implementation requirements. Join us at Eridu AI to be a part of a world-class team working on groundbreaking technology that shapes the future of AI infrastructure. Your work will directly contribute to transforming data center capabilities and developing next-generation AI networking solutions. The starting base salary will be determined based on relevant skills, experience, qualifications, and market trends. For more information, visit our website at eridu.ai.,

Job Overview As a part of in Arm&aposs Solutions Engineering group we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies. Responsibilities Synthesis, Physical design and implementation of CPU cores, system interconnect and other ARM Designs. Analyze design timing, area and power to help improve the quality of ARM Design. Optimize design, flow and methodologies to achieve best in class PPAT working with various internal and external teams. Develop and deploy new methodologies to improve implementation efficiency and results Support and develop detailed implementation analysis and data-mining methodologies. Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. Converting R&D concepts into real implementation solutions. Enable our partners to achieve the best possible quality of results Required Skills And Experience Bachelors or Masters degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields. 7+ years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM and Physical verification Strong Communication and Problem Solving Skills. Experience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams Experience working closely in top and block level Synthesis, Floor planning, Place and Route, CTS, logical and physical optimization, timing closure and power analysis flows. Proven programming and scripting skills eg. Tcl, Perl, Python, Make. Nice To Have Skills And Experience Knowledge around Arm based SoCs! Experience with low power design techniques (power gating, voltage/frequency scaling) Experience with Verilog RTL design. Experience with ATPG tools/and or production testing. In Return At Arm, we are guided by our core beliefs that reflect our creative culture and guide our decisions, defining how we work together to surpass ordinary and shape extraordinary. Accommodations at Arm At Arm, we want our people to Do Great Things. If you need support or an accommodation to Be Your Brilliant Self during the recruitment process, please email [HIDDEN TEXT]. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and dont discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. Hybrid Working at Arm Arms hybrid approach to working is centred around flexibility, where we split our time between the office and other locations to get our work done. Within that framework, we empower groups and teams to determine their own particular hybrid working pattern, depending on the work and the teams needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email [HIDDEN TEXT] . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arms approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the teams needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and dont discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. Show more Show less

Where Application Engineering, Sr Staff Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12360 Remote Eligible No Date Posted 27/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled, customer-focused technical leader driven by a passion for solving complex challenges and enabling innovation. With a robust background in semiconductor technologies, electronic design automation (EDA), or related fields, you thrive in fast-paced, collaborative environments where your expertise makes a tangible impact. You possess a strong analytical mindset, adept at diagnosing intricate technical issues and designing creative solutions that empower customers to succeed. Your experience spans the full spectrum of application engineering, from hands-on tool deployment and support to architecting advanced workflows and driving technical engagement with global clients. You are an effective communicator, equally comfortable presenting to executives, mentoring junior engineers, and translating technical jargon into actionable business insights. Your commitment to continuous learning keeps you at the forefront of industry advancements, and your inclusive approach ensures that diverse perspectives are valued and integrated into your work. You embrace ambiguity and adapt quickly to changing priorities, leveraging your organizational skills to manage multiple projects simultaneously. Your customer-centric attitude combines empathy with technical acumen, allowing you to build strong, trust-based relationships. As a proactive team player and natural leader, you inspire those around you to achieve excellence while championing Synopsys values of integrity, innovation, and collaboration. What You ll Be Doing: Engaging directly with customers to understand their technical requirements, workflows, and business objectives, delivering tailored solutions that maximize the value of Synopsys products. Providing advanced technical support for Synopsys EDA tools, including troubleshooting, debugging, and resolving complex issues across various platforms and environments. Leading technical evaluations, product demonstrations, and proof-of-concept activities to showcase Synopsys technology advantages. Collaborating closely with R&D and product management teams to influence product direction based on customer feedback and industry trends. Developing and delivering technical training, documentation, and best practice materials for both internal stakeholders and external clients. Mentoring and guiding junior engineers, fostering a culture of knowledge sharing and continuous improvement within the team. Representing Synopsys at industry events, conferences, and customer meetings as a technical subject matter expert. The Impact You Will Have: Accelerating customer adoption and satisfaction by providing world-class technical solutions and support. Enabling successful deployment of cutting-edge EDA tools, directly contributing to the design and verification of next-generation silicon chips. Driving product innovation by relaying customer insights and real-world challenges to Synopsys engineering teams. Enhancing Synopsys reputation as a trusted technology partner through exceptional service and technical leadership. Reducing time-to-market for customers by streamlining workflows and optimizing tool usage. Strengthening long-term customer relationships and identifying new opportunities for Synopsys solutions. What You ll Need: Extensive experience with EDA tools (e.g., synthesis, verification, physical design, DFT, timing analysis) and semiconductor design flows. Strong programming and scripting skills (such as TCL, Python, Perl, or Shell) for automation and customization tasks. Solid understanding of digital and/or analog IC design principles and methodologies. Proven ability to troubleshoot complex technical issues and deliver practical solutions in a customer-facing role. Excellent written and verbal communication skills, with the ability to present technical information clearly to diverse audiences. Familiarity with Linux/Unix environments and version control systems. Bachelor s or Master s degree in Electrical Engineering, Computer Engineering, or a related technical field (PhD a plus). Who You Are: A collaborative team player who values diversity and actively contributes to an inclusive work environment. Resourceful and self-motivated, with a strong sense of ownership and accountability for results. Excellent at building relationships and influencing stakeholders at all levels. Adaptable and resilient, able to thrive in a dynamic, fast-evolving industry. Analytical thinker with a keen attention to detail and a passion for continuous improvement. Effective mentor and coach, fostering growth in others. The Team You ll Be A Part Of: You ll join a high-impact Customer Application Services team at Synopsys, dedicated to empowering our clients to achieve their design goals with maximum efficiency and innovation. The team brings together experts in EDA, semiconductor design, and customer engagement, collaborating across functions to solve the most challenging technical problems. With a focus on knowledge sharing, continuous learning, and technical excellence, the team is instrumental in driving Synopsys leadership in the industry and ensuring our customers ongoing success. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled, customer-focused technical leader driven by a passion for solving complex challenges and enabling innovation. With a robust background in semiconductor technologies, electronic design automation (EDA), or related fields, you thrive in fast-paced, collaborative environments where your expertise makes a tangible impact. You possess a strong analytical mindset, adept at diagnosing intricate technical issues and designing creative solutions that empower customers to succeed. Your experience spans the full spectrum of application engineering, from hands-on tool deployment and support to architecting advanced workflows and driving technical engagement with global clients. You are an effective communicator, equally comfortable presenting to executives, mentoring junior engineers, and translating technical jargon into actionable business insights. Your commitment to continuous learning keeps you at the forefront of industry advancements, and your inclusive approach ensures that diverse perspectives are valued and integrated into your work. You embrace ambiguity and adapt quickly to changing priorities, leveraging your organizational skills to manage multiple projects simultaneously. Your customer-centric attitude combines empathy with technical acumen, allowing you to build strong, trust-based relationships. As a proactive team player and natural leader, you inspire those around you to achieve excellence while championing Synopsys values of integrity, innovation, and collaboration. What You ll Be Doing: Engaging directly with customers to understand their technical requirements, workflows, and business objectives, delivering tailored solutions that maximize the value of Synopsys products. Providing advanced technical support for Synopsys EDA tools, including troubleshooting, debugging, and resolving complex issues across various platforms and environments. Leading technical evaluations, product demonstrations, and proof-of-concept activities to showcase Synopsys technology advantages. Collaborating closely with R&D and product management teams to influence product direction based on customer feedback and industry trends. Developing and delivering technical training, documentation, and best practice materials for both internal stakeholders and external clients. Mentoring and guiding junior engineers, fostering a culture of knowledge sharing and continuous improvement within the team. Representing Synopsys at industry events, conferences, and customer meetings as a technical subject matter expert. The Impact You Will Have: Accelerating customer adoption and satisfaction by providing world-class technical solutions and support. Enabling successful deployment of cutting-edge EDA tools, directly contributing to the design and verification of next-generation silicon chips. Driving product innovation by relaying customer insights and real-world challenges to Synopsys engineering teams. Enhancing Synopsys reputation as a trusted technology partner through exceptional service and technical leadership. Reducing time-to-market for customers by streamlining workflows and optimizing tool usage. Strengthening long-term customer relationships and identifying new opportunities for Synopsys solutions. What You ll Need: Extensive experience with EDA tools (e.g., synthesis, verification, physical design, DFT, timing analysis) and semiconductor design flows. Strong programming and scripting skills (such as TCL, Python, Perl, or Shell) for automation and customization tasks. Solid understanding of digital and/or analog IC design principles and methodologies. Proven ability to troubleshoot complex technical issues and deliver practical solutions in a customer-facing role. Excellent written and verbal communication skills, with the ability to present technical information clearly to diverse audiences. Familiarity with Linux/Unix environments and version control systems. Bachelor s or Master s degree in Electrical Engineering, Computer Engineering, or a related technical field (PhD a plus). Who You Are: A collaborative team player who values diversity and actively contributes to an inclusive work environment. Resourceful and self-motivated, with a strong sense of ownership and accountability for results. Excellent at building relationships and influencing stakeholders at all levels. Adaptable and resilient, able to thrive in a dynamic, fast-evolving industry. Analytical thinker with a keen attention to detail and a passion for continuous improvement. Effective mentor and coach, fostering growth in others. The Team You ll Be A Part Of: You ll join a high-impact Customer Application Services team at Synopsys, dedicated to empowering our clients to achieve their design goals with maximum efficiency and innovation. The team brings together experts in EDA, semiconductor design, and customer engagement, collaborating across functions to solve the most challenging technical problems. With a focus on knowledge sharing, continuous learning, and technical excellence, the team is instrumental in driving Synopsys leadership in the industry and ensuring our customers ongoing success. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Where Applications Engineering, Staff Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12365 Remote Eligible No Date Posted 27/07/2025 Job Description and Requirements Our Silicon Design & Verification business is all about building high-performance silicon chips faster. We re the world s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance eliminating months off their project schedules. Were looking for an Applications Engineer to join our team. Does this sound like a good role for you This is an exciting opportunity to be part of applications engineering team that supports the industry leading Static Timing Analysis tool, Primetime. The primary focus of the Application Engineer (AE) is to drive increased usage of the product in both pre-sale and post-sale capacity. Pre-sales tasks include competitive benchmarks and evaluation, articulating the superiority to our customer s design team and management. Post-sales tasks include customer training, tape-out support and advance collaboration initiatives for product enhancements. The job involves working closely with users/customers and multiple organizations like R&D, marketing, sales among others. Key Qualifications Synopsys STA tool, Primetime experience and knowledge are required Knowledge of timing corners/modes, process variations and signal integrity related issues are required Familiarity with synthesis, Physical design, extraction and ECO methodology is desired Strong TCL knowledge is preferred Excellent verbal and written communication skills are mandatory. Prior customer facing role is a plus BSEE or equivalent, required with 3-4 years of experience, or MSEE, or equivalent with 2-3 years of experience Job Description and Requirements Our Silicon Design & Verification business is all about building high-performance silicon chips faster. We re the world s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance eliminating months off their project schedules. Were looking for an Applications Engineer to join our team. Does this sound like a good role for you This is an exciting opportunity to be part of applications engineering team that supports the industry leading Static Timing Analysis tool, Primetime. The primary focus of the Application Engineer (AE) is to drive increased usage of the product in both pre-sale and post-sale capacity. Pre-sales tasks include competitive benchmarks and evaluation, articulating the superiority to our customer s design team and management. Post-sales tasks include customer training, tape-out support and advance collaboration initiatives for product enhancements. The job involves working closely with users/customers and multiple organizations like R&D, marketing, sales among others. Key Qualifications Synopsys STA tool, PrimeTime experience and knowledge are required Knowledge of timing corners/modes, process variations and signal integrity related issues are required Familiarity with synthesis, Physical design, extraction and ECO methodology is desired Strong TCL knowledge is preferred Excellent verbal and written communication skills are mandatory. Prior customer facing role is a plus BSEE or equivalent, required with 3-4 years of experience, or MSEE, or equivalent with 2-3 years of experience At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Strong on Digital Design, SV, UVM. Hands-on experience in any of the DV protocols like PCIe, USB 3.0, DDR 3/4/5, AMBA, Ethernet (10G/100G), SATA, and MIPI (CSI/DSI), UFS, CXL Also Hiring PD, RTL, DFT Apply& Share resume to mansoor@hisoltech.com

Eximietas is currently seeking Senior Physical Design Leads/Architects with at least 10+ years of experience to join their team in Visakhapatnam. Immediate joiners or those with a short notice period are preferred for this role. Qualifications: - A minimum of 10+ years of experience in Physical Design using mainstream P&R tools. - A Bachelor's or Master's Degree in Electronics, Electrical, Telecom, or VLSI Engineering. In this role, you will: - Work on designs using advanced nodes such as 10nm/7nm/5nm or lower, collaborating with various customers to meet performance, area, and power targets. - Develop flow and methodology for placement, clock-tree synthesis, and routing. - Provide training and technical support to customers. Key Technical and Professional Requirements: - Proficiency in place & route flow, including placement guidelines, clock-tree synthesis, routing, and timing optimizations. - Experience in hierarchical designs and Low Power implementation is advantageous. - Familiarity with Synthesis, collaborating with RTL and implementation designers for improved results. - Knowledge of Floor Plan design, encompassing placement of hard macros, padring, power grid, and custom analog routes. - Experience in Static Timing Analysis tasks such as constraints development, parasitic extractions, and sign-off requirements. - Understanding of Physical Verification processes including DRC, LVS, DFM, and chip finishing. If you are interested in this opportunity, please share your resume with maruthiprasad.e@eximietas.design. We look forward to receiving your applications!,

You play a crucial role at AMD, where the focus is on transforming lives through innovative technology to make a difference in the industry, communities, and the world. The mission at AMD is centered around creating exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. The core of this mission lies in the AMD culture, which thrives on pushing the boundaries of innovation to tackle the world's most pressing challenges. The values of execution excellence, directness, humility, collaboration, and inclusivity of diverse perspectives drive the AMD team towards achieving their goals. As a SoC Design Architect at AMD, you will take on a leadership role in designing high-end networking silicon. Your responsibilities will include overseeing the development of SoCs in collaboration with IP, Subsystem, and Physical design teams. You will be detail-oriented when it comes to managing Power, Performance, and Area, while also ensuring adherence to schedules and cost management. This senior position will challenge you to lead the development of cutting-edge networking IP and silicon, coordinating milestones across various geographical locations. To excel in this role, you must possess exceptional communication and presentation skills, as evidenced by technical publications, presentations, trainings, and executive briefings. Your ability to address SOC design challenges, guide teams towards milestones, and communicate progress effectively to upper management will be crucial for success. Key Responsibilities include defining product features, driving technical specifications for SoC and IP blocks, collaborating with IP/Domain architects to resolve technical issues, and providing technical direction to execution teams. You will also be responsible for system optimization, area and floorplan refinement, verification test plan reviews, bug resolution, and performance/power verification sign-offs. Preferred Experience for this role includes a strong foundation in Systems & SoC architecture, expertise in CPU or Networking, memory sub-systems, power management, and low power design. Excellent communication, management, and collaborative skills are essential, along with the ability to work effectively with diverse teams across different geographies. Academic Credentials preferred for this position include a Bachelor's or Master's degree in a related discipline. Join AMD to be a part of a team that drives innovation and makes a positive impact on the world.,

The ideal candidate for this position should have a strong understanding of the semiconductor chip design services domain with at least 4-8 years of experience. You must have a proven track record of successfully closing positions across SOC Verification, Physical Design, and DFT. In-depth knowledge of ASIC skills such as SOC Verification, Physical Design, and DFT is essential for this role. As part of your responsibilities, you will be required to identify talent beyond job portals and actively engage with the right talent pool for semiconductor skills. Additionally, you should possess the ability to headhunt passive candidates and effectively sell the job and the employer brand to potential candidates. Strong verbal and written English communication skills are a must-have for this position. Key skills required for this role include physical design, SOC verification, DFT, semiconductor chip design services, verbal and written English communication skills, talent acquisition and management, and effective communication skills. If you meet these requirements and are looking to take on a challenging role in the semiconductor industry, we encourage you to apply for this exciting opportunity.,

Physical Design Engineer (Semiconductor) Role Summary: Responsible for the layout and implementation of digital ICs from RTL to GDSII. Key Responsibilities: Perform floor planning, placement, routing, and timing closure. Optimize power, performance, and area (PPA). Work with verification and DFT teams to ensure design integrity. Use tools like Cadence Innovus , Synopsys ICC2. Generate and validate physical design sign-off reports. Qualifications: Bachelors/ Masters in Electrical or Computer Engineering . Proficiency in physical design flows and EDA tools. Knowledge of STA, IR drop, EM analysis.

Job Details Job Description: Altera is looking for a talented and driven Silicon Design Engineering Manager to lead and inspire a multidisciplinary silicon design team. In this critical role, you will manage design engineers across multiple functional domainsincluding logic design, verification, circuit design, and physical implementationfor cutting-edge IP, subsystems, SoCs, and discrete chips. Youll be at the forefront of Alteras product innovation, driving high-quality silicon solutions that meet power, performance, area, and cost objectives. Key Responsibilities Lead and manage a team of silicon design engineers across multiple disciplines and development phases. Drive end-to-end development of IP blocks, subsystems, and full-chip SoC designs, ensuring on-time delivery with high quality. Oversee design reviews, ensuring power, performance, area (PPA), and cost targets are met. Collaborate with architecture, IP, and SoC development teams to ensure cohesive design and execution. Monitor verification results, conduct design debug, analyze data, and drive resolution of design issues. Implement and maintain rigorous silicon quality and continuous improvement standards. Optimize and evolve silicon development methodologies, tools, and processes. Set clear team goals, manage priorities, provide coaching, and foster a culture of accountability and high performance. Role model Altera and Intel values while creating an inclusive, productive, and innovative work environment. Minimum Requirements Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. 10+ years of experience in silicon design, including at least 3 years in a management or technical leadership role. Proven track record managing full lifecycle silicon design projects from architecture through tape-out. Strong technical background in logic design, verification, and physical design. Deep understanding of PPA trade-offs and experience driving metrics-based decision making. Experience working across functional teams and global development environments. Preferred Qualifications Experience in SoC or FPGA-based design projects. Familiarity with industry-standard EDA tools and design methodologies. Demonstrated leadership in team building, performance management, and talent development. Strong communication and organizational skills. Qualifications Job Type: Regular Shift Shift 1 (India) Primary Location: Bengaluru, Karnataka, India Additional Locations: Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Show more Show less

About Marvell . Your Team, Your Impact Data Centre Engineering Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. What You Can Expect Define the memory sub system architecture, micro-architecture and register specification for highly complex SoCs. Drive and participate in specification writeup Conduct detailed performance, architectural and design requirement reviews with cross-functional teams, IP Vendors and customers Implement a specification using RTL coding techniques and best practices Work with third party vendors to define customization requirements of third party IPs (controller, PHY, etc. ) Work with the physical design teams, reviewing and providing guidance in floorplanning, power analysis, synthesis and timing signoff. Work with the verification team on pre-silicon verification tasks such as reviewing the verification test plans, coverage analysis, full-chip simulation and emulation, performance and power analysis and debug Help develop and/or evaluate design and verification methodologies and participate in improving existing ones Collaborate with and provide guidance to the post silicon and software teams for prototype bring up and performance tuning Provide mentorship to the more junior team members What Were Looking For Bachelor s degree in Computer Science, Electrical Engineering or related fields and 20+ years of related professional experience. Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 18+ years of experience. Experience in creating architectural, micro-architectural, and register specifications. Verilog/System Verilog RTL coding with System Verilog assertions Well-versed in all stages of the ASIC design flow (including specification, architecture and design implementation, prototype bring-up) Expertise in high speed memory protocols (DDR4/5, LPDDR4/5X, HBM3) Has worked on complex chips such as network processors, CPUs , GPUs , NOCs , Switches , Machine Learning SoCs etc. owning full chip, subsystem and block level architecture and design Expertise in any of the following domains would be a big plus: networking, embedded systems architecture, computer architecture, machine learning accelerators Experience with scripting in Perl/Python/Shell Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

Physical Design Engineer (Semiconductor) Role Summary: Responsible for the layout and implementation of digital ICs from RTL to GDSII. Key Responsibilities: Perform floor planning, placement, routing, and timing closure. Optimize power, performance, and area (PPA). Work with verification and DFT teams to ensure design integrity. Use tools like Cadence Innovus, Synopsys ICC2. Generate and validate physical design sign-off reports. Qualifications: Bachelors/Masters in Electrical or Computer Engineering. Proficiency in physical design flows and EDA tools. Knowledge of STA, IR drop, EM analysis.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications Bachelors - Electronics Engineering 4-8 Years hands on experience in PDN Signoff using Redhawk / RHSC / Voltus at block level / SOC Level. IR Signoff CPU/high performance cores Signal EM & Power EM Signoff for Chip TOP level & Block level CPU/DSP and other HMs Development of PG Grid spec for different HM Validating the PG Grid using Grid Resistance & Secondary PG Resistance Checks Validating the IR Drops using Static IR , Dynamic IR Vless & VCD Checks for validating Die & Pkg Components of IR Drops Working with SOC and Packaging Teams on Bumps Assignments / RDL Enablement / Pkg Routing Optimizations to improve overall PDN Design Good knowledge on PD would is desirable. Python , Perl , TCL Skill Set Hands on experience in PDN Signoff using Redhawk / RHSC / Voltus at block level / SOC Level. Good understanding on Power Integrity Signoff Checks. Proficient in scripting languages (Tcl and Perl). Familiarity with Innovus for RDL / Bump Planning/PG eco . Ability to communicate effectively with multiple global cross-functional teams. Tools Redhawk , Redhawk_SC and basic use case of Innovus/ Fusion Compiler Power Planning/Floor planning ,Physical Verification hands on experience is added advantage. LSF /compute optimization understanding. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.