439 Physical Design Jobs - Page 6

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -4+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Position Summary Complex SOC Top Physical Implementation for next generation SoCs by means of Synthesis, Place and Route, STA, timing and physical signoffs Role and Responsibilities Hands on experience doing physical design and timing closure of complex blocks and full-chip designs Should have strong understanding of timing, power and area trade-offs and optimization of PPA Power user of industry standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ Expertise in block level and full-chip SDC cleanup, Synthesis optimization, Low Power checking and logic equivalence checking Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scaling) Familiar with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions Familiar in hierarchical design, top-down design, budgeting, timing and physical convergence Skills and Qualifications Experience in top level floorplanning including partition shaping and sizing, pin placement, channel planning, high speed signal and clock planning and feed-through planning is a plus Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level Should have gone through 4+ recent successful SoC tape-outs Should have 8 14 years of experience in physical implementation and design

Roles and Responsibilities Complex SOC Top Physical Implementation for next generation SOCs in area of mobile application processors, modem sub-systems and connectivity chips by means of Synthesis, Place and Route, STA, timing and physical signoffs Hands on experience doing physical design and timing closure of complex blocks and full-chip designs Experience in top level floor planning including partition shaping and sizing, pin placement, channel planning, high speed signal and clock planning and feed-through planning is a plus Should have strong understanding of timing, power and area trade-offs and optimization of PPA Power user of industry standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ Expertise in block level and full-chip SDC clean up, Synthesis optimization, Low Power checking and logic equivalence checking Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scaling) Familiar with typical SOC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions Familiar in hierarchical design, top-down design, budgeting, timing and physical convergence Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level Should have gone through recent successful SOC tape-outs Experience 5+ Years of experience Qualifications B.Tech/B.E/M.Tech/M.E

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures todays innovators stay Ahead of Whats Possible . Learn more at www.analog.com and on LinkedIn and Twitter (X) . Job Responsibilities Implementing RTL to GDS2 flow Floor-planning, Placement, CTS, Routing using physical design tools Synthesis, LEC Debugging timing constraints , Static timing analysis as part of Physical Design flow Extraction, Physical Verification(LVS/DRC) Crosstalk analysis, EM/IR analysis Position requirements BE/BS/Mtech/M.E degree in Electrical/Electronics/Computer science from a reputed institute 2-6 years of relevant experience Hands on experience doing physical design and timing closure of complex blocks Strong understanding of timing, power and area trade-offs and optimization of PPA Knowledge of clock tree synthesis optimization to meet latency, skew goals Understanding timing Constraints and debugging through PD flow Knowledge of Design Margins timing corners, Timing analysis and signoff timing closure Good Debugging skills in resolving Congestion and Timing, SI/CrossTalk Analysis and Write Timing/Functional ECOs Exposure in signoff Power, IR and Physical Verification at both block and chip level is desirable Experience with scripting and automation - Perl/Tcl/shell and implementation flows Good verbal and written communication skills to work effectively with teams spread geographically

Overview About Business Unit: A consolidated team of database technology professionals, we provide expertise across all major database engines and Big Data solutions to support Epsilon products and platforms. The team has a unique alignment that combines a horizontal organizational structure with vertically aligned sub-groups dedicated to our clients. By adhering to consistent standards and best practices, the team ensures operational excellence and has close ties with product teams at Oracle, IBM, Cloudera, Amazon and Microsoft. Seeking a highly motivated and well-rounded Senior Oracle DBA with a strong development background to be part of a fast-paced production support and full-lifecycle implementation team. Candidate is expected to be familiar with database architecture, logical and physical design, automation, documentation, installs, shell scripting, PL/SQL programming, backup recovery concepts, and database performance and tuning. Candidate must have good analytical, verbal, and written skills. Click here to view how Epsilon transforms marketing with 1 View, 1 Vision and 1 Voice. Responsibilities Full life cycle support of clients database(s). Database system uses RAC and non-RAC for OLTP and warehouse, Active DataGuard for DR, partitioning on 12c and 19c on premises and cloud environment. Responsible for database backups, design, development, testing, and performance tuning. Will work with developers to design and build new structures to support application enhancements and promote database changes throughout the Dev, UAT and Prod databases. Responsible for quarterly patch applications (PSU) and periodic database upgrades with minimal downtime in database environment. Required to participate in 24x7 on-call rotation and be available to perform periodic after-hours support. Proactively think toward automation of repeated tasks. Qualifications 6+ years of related experience with implementation and administration of database systems. Bachelor Degree or equivalent experience required. Able to administer, manage and tune high-transaction Standalone/RAC production server environment(s) on premises and cloud environments. Able to understand and meet needs of end users. Able to work with multiple project in a dynamic, fast paced and often changing environment. Strong design, development, administration skills. Strong knowledge on managing Automatic storage management. Strong analytical and troubleshooting skills for complex database performance issues using AWR/ASH/ADDM/TKPROF/SQLT/10046 tracing/OSWatcher/CHM etc. Strong knowledge of database upgrade/migrations. Strong knowledge in using Backup and recovery tools(RMAN/EXPDP/IMPDP) Strong knowledge of Oracle DataGuard Physical Standby configuration, build and support including DataGuard Broker and replication. Knowledge on database programming and query troubleshooting. Knowledge on Oracle Enterprise Manager. Experience in managing Database in AWS cloud environment. Experience in Oracle Exadata Experience in writing Shell scripts. Have good written/oral communication and soft skills. Oracle certification can be plus. Additional Information Epsilon is a global data, technology and services company that powers the marketing and advertising ecosystem. For decades, we ve provided marketers from the world s leading brands the data, technology and services they need to engage consumers with 1 View, 1 Vision and 1 Voice. 1 View of their universe of potential buyers. 1 Vision for engaging each individual. And 1 Voice to harmonize engagement across paid, owned and earned channels. Epsilon s comprehensive portfolio of capabilities across our suite of digital media, messaging and loyalty solutions bridge the divide between marketing and advertising technology.

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe , CXL , and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . Job Summary: As a Static Timing Analysis (STA) Engineer at Astera Labs, you will play a pivotal role in ensuring our digital ASIC designs meet stringent timing and performance requirements, with a strong emphasis on Design for Test (DFT). You will be responsible for timing analysis, identifying critical paths, and driving timing closure across complex ASICs and chiplets. This is a unique opportunity to contribute to the development of cutting-edge silicon for AI infrastructure. Key Responsibilities: Collaborate with design and architecture teams to define and refine timing constraints for DFT across complex ASICs and chiplets. Perform timing analysis and signoff in all DFT modes using industry-standard tools such as PrimeTime. Analyze and resolve timing violations, with a focus on test modes and scan paths. Integrate and validate timing constraints from third-party IPs and external vendors. Generate detailed timing reports, highlighting violations and providing optimization recommendations. Work closely with RTL, physical design, DFT, and verification teams to resolve timing-related issues. Contribute to the development and enhancement of STA methodologies, flows, and automation. Demonstrate a professional attitude with the ability to prioritize tasks, plan effectively for meetings, and work independently with minimal supervision. Exhibit an entrepreneurial mindset and a can-do attitude, acting quickly and decisively with the customer in mind. Collaborate effectively with cross-functional and globally distributed teams. Basic Qualifications: Bachelor s degree in Electrical or Computer Engineering with 8+ years of ASIC experience, or a Master s degree with 6+ years. Proven experience with block- and full-chip timing constraints, including test modes. Strong understanding of DFT architectures and hands-on experience closing timing specifically for DFT. Experience integrating third-party IPs and managing associated timing constraints. Proficiency in STA tools such as PrimeTime and scripting for automation. Preferred Qualifications: Experience with automated constraint generation and validation tools. Familiarity with high-speed interfaces such as PCIe, CXL, and DDR. Strong communication and collaboration skills in cross-functional, globally distributed teams. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

About Marvell . Your Team, Your Impact Central Engineering (CCDS) - ASIC India in Marvell is a Custom Logic Design and Methodology group responsible for delivering complex ASIC chips. This group provides technology development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology and design. You will be working with this team to directly enable customer DFT requirements. What You Can Expect The candidate Marvell is looking for will have: Very good knowledge on SCAN/ATPG/JTAG/MBIST Good Knowledge and understanding on JTAG for IEEE1149. 1/6 standards Proficiency in Industry standard Tools for Scan insertion, ATPG, MBIST and JTAG. (Preferably Synopsys/Mentor tools) Proven experience on Test structures for DFT, IP Integration, ATPG Fault models, test point insertion, coverage improvement techniques Proven experience in Scan insertion techniques at block level and Chip top level Good hands on experience on Memory BIST generation, Insertion, verification on RTL/Netlist level Cross domain knowledge to resolve DFT issues with design, synthesis, Physical design, STA team Good knowledge on Perl/ Tcl scripting Proven experience on gate level simulations with notiming and SDF based simulations Experience with Post-Si ramp up and debug on ATE Very good team player capabilities and excellent communication skills to work with a variety of teams across the global organization High sense of responsibility and ownership within the team for successful Tapeout and Post -Si ramp up of the project. What Were Looking For Bachelor s degree in Computer Science, Electrical Engineering or related fields and at least 5 years of related professional experience. Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-4 years of experience. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

THE ROLE: Join AMD as we push the boundaries of whats possible in graphics and compute technology. We are seeking a talented RTL Physical Design Engineer to contribute to the development and optimization of our cutting-edge CDNA and RDNA graphics IP. This role involves transforming sophisticated RTL designs into robust and efficient physical layouts, critical to the performance of our next-generation graphics and compute solutions. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Key Responsibilities: Physical Design Implementation: Translate complex CDNA and RDNA graphics IP RTL designs into optimized physical layouts. Utilize industry-leading EDA tools for synthesis, place-and-route (PnR), and physical verification processes to take the design thru mock-taepout Performance Optimization: Focus on power, performance, and area (PPA) optimization to meet the stringent requirements of high-performance graphics and compute products. Collaborate with architecture and front-end design teams to align RTL design with physical constraints and objectives. Verification and Timing Closure: Conduct static timing analysis (STA) to ensure robust timing closure and sign-off for graphics IP. Implement and verify design rule checks (DRC), layout versus schematic checks (LVS), and power grid analysis tailored to CDNA and RDNA requirements. Collaboration and Communication: Work closely with cross-functional teams, including architects, RTL designers, and verification engineers to ensure seamless integration and functionality of graphics IP cores. Provide feedback and suggest improvements to design methodologies and processes to push the technology envelope further. Documentation and Reporting: Maintain comprehensive design documentation, methodologies, and updates. Prepare detailed reports on design progress, performance metrics, and any technical challenges encountered. PREFERRED EXPERIENCE: Domain Expertise: Experience with working on complex design and optimizing for performance, power, and area. Technical Proficiency: Proven track record in RTL synthesis, place-and-route (PnR), and static timing analysis (STA) for complex IP cores. Proficiency with industry-leading EDA tools, such as Synopsys Design Compiler, Cadence Innovus, and timing analysis tools like PrimeTime. Experience with low-power design methodologies and techniques for high-performance graphics IP. Design and Verification: Successful completion of full-chip sign-off, including design rule checks (DRC) and layout versus schematic (LVS) checks. Strong skills in signal integrity analysis, including crosstalk and IR drop evaluations. Process Technology: Experience working with advanced semiconductor process nodes (e.g., 7nm, 5nm, or below). Knowledge of process-related challenges and optimization techniques for graphics applications. Scripting and Automation: Proficiency in scripting languages such as Perl, Python, or TCL to automate design flows and improve efficiency. Experience developing and maintaining scripts for design rule checks and optimization processes. Problem-Solving and Innovation: Demonstrated ability to solve complex design challenges using innovative approaches. A track record of contributing to the improvement of design techniques and methodologies in a graphics-focused engineering team. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

As a member of the AECG Custom ASIC Group, you will help bring to life cutting-edge designs. As a member of the physical integration and verification team , you will work closely with the physical design implementation, IP teams and fab contacts to achieve quality tapeout and first pass silicon success. THE PERSON: A successful candidate will work on full chip SoC physical integration, verification and tapeout with physical design engineers. The candidate is expected to be detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Drive Full chip physical integration and verification (DRC/LVS, ERC, DFM checks) Work with fab and fab contacts for all the tapeout activities leading to final tapeout. Work closely with physical design implementation and signoff team to achieve faster TAT Work closely with CAD team to come up with new flows and methodologies in the physical verification domain PREFERRED SKILLSET: Experience : More that 12 years of relevant experience. Driven multiple tapeouts across different technology nodes Sound knowledge of full chip physical integration and verification flows Hands on experience on industry standard tools such as Calibre and ICV Sound understanding for DRC/LVS decks. Should be able to make updates as required. Good in scripting languages such as Tcl and Perl Self driven, positive attitude and team worker ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Job Details: : Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design. Participates in the definition of architecture and microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Works with IP providers to integrate and validate IPs at the SoC level. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: A bachelors degree in electrical/computer engineering, Computer Science or related field with 6+ years of experience (or) a masters degree with 4+ years of experience. Preferred Qualification: Relevant experience with skills in SoC flows, RTL integration and Globals (Clocking, Boot/Reset/Fabrics, DfD, Fuse, etc). Experience in subsystem design and HSIO protocols such as PCIe, UCIe is a plus. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Job Details: : In this position, you will be working in a team of enthusiastic engineers on High Speed Designs in P and R from RTL to GDSII. You will be part of ACE Group, in the P-Core design team driving Intels latest CPUs in the latest process technology. Your responsibilities will include but not limited to: Meet the design targets of high performance and low-power digital design.Static timing analysis. Power OptimizationDesign Convergence Experience at IP, SoC level. Ability to work in a highly dynamic environment across geographies. Back end design and implementation of new features. Post silicon performance push activities. PPA improvement and Methodology improvements Qualifications: You must possess a Masters Degree in Electrical or Computer Engineering with atleast 8 or more years of experience in related field or a Bachelors Degree with at least 10 years of experience. Technical Expertise in Synthesis, Placement, CTS, Post-Route Optimization and P and R tools (CDNS and SNPS) Preferred Qualifications- Familiarity with Verilog/ VHDL - Tcl, Perl, Python scripting Strong verbal and written communication skills Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core , and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. *

Job Details: : You will be part of ACE India , in the P- Core design team driving Intels latest CPUs in the latest process technology. In this position, you will be working in a team of enthusiastic engineers on High Speed Designs in PNR from RTL to GDSII. Your responsibilities will include but not limited to:Meet the design targets of high performance and low-power digital design.Static timing analysis.Power Optimization.Design Convergence Experience at IP, SoC level.Ability to work in a highly dynamic environment across geographies.Back end design and implementation of new features.7Post silicon performance push activities. Qualifications: You must possess a Masters Degree in Electrical or Computer Engineering with atleast 6 or more years of experience in related field or a Bachelors Degree with at least 8 years of experience. Technical Expertise in Synthesis, Placement, CTS, Post-Route Optimization and P and R tools (CDNS and SNPS) . Preferred Qualifications- Familiarity with Verilog/ VHDL - Tcl, Perl, Python scripting. Strong verbal and written communication skills Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. *

Job Details: : Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams. Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT. Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU. Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. Qualifications: Qualifications: B.Tech with 3+ years or M.Tech with 2+ Years of hands-on experience with end-to-end SD flow - synthesis to GDS using industry standard EDA tool, with a proven track record of successful projects. Has good understanding on timing methodology, constraints building etc. Experience in floorplaning concepts and actual work, and integration of hierarchical design Good understanding and experience with multiple power domains designs. Have hands on experience on LV flow and clean up. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Job Details: : Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification. Qualifications: Candidates must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. listed below would be obtained through a combination of Industry job-relevant experience, internship experiences and or schoolwork/classes/research. Education Requirement- Bachelors degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 6-8 years of industry work experience, or- Masters degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 5-7 years of industry work experience, or- PhD in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 4 years of related work experience. Minimum Qualifications- 4+ years of experience in relevant Pre-Silicon validation position having gone through multiple project cycles to gather in-depth experience. 4+ years of experience in logic design verification with various tools and methodologies including System Verilog, Perl, OVM/UVM, logic simulators, and coverage tools. 4+ years of experience with pre-silicon simulation tool flows such as Synopsys VCS Verdi and DVE. 4+ years of experience in OVM/UVM for developing verification test benches and constrained random verification. Preferred Qualifications- Experience with PCIe, Power Management, Ethernet, Network packet processing. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Job Details: : Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. listed below would be obtained through a combination of Industry job-relevant experience, internship experiences and or school work/classes/research. Education Requirement- Bachelors degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 10+ years of industry work experience, or- Masters degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 9+ years of industry work experience, or- PhD in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 8+ years of related work experience.Minimum Qualifications- 9+ years of experience in relevant Pre-Silicon validation position having gone through multiple project cycles to gather in-depth know how. Solid work experience in designing, verifying, and validating complex hardware systems. Solid programming skills in C/C++, Verilog, System Verilog, UVM, assembly, and Python. Proficient in debugging SOC, fabric, NOC, memory, various protocols like PCIE or Ethernet, or other complex ASIC designs. Knowledge of advanced computer architecture and micro-architecture concepts. Experience with writing directed and random test cases. Experience with design verification and validation methodologies and strategies. Good communication skills, and a team player. Able to work independently in a fast-paced team and environment. Desired - Deep knowledge of system architecture including CPU, Data path packet processing flows , Boot Flows, fabrics, interconnects, NOC, memory sub-systems, I/O peripherals (UART/SPI), bus protocols (AXI/APB), PCIE, Ethernet, DMA etc. Experience with boot, reset, clock and power management. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and and problem-solving skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 8+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL/Test Pervassive Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -8+ years of relevant experience - At least 1 generation of processor core/cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

We are seeking a highly skilled and experienced DFT Engineer to join our dynamic team of engineers to develop the next-generation Flash Controllers. As an SoC DFT Engineer, you will be responsible for defining and implementing industry leading DFT solutions, with emphasis on SCAN, MBIST, BSDL etc. The ideal candidate will have a deep understanding of DFT Architecture, Implementation flow, MBIST, SCAN ATPG & Simulation expertise. ESSENTIAL DUTIES AND RESPONSIBILITIES: DFT Architecture definitions for SoC development Leading complex activities and providing solutions for complex DFT problems. Collaborate with cross-functional teams to define and refine SoC DFT requirements, ensuring alignment with industry standards and customer needs. Working closely with the Design, Verification, Physical Design & Test Engineering teams while guiding them on the test requirements and methodologies. Work closely with the Product Engineering team and understand the test requirements, get involved in complex silicon debugs. Evaluate all aspects of the SoC DFT flow from requirements, through detailed definitions, and work closely with the CAD to continuously improve the DFT methodology. Qualifications B.Tech / M,Tech / Phd in Electronics, Computer science or Electrical Engineering Minimum 15+ years of experience in DFT Strong understanding of DFT Architecture

Job Title: Physical Design Engineer PnR / STA Location: Bangalore Experience: 6 - 10 Years Notice Period: 015 Days (Immediate joiners preferred) Job Type: Full-Time | Onsite Job Description: We are looking for a skilled Physical Design Engineer with strong experience in Place & Route (PnR) and Static Timing Analysis (STA) to join our growing silicon engineering team. The ideal candidate will take ownership of block-level or full-chip implementation and timing closure for high-performance, low-power SoCs. Key Responsibilities: Drive RTL to GDSII flow for block-level or full-chip implementation Perform floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification (LVS/DRC) Execute timing closure using PrimeTime (STA) and handle multi-mode, multi-corner (MMMC) analysis Develop and optimize power, performance, and area (PPA) Collaborate closely with RTL, DV, DFT, and backend teams to resolve implementation and timing issues Work on advanced node technologies (7nm/5nm/3nm) with signoff-quality methodologies Create scripts for flow automation and report generation Required Skills: Hands-on experience with industry-standard tools (Innovus, ICC2/Fusion Compiler, PrimeTime, RedHawk/Voltus) Strong knowledge of PnR flow , STA , RC extraction , and signal/power integrity Solid understanding of timing constraints (SDC) and timing exceptions Familiarity with low-power design techniques, multi-voltage domains, and UPF Experience with scripting languages: Tcl , Perl , Python Strong problem-solving skills and ability to work in a fast-paced team environment Preferred Qualifications: Bachelor’s/Master’s degree in Electronics, Electrical, or VLSI Engineering Tapeout experience on multiple SoC designs Exposure to hierarchical and flat design methodologies Why Join Us? Work on high-volume SoCs with leading semiconductor teams Exposure to cutting-edge EDA tools and latest technology nodes Transparent career growth path and technical mentorship Competitive compensation and work-life balance.

We're hiring passionate Physical Design Engineers Freshers! Get hands-on training, work on live projects, and grow your VLSI career. B.Tech (ECE/EEE, 2021, 2024). MTech (2022-2025) Apply: pdfresher.siliconus@gmail.com Annual bonus Health insurance Provident fund

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are meticulous about Power, Performance and Area while driving schedule and managing cost. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 16+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe , CXL , and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . As an Astera Labs Principal DFT (Design for Test) Engineer, you will be part of the DFT Design team that develops the next generation of Astera Labs connectivity products that support the world s leading cloud service providers and server and networking OEMs. In this role, you have exposure and be responsible for the full product life cycle, from definition to mass production to end of life of the products. You will be working closely with all engineering teams, physical design and functions like back-end testing, manufacturing, defect, and reliability analysis. This employee must be team oriented with a focus on solving problems in a collaborative manner between multiple engineering teams. Basic qualifications: Minimum of bachelor s degree in computer engineering/ electrical engineering, Masters preferred. Minimum 8+ years of experience in a semiconductor company as a DFT engineer Must be local or willing to relocate Required experience : Chip design, Verilog and System Verilog Verification, UVM methodology ATPG tools Scan insertion tools Gate-level simulations Static timing analysis Scripting (Perl/Tcl) Familiarity with ATE Hands-on expertise with commercial test generation tools for large complex designs Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression Experience running test compression software Experience using the Mentor Tessent or synopsys DFT Max and Tetramax tools Preferred experience: Experience with defining and implementing SOC level verification on large designs. Working with 93k Tester Experience with IEEE 1500 Standard or IEEE 1687 standard and MBIST, LBIST Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

The Opportunity Were looking for the Wavemakers of tomorrow. What youll need: Good understanding of overall design Flow RTL to GDS. Must have 14+ years of experience on signing off the full chip synthesis/STA for tape outs Hands on Experience on Both Block level and Full chip timing Constraints Development and Management for hierarchical designs. Deep Understanding of DFT Constraints. Hand on Synthesis & STA Experience on Lower node Technologies with Synopsys/Cadence Tools. good understanding of overall ASIC Physical Design/DFT, Tools and implication on Timing Convergence Must have in-depth understanding of relevant areas of Library / Memory / Other collaterals and dependencies on STA Must understand Ultra Submicron issues, Variation aware/Aging Aware Design Sign-off Must understand CTS/Other clock Distribution methodologies well. Good knowledge on Timing Budgets. Knowledge on Perl / TCL / Python scripting language Experience on multi voltage designs using CPF/UPF. Good understanding on timing/area/power/complexity tradeoffs on complex interface design Hands on experience on power analysis using PTPX Good understanding of VHDL / Verilog Constructs. Familiarity with IP level verification and strong RTL debugging capabilities is an added bonus A, enthusiastic team player who enjoys working with others Experience troubleshooting issues with users Experience communicating updates and resolutions to customers and other partners complex technical concepts to other design peers in verbal and written form What Youll Do: We are looking for experienced STA engineer to lead the timing convergence of the SoCs.Responsibilities include STA setup, convergence, reviews and sign-off for Multi-Mode and Multi-corner Multi voltage domain designs. Constraint Generation & Maintenance for Block / SOC for complex hierarchical Designs for all the Modes Timing analysis, and timing closure at Full chip level while supporting the PD team on Block/SS level timing convergence. Interaction with Design, DFT, IP&PD teams for Timing Convergence & Resolving Constraint Conflicts. Support Verification team to enable GLS. Guide the CTS strategies and provide feedback to Implementation Team. Manage the timing ECO generation and strategize the implementation methodology. Develop Automation scripts with-in STA tools for Methodology development. You will be reporting to Director - ASIC engineering. We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Exp : 3- 5 Yrs Position : Senior or Lead Expertise : Power fundamentals Good knowledge of PTPX Good knowledge of CLP Knowledge of design verification, RTL coding, synthesis, and physical design Protocol knowledge of , DDR, CHI, Cache, computer organization, bus protocol, Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. We are hiring across mutliple roles in the below domain: 1. Physical Design 2.RTL Design 3. Design Verification 4. STA/ Synthesis 5. DFT 6. FPGA Emulation 7. Validation