1691 Physical Design Jobs - Page 6

As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems. Your role will encompass a wide range of tasks including working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge products. You will collaborate with cross-functional teams to meet performance requirements and develop innovative solutions. **Key Responsibilities:** - Lead a high performing team of engineers in the implementation domain for Display Sub-System - Manage multiple time-critical and complex projects effectively ...

As an Implementation Engineer at Kinara, a Bay Area-based venture backed company, you will play a crucial role in leading and executing Synthesis and Static Timing Analysis (STA) for complex AI SoC designs with multi-mode and multi-power domain functionalities. Your responsibilities will include: - Conducting Synthesis and STA to ensure the quality and reliability of our products - Optimizing designs for low power and high performance with logically equivalent RTL - Implementing ECOs for functional and timing closure - Working with multi-clock, multi-power domain designs and multi-mode timing constraints - Inserting DFT and collaborating with different functional teams like RTL Design, DFT, ...

Role Overview: You will be part of a team that focuses on developing custom silicon solutions for Google's direct-to-consumer products, contributing to the innovation and advancement of products used globally. Your role will be instrumental in shaping the future of hardware experiences by enhancing performance, efficiency, and integration. Key Responsibilities: - Lead a team of Register-Transfer Level (RTL) engineers in IP development, including planning tasks, conducting code and design reviews, and developing features within the IP. - Collaborate with the architecture team to create implementation strategies (e.g., microarchitecture and coding) that meet quality, schedule, and Power Perfor...

10–20 yrs exp in ASIC/SoC Physical Design. Must have hands-on PnR, STA, CTS, floorplanning, tapeout exp. Strong tool skills & team leadership a must. Location: Bangalore (priority)/Chennai/Hyderabad/Noida. Required Candidate profile PD engineer with 10+ yrs in ASIC/SoC design. Skilled in floorplanning, PnR, STA, CTS, tapeouts. Strong in timing closure, tool expertise & team mentoring. Prefers Bangalore, open to other metros.

As a senior physical design engineer, your role involves mentoring and coaching junior team members throughout the design process. You will provide technical guidance and support, ensuring optimal design quality and performance. Your responsibilities include: - Reviewing and providing feedback on floorplans, placement, and routing strategies. - Guiding the team in achieving timing closure targets through effective analysis and optimization techniques. - Collaborating with cross-functional teams to address design challenges and meet project goals. - Developing and maintaining best practices for physical design implementation. - Staying updated with industry trends and advancements in physical...

Role Overview: You are expected to execute any sized customer projects independently with minimum supervision and guide team members technically in any field of VLSI Frontend Backend or Analog design. As an Individual contributor, you will take ownership of any one or more tasks/modules related to RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, Signoff, etc. and lead the team to achieve results. Your responsibilities will include completing assigned tasks successfully and on-time within the defined domain(s), anticipating, diagnosing, and resolving problems, coordinating with cross-functional teams as necessary, ensuring on-time quality...

Arm is leading the vision to unlock a broad ecosystem of silicon required for AI, Data centers, mobile, compute and IoT. As a member of Solution engineering, you will be joining a team developing CAD solutions to develop tools flows for end2end convergence. Work with front-end and physical implementation SoC and core design teams on design architecture, interfaces, timing and power requirements for power/MHz efficiency. Major focus on solutions scalability across advanced technodes and PPA trade-offs. The position requires delivering solution for both internal and 3rd party IP integration. The position also gives opportunity for leading product level implementation. Responsibilities: CAD sof...

We are seeking a highly motivated and experienced SoC technical lead to join our team in developing SoCs based on ARM technology. The candidate will be responsible for delivery of multitude of SOCs The ideal candidate person will have demonstrated experience as a leader to influence and drive SOC teams. The candidate should have technical leadership along with ability and desire to be hands on in all phases of development. Lead the development of various SOC s from concept to production Collaborate with multi-functional and geographically spread-out teams including software, architecture, and hardware teams to develop high-quality and timely execution. Work multi-functionally to define robus...

SUMMARY Retail Staff Opportunity for Freshers ===================================== Summary ----------- We are seeking enthusiastic and motivated individuals to join our retail team as Retail Staff. As a Retail Staff member, you will play a vital role in ensuring the smooth operation of our retail stores, providing excellent customer service, and maintaining a visually appealing store environment. This is an excellent opportunity for freshers to gain hands-on experience in the retail industry and develop valuable skills. Responsibilities - - - - - - - - - - - - - - - - - - - Folding and stacking merchandise at the basic table Timely display of received stocks to maintain a visually appealing...

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with ...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: The responsibility includes:-. -Independent planning and execution of Netlist-to-GDSII. -Good understanding of basics of static timing analysis. -Well versed with the Block level and SOC level timing closure (STA) methodologies, ECO generation and predictable convergence. -Should be able work in close collaboration with design, DFT and PNR team and resolve issues wrt constraints validation, verification, STA, Physical design, etc. -Should have good exposure to high frequency multi voltage design convergence. -Good understanding of clock networks. -Circuit level comprehension of timing critical paths in the...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Enginee...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Enginee...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Enginee...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Enginee...

He/She should be able to do block level / top-level floor planning, PG Planning, partitioning (for hierarchical designs) , placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks and be able to fix the violations . S hould have worked on 4 5nm , 28nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design eng inee rs. Interface with front-end ASIC teams to resolve issues. Excellent comm...

General Summary: We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. As a CPU Micro-architecture and RTL Design Engineer, you will work with chip architects to conceive of the micro-architecture, and also help with architecture/product definition through early involvement in the product life-cycle. Roles And Responsibilities Performance exploration. Explore high performance strategies working with the CPU modeling team. Microarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification. RTL ownership. Development, assessment and r...

Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. PD JD: Thorough knowledge of the ASIC designs Place and Route flow and methodology. Hands-on experience in executing complete PD ownership from netlist to GDS2 including HM level...

Position: PD CAD Engineer (SI80FT RM 3639) Key Responsibilities: Develop and support automated physical design (PD) CAD flows, including floorplanning, placement, and routing optimization. Customize and optimize physical design flows using industry-standard EDA tools (such as Synopsys Fusion Compiler, Cadence Innovus). Collaborate with the design and CAD teams to improve PD workflows, ensuring robust and efficient flow from RTL to GDSII. Implement automation scripts using TCL, Perl, and Python to improve flow reliability and reduce design cycle time. Perform tool evaluations and benchmarking to keep PD flows up-to-date with the latest EDA advancements. Provide documentation, training, and su...

Experience in ASIC/SoC Physical Design & STA implementation (Synthesis to GDSII). EDA tools - Synopsys: Design Compiler, ICC2, PrimeTime. Cadence: Innovus, Tempus, TCL, Perl, Python, Shell STA concepts — setup/hold analysis, OCV/AOCV, SI, & Crosstalk

Key Responsibilities: Lead the architecture, design, and integration of SoC-wide clocking networks including clock generation (PLLs, DLLs), distribution, gating, and domain crossing strategies. Define and optimize power-performance-area (PPA) trade-offs for complex clocking and circuit topologies. Collaborate cross-functionally with RTL, physical design, verification, and DFT teams to deliver end-to-end SoC clocking and custom IP. Own the technical roadmap and methodology improvements for clocking, timing closure, and custom circuits. Mentor and technically guide a team of junior and senior designers. Review and approve specifications, schematics, simulations, and post-layout signoff for hig...

Roles and Responsibilities: Perform RTL-to-GDSII implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure. Work on P&R flows using tools such as Cadence Innovus / Synopsys ICC2 . Handle timing analysis and sign-off using PrimeTime / Tempus . Perform power planning, IR-drop, and EM analysis to meet reliability targets. Execute DFM closure DRC/LVS/ANT checks using Calibre . Implement ECOs for timing, functionality, and metal fixes. Work closely with front-end, verification, and DFT teams to ensure full-chip integration and timing convergence. Optimize Power, Performance, and Area (PPA) for block- and top-level designs. Contribute to flow automa...

Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5-8 years industry experience in physical design methodology. Good knowledge and hands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical ...

Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8-10 years of industry experience in physical design methodology. Good knowledge and hands-on experience in physical design methodology, which includes logic synthesis, placement, clock tree synthesis, routing. Should be knowledgeable in phy...