1246 Physical Design Jobs - Page 7

3 years Service Agreement Experience: 0 - 4 years Role & responsibilities: Responsible for development and support of Projects. Responsible for debugging the source codes in Verilog, SV, and UVM. Responsible for Monitoring the trainee's progress. Will be a point of contact for trainees to query on Technical concepts. Preferred candidate profile Freshers Sound Knowledge on Verilog, SV, Digital ,UVM / Back-end design. Physical Design, Analog Good communication skill. Should be good in Digital Electronics. 3 years Service Agreement.

Job Purpose To handle and provide solution for a transactional activities of field team and making sure the implementation of projects are end to end satisfying the requirement. Duties and Responsibilities 1.Resolving SFDC functions related issues2.Resolving BRE level issues3.Educating internal and field teams on issues due to training requirements4.Constant observations on the issues raised by the field team5.Raising regular IT request to resolve issues6.Constant communication between IT and Product teams to identify the changes7.Attending bi-weekly meetings with IT to find the bigger solution8.Find solutions to the repetitive problems and submit BRD9.Interacting with field teams to identif...

Job Purpose This position is open with Bajaj Finance ltd To handle and provide solution for a transactional activities of field team and making sure the implementation of projects are end to end satisfying the requirement Duties and Responsibilities Resolving SFDC functions related issues2 Resolving BRE level issues3 Educating internal and field teams on issues due to training requirements4 Constant observations on the issues raised by the field team5 Raising regular IT request to resolve issues6 Constant communication between IT and Product teams to identify the changes7 Attending bi-weekly meetings with IT to find the bigger solution8 Find solutions to the repetitive problems and submit BR...

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with ...

Lead and develop timing methodologies, establish SDC constraints, and automate processes for special timing checks, ensuring design convergence and managing ECOs effectively. Perform static timing analysis setup and sign-off for multi-corner, multi-voltage processes to align with PPA targets, initially at the hierarchical level and subsequently at the top-level, reviewing the timing arcs for the .lib generation. Collaborate closely with RTL, DFT, and IP teams to ensure smooth integration and address physical design concerns affecting scan shift and scan capture modes for DFT. Identify opportunities to optimize clock skew and insertion delay across various corners and modes. Evaluate the cloc...

Engineer with a good attitude, strong analytical skills, effective communication, and excellent problem-solving abilities. KEY RESPONSIBILITIES: Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure. Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA. Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM/IR and signoff. Handling differen...

THE ROLE: The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collab...

If you have an experience developing RTL for IP or subsystems and understand architectural specifications, this role is for you. You will be responsible for IP and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively with the IP/SoC team. Key Responsibilities: Design of IP and subsystems with integration of AMD and other 3rd party IPs Perform quality checks (lint, CDC, and power rule checks) of power-gated digital designs Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC Work in partnership with SOC teams to support the IP at S...

The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are meticulous about Power, Performance and Area while driving schedule and managing cost. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, C...

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing ...

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Work with IP SOC teams across all our sites (GFX, Memory controller, Multimedia engines, IOs, PCIE ) to understand the features and create verification plans Will help scoping out the testbench architecture and the simulation configuration, test planning, coverage planning etc Will develop system config and initialization sequences to various system configurations at the SOC Will work with Graphics/IO IP team and verify some of the grap...

AMD seeks a passionate, collaborative leader with strong technical skills and the initiative to motivate an expert team. You will manage aSilicon Engineeringgroup and innovate with internal teams and external partners to create the next generation of computing technologies. THE PERSON: The ideal candidate has experience leading others in technical and managerial settings. You also have excellent communication, writing, and presentation skills. KEY RESPONSIBILITIES: ASIC design verification experience 12+ years Verification of high performance x86-core ISA features Architecting and development of testbench, test-bench components for high performance Cache, x86 ISA features, clock/reset/power ...

Engineer with good attitude who seeks new challenges and has good analytical and and problem-solving skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player who hasexcellent communication skills and experience collaborating with other engineers located in different sites/timezones. KEY RESPONSIBILITIES: Working on static timing analysis setup and signoff of multi-corner multi-voltage designs. Owning timing execution to meet timing requirements including timing budgeting, repeater planning, constraints/exceptions generation and management Areas of focus include Timing analysis and verification, extraction and noise glitch analysis Engaging clos...

The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are meticulous about Power, Performance and Area while driving schedule and managing cost. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, C...

The position will involve working with a very experienced CPU physical design team. The person is responsible for delivering the physical design of critical CPU units to meet challenging goals for frequency, power, and other design requirements for AMDs next-generation processors in a fast-paced environment with cutting-edge technology. THE PERSON: Engineer with a good attitude, strong analytical skills, effective communication, and excellent problem-solving abilities. KEY RESPONSIBILITIES: Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff Understand the micro-architecture to perform feasibility studies...

As a Silicon Design Engineer in the AMD AECG ASIC TFM (tools Flows Methodology) team, you will work with design experts (FE and BE) to come up with the best implementation methodologies/flows and work on development and support of the FE/BE flows. KEY RESPONSIBILITIES: Define and drive key Frontend/Beckend/Physical Design methodologies. Partner with AMD CAD Teams, Design team, physical design teams to ensure seamless end to end design flows. Work with existing development teams to define roadmaps for existing flows and assist in difficult technical debug. Work closely with design teams to gather requirements and develop strategies to tackle key technical problems. Work on Floor-plan, Physica...

The ideal candidate for this role should possess a Bachelor's degree or equivalent practical experience along with a minimum of 2 years of experience in developing and maintaining STA constraints and scripts. It is essential to have prior experience working collaboratively in a team of DFT engineers, specifically with Register-Transfer Level (RTL) and Physical Designer Engineers. Preferred qualifications for this position include a Bachelor's or Master's degree in Electrical Engineering or Computer Science, or relevant practical experience. The candidate should have at least 6 years of experience in Static Timing Analysis with exposure to mixed signal design. Proficiency in flow methodology ...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Job Overview : We are seeking an exceptional Physical Verification Engineer to take a key role in oursemiconductor design team. As a Block/Fullchip/Partition Physical Verification Engineer , you willResponsible for development and implementation of cutting-edge physical verification methodologiesand flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensurethe successful delivery of high-quality designs Responsibilities : Drive physical verification DRC, Antenna, LVS, ERC at cutting edge FinFET technology nodesfor various foundries. Physical verification of a complex SOC/ Cores/ Blocks DRC, LVS, ERC, ESD, DFM, Tape out. Work hands-on to solve critical ...

Requirements :Bachelors or Masters Degree with a strong VLSI BackgroundMinimum 3 years of experience in the area of Synthesis Synthesis Engineer: (3-10 Years)Key Responsibilities:Synthesis Environment setupValidating synthesis SDC qualityUtilize Synthesis tool variables and methodologies to extract the best area/power achievable for the process node Checking the synthesis DEF qualityAnalyze critical timing violation groups and congestion solve them by finetune floorplan or placement constraints Compare area/power with previous projects and check current project results DFT Insertion and debugging basic DFT issues Discuss directly with Design teams & Physical design teams to get the best synt...

Define and drive netlist-level power estimation methodologies using industry-leading tools (e.g., Synopsys PrimeTime PX, Cadence Voltus). Establish and maintain correlation frameworks between RTL and gate-level power, and between estimated and silicon power. Develop automated flows for toggling activity generation, vector-based and vectorless power estimation, and regression reporting. Analyze power consumption trends and identify hotspots; provide recommendations for low-power design optimization. Collaborate with RTL design, physical design, DFT, and architecture teams to ensure early and accurate power signoff. Lead methodology development for corner analysis, dynamic/static power separat...

RESPONSIBILITIES:Responsible for Multi Voltage domain STA environment setup, execution and timing closure Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checksEnsuring timing correlation between PnR STA and timely feedbacks to PD teamGenerating block level HS session and using Top context from SoC for Block-SoC Interface timing closure Generating timing ECO using Tweaker/PrimeClosure

Responsible for mobilizing youth for training programs and ensuring successful placement through employer engagement and community outreach. ","responsibilities":" Mobilize youth and conduct outreach Counsel and enroll candidates Coordinate placements and employer interactions Maintain placement records and follow-ups Support training and center operations ","eligibility":" Graduate in any discipline 02 years experience in mobilization or placements ","