432 Physical Design Jobs - Page 5

Technical Skill Set - SOC level Floor Plan, PNR, IO Ring Design, Timing Closure, Physical Verification, Power planning and analysis, ECOs on 7nm and 10nm technology nodes. Must-Have Hands-on experience on Full chip floor plan, Full chip PNR, and Design Partitioning. Hands-on experience in IO Planning, Bump Plan and RDL Routing. Experience in ECOs, Synthesis and STA, and Power analysis. Hands-on experience in Physical verification. Hands-on experience on 7nm and 10nm technology nodes. Good-to-Have Effective communication skills to interact with cross-functional teams.

Role & responsibilities Those who had a chance to work on CPU, GPU and / or NPU would be better on 3 or 5 nm Technology . Experience Levels would 4-8 years.

Design analog and mixed-signal modules in CMOS and Smart PowerTechnologies, with a particular focus on achieving high-efficiency power conversion for applications using GaN devices. Job Description Design analog and mixed-signal modules in CMOS and Smart PowerTechnologies , with a particular focus on achieving high-efficiency powerconversion for applications using GaN devices. D esign and verify pre-silicon analog/mixed-signal integrated circuitblocks , including incorporating features for testing and quality assurance, and providing support for top-level integration. Assist in defining the requirements for analog and mixed-signalblocks , aligning them with IP Module architecture, and ensuring compliance with requirements through documentation. Estimate effort and planning design work packages to meet project milestones. Provide essential support to physical design engineers, post-silicon verification, production testing , and other critical activities extending beyond the design phase. You are best equipped for this task if you have: A masters degree in electrical/Electronic Engineering, Physics or equivalent field of studies. Experience in analog and mixed-signal circuit design, particularly in CMOS and Smart Power Technologies. Good Analytical skills and very good understanding of Analog Design. Familiarity with high-efficiency power conversion, such as DC-DC converters, is highly desirable. Experience in pre-silicon verification and with System Verilog would be a plus. Proficiency in computer-aided design tools and methodologies. Excellent problem-solving and communication skills. Ability to work effectively in a collaborative team environment. Detail-oriented with a commitment to quality and precision. Fluency in English

Design analog and mixed-signal modules in CMOS and Smart PowerTechnologies, with a particular focus on achieving high-efficiency power conversion for applications using GaN devices. Job Description In your new role you will: Design analog and mixed-signal modules in CMOS and Smart PowerTechnologies , with a particular focus on achieving high-efficiency power conversion for applications using GaN devices. Design and verify pre-silicon analog/mixed-signal integrated circuit blocks , including incorporating features for testing and quality assurance, and providing support for top-level integration. Assist in defining the requirements for analog andmixed-signal blocks , aligning them with IP Module architecture, and ensuring compliance with requirements through documentation. Estimate effort and planning design work packages to meet project milestones. Provide essential support to physical design engineers,post-silicon verification, production testing , and other critical activities extending beyond the design phase; Your Profile You are best equipped for this task if you have: A masters Degree in Electrical/Electronic Engineering, Physics or equivalent field of studies. Experience in analog and mixed-signal circuit design, particularly in CMOS and Smart Power Technologies. Good Analytical skills and very good understanding of Analog Design. Familiarity with high-efficiency power conversion, such as DC DCconverters, is highly desirable. Experience in pre-silicon verification and with System Verilog wouldbea plus. Proficiency in computer-aided design tools and methodologies. Excellent problem-solving and communication skills. Ability to work effectively in a collaborative team environment. Detail-oriented with a commitment to quality and precision. Fluency in English

You have a passion for modern, complex processor architecture, digital design as we'll as verification/design quality. You are a team player who has excellent communication skills, strong analytical & problem-solving skills and are willing to learn and ready to take on problems. A global mindset and ability to work in a multi site environment are keys to being successful in this role. KEY RESPONSIBILITIES: RTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design Architect and design of power management features, cache, coherency. Design optimization for implementing power efficient IP, implementing the RTL using low power techniques Responsible for the inter IP integration issues resolution Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem. Work closely with DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design Architecting, micro-architecting and documentation of the design features Lead design team from all aspects of the RTL deliverables. Mentor the junior members of the RTL team to meet the team goals Represents AMD to the outside technical community, partners and vendors Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion. PREFERRED EXPERIENCE: 12+ years of experience in Digital IP/ASIC design and Verilog RTL development Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification. Should be we'll versed with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation. Expert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects. Should possess expertise in front-end EDA tools sign-off and its flows. Familiarity with low power design and low power flow is an added plus. Ability to program with scripting languages such as Python or Perl is a plus; Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements; Proven interpersonal skills, leadership and teamwork; Excellent writing skills in the English language, editing and organizational skills required; Skilled at prioritization and multi-tasking; Good understanding of engineering terminology used within the semiconductor industry; Good understanding of digital design concepts; Knowledge of, or experience in, functional design verification or design is highly desired. ACADEMIC CREDENTIALS: masters degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or VLSI design Engineering.

As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineer s . The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning P REFERRED EXPERIENCE : Understanding of Design for Test methodologies and DFT verification experience ( eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc .) Experience with Mentor testkompress and/or Synopsys Tetramax /DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

ARF Design Pvt Ltd is looking for Physical Design Engineer/Lead to join our dynamic team and embark on a rewarding career journey The Physical Design Engineer is responsible for designing and implementing the physical layout of integrated circuits (ICs) using industry-standard tools and methodologies Participate in design reviews and provide input on design trade-offs, performance targets, and optimization strategies Excellent communication and collaboration skillsStrong analytical and problem-solving skillsFamiliarity with scripting languages, such as Tcl, Perl, or Python

: We are looking for a highly skilled & experienced PD expert to join our Flows & Methodologies team. The candidate must be experienced, hands-on and have robust understanding of physical design including Floorplan, Power-plan, Place & Route, UPF, CTS. This role requires strong analytical skills, attention to detail, and the ability to work collaboratively with cross-functional teams. Proficiency in relevant EDA tools and a solid understanding of digital design principles are essential for success in these positions Scope of Responsibilities: As part of the Design Enablement team of the organization, you need to work closely with SoC cross functional teams to develop and define Physical Design methodology to meet SoC & IP level objectives on low geometry nodes (3/5/16nm) Your scope of work will cover tools and flows definition, requirement management for SoC Place & Route, UPF, Formal Verification, Floorplan & Power-Plan You will work with EDA Vendors to proactively review latest tools and flows offerings in Physical Implementation domains. Evaluate latest offerings and benchmark with organization used tools, flows, and methodologies. Work with EDA Vendors to review and resolve blocking issues You will be an actor of change for deploying new tools & methodologies across the organization Qualifications Specific skills & knowledge : Bachelor or Master or Ph. D. in Electronics Engineering and specialization in VLSI domain 10+ years of hands-on experience in Physical Design : UPF, Formal & Physical verification, floorplan, power-plan, Place & Route Proven experience in delivering physical implementation closure methodology ensuring timing & physical convergence Experience in Synopys & Cadence tool sets (Fusion Compiler, Innovus) , low geometry node issues, working with EDA team in reviewing & resolving blocking issues in project Experience in customizing flows & methodology to meet low power & area objectives of SoC Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Can - do attitude, openness to new environment, people and culture Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus Ability to work independently and as part of a team

Roles and Responsibilities Good experience in PD execution of multiple medium to High critical blocks/HMs from Netlist to GDSII Develop and qualify the methodology and implementation flow in advanced technologies like 14nm and below. Well versed with FC/Innovus tools and good understanding of place/cts/Route critical settings Develop expertise in ASIC Synthesis, Floor Planning, STA (Static Timing Analysis), and other relevant technologies. Good experience in Low power designs Conduct thorough analysis of designs to identify potential issues and implement solutions. Perform physical design activities including floor planning, PNR (Physical Netlist) creation, and timing closure using Innovus tools. Interested candidates can contact me at shubhanshi@incise.in

Your Job The engineer will be responsible for doing physical design implementation, timing closure, and Physical verification at the block level. Job Responsibilities Execute block-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Need experience in full chip physical design such as integration of blocks, top level floorplanning, clock tree synthesis, timing constraints development and convergence. I/O placement and constraints. Experience with UPF coding and modification as per design requirements. Need to take care of all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out. Should be able to interface with the Front End Design team to resolve Design Issues Must possess hands on experience in P&R from RTL to GDS including timing closure and Physical verification. Design experience in all aspects of physical design. Proficient and powerful user of Synopsys ICC/ICC2, Cadence innovus. Experience in Mentor Calibre tools to run Physical verification Experience in Apache to run EM IR- analysis is a Plus. Experience in Tcl/ Tk, PERL, Makefile is a Plus Excellet verbal and written communication skill is required. Excellent interpersonal and analytical skills with an ability to work independently and within a team are required. Highly motivated, excellent team player, and customer oriented. Experience 4-6 Years of Physical Design Experience Qualification Bachelor or Master's degree in Electrical and Electronics engineering. Required Skills And Qualification Good understanding of low power concepts. Good exposure in Floorplanning, CTS, STA, Physical Verification. Good understanding of top-level physical design, partitioning and timing constraints, IR Drop. Basic understanding of timing constraints. Knowledge in Automation script (TCL, Perl, etc), Auto FuSA would be an added advantage.

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 12+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

- Lead the architecture, design and development of Processor Core Vector- Scalar Execution unit for high-performance IBM Systems. - Architect and design Fixed point/Floating point/Vector/SIMD/Crypto instructions of a high performance processor CPU - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise - 8 or more years of demonstrated experience in architecting and designing Execution unit of CPU - Hands on experience of implementing Arithmetic/Crypto/SIMD functions - Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - At least 1 generation of Processor Core silicon bring up experience - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of instruction dispatch and load/store units - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of one object oriented language and scripting language - Understanding of Agile development processes - Experience with DevOps design methodologies and tools Preferred technical and professional experience Master's Degree/PhD

BE Mechanical/Electrical with 6-10 years of experience in the Energy/Manufacturing sector/Auto Sector Preferred candidates from high voltage industry Candidates will be responsible for - Procurement from Import and Domestic (Timely placement of PO's, ensuring on time delivery, incoterm, optimizing freight, timely forecasting etc) Procurement of casting ,machining, sheet metal, fabrication, electrical articles & equipment's (CT/VT/Panels etc)for production (assembly) ensuring freight optimization & product cost out for high voltage GIS(Gas Insulated Switchgear) upto 400kv. Inventory management -Ensuring ITR targets Built safety stocks for Delivery, quality critical parts ensuring lead times Initiate & drive cost out measures Explore new suppliers & expedite development Maintain business relationship with all supplier for best outcome Travelling /Visit to suppliers required. (As per business requirement) Excellent Communication skills (Written/Oral)

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Aprisa offers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. The detail-route-centric architecture and hierarchical database enable fast design closure and optimal quality of results at a competitive runtime. This role is based in Bangalore. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. This is your role Lead a Team of Engineers working on solving the latest design challenged in Logic Synthesis Collaborate with RnD and drive the roadmap for next generation RTL2GDSII solution. Work with design community in solving critical designs problems to achieve desired performance, area and power targets. Deployment of Synthesis solution with various customers working on cutting edge technologies (7nm and forward). Develop & deploy training and technical support to customers using Siemens EDA tools. We don’t need superheroes, just superminds! Typically requires minimum of 9+ years of experience in Logic Synthesis flows Proficiency in Verilog, System Verilog & VHDL. Strong knowledge of RTL2GDSII flow with strong fundamentals in digital design & implementation. Prior experience in IC digital design flows and front-end EDAT tools including Synthesis, DFT, Formal Verification, Logic Equivalence Checks Hands-on experience using commercial synthesis tools like Synopsys-DC/FC, Cadence-Genus is a must. Experience with advance technology nodes 7nm and below. Hands-on experience in debug & deliver solutions to critical design issues related to synthesis. TCL, Perl or Python scripting is a plus. Self-motivated team player with a zeal to drive high team performance. Good problem solving and debugging skills. Strong verbal & written communication skills We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #LI-EDA #LI-Hybrid

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more efficiently. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Position presents an opportunity to join the award winning and market leading Tessent team, India. The focus of the role is advanced design-for-test (DFT) insertion and automatic test pattern generation (ATPG) for semiconductor designs. It will involve understanding and supporting the latest DFT ATPG electronic design automation (EDA) technologies such as Tessent TestKompress and Streaming Scan Network (SSN). Someone in this role will gain a deep understanding of scan design, on-chip clock controls, and IJTAG infrastructure in support of scan testing. They will support the worldwide application engineering team on complex ATPG issues and build testcases for advanced DFT methodologies. This role is based in Noida. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. Responsibilities for this role include: Build and deliver in-depth technical presentations, develop training material, white papers, supplied articles, and application notes. Work with customers as well as Siemens stakeholders such as regional application engineers, global support engineers, and marketing. Are you expertized in working through complex technical issues and independently building solutions and new methodologies! Explain complex principles in simple terms to broad audiences. Some travel, domestic and international. Successful deployment of existing and new Tessent DFT products in customer designs by enabling AEs. Working closely with our key customers on deployment challenges. Working with PEs and R&D to ensure new product readiness testcase in form of testcases, documentation and trainings. Architecture reviews of customer designs. Closely working with AEs to gather top issues blocking their engagement's success. Deep learning opportunities for Tessent DFT products including opportunities to present at various conferences worldwide including ITC and Siemens U2U. We don’t need hard workers, just superminds! BS degree (or equivalent) in Electrical Engineering, Computer Science or related field is required with 10 - 15 years of experience. Knowledge of design logic design languages, tool usage, design flow steps required. We are looking for someone that has exposure to DFT or SoC design for complex ASICs / SOCs. ATPG, IEEE 1687 IJTAG, boundary scan (BSCAN), hierarchical DFT implementation. Knowledge of a scripting language like TCL. We need someone self-motivated and dedication to improvement with strong problem-solving skills. Excellent organizational skills, written and verbal English language communication skills. Proficiency in LINUX and Windows environments. The role presents many opportunities to build specialized DFT and ATPG knowledge. Publications and other promotions of methodologies is encouraged. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #LI-EDA #LI-HYBRID

We are seeking a highly skilled and experienced Synthesis and Static Timing Analysis (STA) expert to join our semiconductor team. The ideal candidate will have a strong background in digital design and a deep understanding of synthesis and STA processes. This role involves working closely with cross-functional teams to ensure the successful implementation and optimization of digital designs. Key Responsibilities: Good Understanding of RTL, Synthesis, LEC, VCLP, Timing Constraints Generation, UPF, Timing Closure and Signoff. Develop TCL scripts and design constraints to perform synthesis, DFT insertion, and static timing analysis. Interface for DFT strategy and implementation. Responsible for design convergence in timing and logic equivalence. Experience with EDA tools like Genus, Fusion Compiler, Primetime, Tempus, LEC, VCLP. Knowledge of scripting languages such as Perl, Python, or TCL. Qualifications Exp : 5 to 12 years of experience Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

As a Logic design lead in the IBM Systems division, you will be responsible for the micro architecture, design and development of a high-bandwidth, low-latency on-chip interconnect (NoC) and chip-to-chip interconnect and integration into high-performance IBM Systems. Design and architect different interconnect topologies as driven by bandwidth, latency and RAS requirements Develop the features, present the proposed architecture in the High level design discussion Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW teams to develop the feature Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in silicon bring-up and validation of the hardware Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8+ years of relevant experience - At least 1 generation of processor interconnect design delivery leadership (eg UPI, axi, amba, NoC). - Expertise of SMP coherency - Experience in different on-chip interconnect topologies (e.g., mesh, crossbar) - Understanding of various snoop and data network protocols - Understanding of latency & bandwidth requirements and effective means of implementation - Working knowledge of queuing theory - numa/nuca architecture - Proficient in HDLs- VHDL / Verilog - Experience in High speed and Power efficient logic design -Experience in working with verification, validation, physical design teams for design closure including test plan reviews and verification coverage - Good understanding of Physical Design and able to collaborate with physical design team for floor planning, wire layer usage and budgets, placement of blocks for achieving high-performance design - Experience in leading uarch, RTL design teams for feature enhancements.

Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Required technical and professional expertise 5-8 years industry experience in physical design methodology. Good knowledge andhands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical verification ( LVS,DRC. etc), Noise analysis, Power analysis and electro migration . Team player with good problem solving skills, communication skills and leadership skills. Preferred technical and professional experience Automation skills in PYTHON, PERL , and/or TCL

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -4+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Position Summary Complex SOC Top Physical Implementation for next generation SoCs by means of Synthesis, Place and Route, STA, timing and physical signoffs Role and Responsibilities Hands on experience doing physical design and timing closure of complex blocks and full-chip designs Should have strong understanding of timing, power and area trade-offs and optimization of PPA Power user of industry standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ Expertise in block level and full-chip SDC cleanup, Synthesis optimization, Low Power checking and logic equivalence checking Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scaling) Familiar with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions Familiar in hierarchical design, top-down design, budgeting, timing and physical convergence Skills and Qualifications Experience in top level floorplanning including partition shaping and sizing, pin placement, channel planning, high speed signal and clock planning and feed-through planning is a plus Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level Should have gone through 4+ recent successful SoC tape-outs Should have 8 14 years of experience in physical implementation and design

Roles and Responsibilities Complex SOC Top Physical Implementation for next generation SOCs in area of mobile application processors, modem sub-systems and connectivity chips by means of Synthesis, Place and Route, STA, timing and physical signoffs Hands on experience doing physical design and timing closure of complex blocks and full-chip designs Experience in top level floor planning including partition shaping and sizing, pin placement, channel planning, high speed signal and clock planning and feed-through planning is a plus Should have strong understanding of timing, power and area trade-offs and optimization of PPA Power user of industry standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ Expertise in block level and full-chip SDC clean up, Synthesis optimization, Low Power checking and logic equivalence checking Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scaling) Familiar with typical SOC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions Familiar in hierarchical design, top-down design, budgeting, timing and physical convergence Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level Should have gone through recent successful SOC tape-outs Experience 5+ Years of experience Qualifications B.Tech/B.E/M.Tech/M.E

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures todays innovators stay Ahead of Whats Possible . Learn more at www.analog.com and on LinkedIn and Twitter (X) . Job Responsibilities Implementing RTL to GDS2 flow Floor-planning, Placement, CTS, Routing using physical design tools Synthesis, LEC Debugging timing constraints , Static timing analysis as part of Physical Design flow Extraction, Physical Verification(LVS/DRC) Crosstalk analysis, EM/IR analysis Position requirements BE/BS/Mtech/M.E degree in Electrical/Electronics/Computer science from a reputed institute 2-6 years of relevant experience Hands on experience doing physical design and timing closure of complex blocks Strong understanding of timing, power and area trade-offs and optimization of PPA Knowledge of clock tree synthesis optimization to meet latency, skew goals Understanding timing Constraints and debugging through PD flow Knowledge of Design Margins timing corners, Timing analysis and signoff timing closure Good Debugging skills in resolving Congestion and Timing, SI/CrossTalk Analysis and Write Timing/Functional ECOs Exposure in signoff Power, IR and Physical Verification at both block and chip level is desirable Experience with scripting and automation - Perl/Tcl/shell and implementation flows Good verbal and written communication skills to work effectively with teams spread geographically

Overview About Business Unit: A consolidated team of database technology professionals, we provide expertise across all major database engines and Big Data solutions to support Epsilon products and platforms. The team has a unique alignment that combines a horizontal organizational structure with vertically aligned sub-groups dedicated to our clients. By adhering to consistent standards and best practices, the team ensures operational excellence and has close ties with product teams at Oracle, IBM, Cloudera, Amazon and Microsoft. Seeking a highly motivated and well-rounded Senior Oracle DBA with a strong development background to be part of a fast-paced production support and full-lifecycle implementation team. Candidate is expected to be familiar with database architecture, logical and physical design, automation, documentation, installs, shell scripting, PL/SQL programming, backup recovery concepts, and database performance and tuning. Candidate must have good analytical, verbal, and written skills. Click here to view how Epsilon transforms marketing with 1 View, 1 Vision and 1 Voice. Responsibilities Full life cycle support of clients database(s). Database system uses RAC and non-RAC for OLTP and warehouse, Active DataGuard for DR, partitioning on 12c and 19c on premises and cloud environment. Responsible for database backups, design, development, testing, and performance tuning. Will work with developers to design and build new structures to support application enhancements and promote database changes throughout the Dev, UAT and Prod databases. Responsible for quarterly patch applications (PSU) and periodic database upgrades with minimal downtime in database environment. Required to participate in 24x7 on-call rotation and be available to perform periodic after-hours support. Proactively think toward automation of repeated tasks. Qualifications 6+ years of related experience with implementation and administration of database systems. Bachelor Degree or equivalent experience required. Able to administer, manage and tune high-transaction Standalone/RAC production server environment(s) on premises and cloud environments. Able to understand and meet needs of end users. Able to work with multiple project in a dynamic, fast paced and often changing environment. Strong design, development, administration skills. Strong knowledge on managing Automatic storage management. Strong analytical and troubleshooting skills for complex database performance issues using AWR/ASH/ADDM/TKPROF/SQLT/10046 tracing/OSWatcher/CHM etc. Strong knowledge of database upgrade/migrations. Strong knowledge in using Backup and recovery tools(RMAN/EXPDP/IMPDP) Strong knowledge of Oracle DataGuard Physical Standby configuration, build and support including DataGuard Broker and replication. Knowledge on database programming and query troubleshooting. Knowledge on Oracle Enterprise Manager. Experience in managing Database in AWS cloud environment. Experience in Oracle Exadata Experience in writing Shell scripts. Have good written/oral communication and soft skills. Oracle certification can be plus. Additional Information Epsilon is a global data, technology and services company that powers the marketing and advertising ecosystem. For decades, we ve provided marketers from the world s leading brands the data, technology and services they need to engage consumers with 1 View, 1 Vision and 1 Voice. 1 View of their universe of potential buyers. 1 Vision for engaging each individual. And 1 Voice to harmonize engagement across paid, owned and earned channels. Epsilon s comprehensive portfolio of capabilities across our suite of digital media, messaging and loyalty solutions bridge the divide between marketing and advertising technology.

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe , CXL , and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . Job Summary: As a Static Timing Analysis (STA) Engineer at Astera Labs, you will play a pivotal role in ensuring our digital ASIC designs meet stringent timing and performance requirements, with a strong emphasis on Design for Test (DFT). You will be responsible for timing analysis, identifying critical paths, and driving timing closure across complex ASICs and chiplets. This is a unique opportunity to contribute to the development of cutting-edge silicon for AI infrastructure. Key Responsibilities: Collaborate with design and architecture teams to define and refine timing constraints for DFT across complex ASICs and chiplets. Perform timing analysis and signoff in all DFT modes using industry-standard tools such as PrimeTime. Analyze and resolve timing violations, with a focus on test modes and scan paths. Integrate and validate timing constraints from third-party IPs and external vendors. Generate detailed timing reports, highlighting violations and providing optimization recommendations. Work closely with RTL, physical design, DFT, and verification teams to resolve timing-related issues. Contribute to the development and enhancement of STA methodologies, flows, and automation. Demonstrate a professional attitude with the ability to prioritize tasks, plan effectively for meetings, and work independently with minimal supervision. Exhibit an entrepreneurial mindset and a can-do attitude, acting quickly and decisively with the customer in mind. Collaborate effectively with cross-functional and globally distributed teams. Basic Qualifications: Bachelor s degree in Electrical or Computer Engineering with 8+ years of ASIC experience, or a Master s degree with 6+ years. Proven experience with block- and full-chip timing constraints, including test modes. Strong understanding of DFT architectures and hands-on experience closing timing specifically for DFT. Experience integrating third-party IPs and managing associated timing constraints. Proficiency in STA tools such as PrimeTime and scripting for automation. Preferred Qualifications: Experience with automated constraint generation and validation tools. Familiarity with high-speed interfaces such as PCIe, CXL, and DDR. Strong communication and collaboration skills in cross-functional, globally distributed teams. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

About Marvell . Your Team, Your Impact Central Engineering (CCDS) - ASIC India in Marvell is a Custom Logic Design and Methodology group responsible for delivering complex ASIC chips. This group provides technology development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology and design. You will be working with this team to directly enable customer DFT requirements. What You Can Expect The candidate Marvell is looking for will have: Very good knowledge on SCAN/ATPG/JTAG/MBIST Good Knowledge and understanding on JTAG for IEEE1149. 1/6 standards Proficiency in Industry standard Tools for Scan insertion, ATPG, MBIST and JTAG. (Preferably Synopsys/Mentor tools) Proven experience on Test structures for DFT, IP Integration, ATPG Fault models, test point insertion, coverage improvement techniques Proven experience in Scan insertion techniques at block level and Chip top level Good hands on experience on Memory BIST generation, Insertion, verification on RTL/Netlist level Cross domain knowledge to resolve DFT issues with design, synthesis, Physical design, STA team Good knowledge on Perl/ Tcl scripting Proven experience on gate level simulations with notiming and SDF based simulations Experience with Post-Si ramp up and debug on ATE Very good team player capabilities and excellent communication skills to work with a variety of teams across the global organization High sense of responsibility and ownership within the team for successful Tapeout and Post -Si ramp up of the project. What Were Looking For Bachelor s degree in Computer Science, Electrical Engineering or related fields and at least 5 years of related professional experience. Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-4 years of experience. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1