Physical Design Engineer

Intel

10 - 15 years

11 - 16 Lacs

bengaluru

Posted:17 hours ago| Platform:

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Skills Required

physical design perl tcl python timing closure static timing analysis soc route3 routing drc soc design synthesis sta eda primetime lvs rtl floor planning dft pnr vlsi placement eda tools power integrity clock tree synthesis

Work Mode

Work from Office

Job Type

Full Time

Job Description

Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing
Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis
Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking
Analyzes results and makes recommendations to fix violations for current and future product architecture
Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools
Optimizes design to improve productlevel parameters such as power, frequency, and area
Participates in the development and improvement of physical design methodologies and flow automation

Qualifications:

Minimum Educational Qualifications:B Tech/M Tech in Electrical/VLSI/Computer science with relevant experiencePreferred Qualifications:At least 10+ years of experience in physical design using industry EDA tools
Lead Sub System/SOC physical design for at least 1 product
Experience in Python/Perl/TCL programming languages
Experience in signoff domains (timing, IR-RV
Power, Layout Verification) is an added advantage

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