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Best NanoTech
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Physical Design Engineer

Physical Design Engineer

Best NanoTech

15 years

0 Lacs

bengaluru karnataka india

Posted:1 week ago| Platform:

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Skills Required

design layout manufacturing power timing signal flow planning routing synthesis analysis integrity verification fabrication resolve constraints drc lvs automation macros scripting tcl python perl management leadership electrical engineering synopsys cadence communication

Work Mode

On-site

Job Type

Full Time

Job Description

Physical Design Engineer (5–15 years experience)Job Title: Physical Design Engineer (ASIC / SoC / Mixed-Signal)Experience: 5 – 15 yearsLocation: Bangalore

About The Role

We are seeking a skilled Physical Design Engineer to join our back-end / layout / implementationteam. The candidate will be responsible for translating RTL/netlist designs into physical layoutsready for manufacturing, optimizing for performance, power, area (PPA), timing closure, signalintegrity, and manufacturability.Key Responsibilities

Lead the full physical design flow from netlist to GDSII/layout — including floor-

planning, placement, routing, clock-tree synthesis (CTS), routing and layout
optimizations.

Perform static timing analysis (STA), timing closure, power, signal integrity, IR/EM

analysis, and ensure design meets power, area, performance, and manufacturability
constraints.

Work with design, verification, and manufacturing teams to ensure smooth hand-off to

fabrication; resolve physical design issues, constraints, DRC/LVS and sign-off checks.

Develop and maintain design flows, automation scripts, layout macros, and physical

design methodologies — including scripting (TCL, Python, Perl, Shell) and flow
automation.

Optimize design for PPA (power, performance, area), power management (e.g. low-

power design techniques), and manufacturability.

Provide technical leadership/guidance to layout team members; mentor juniors;

participate in design & timing closure reviews.

Required Qualifications & Skills

Bachelor’s or Master’s degree in Electrical / Electronics / Computer Engineering or

related field.

5 to 15 years’ hands-on experience in physical design/layout for ASIC/SoC (digital or

mixed-signal) — preferably with tape-out experience.

Proficiency with industry standard physical design and EDA tools (e.g. Synopsys ICC2 /

Innovus / Cadence / Mentor tools for P&R, STA, sign-off).

Strong scripting skills (TCL, Perl, Python, Shell) for flow automation.
Good understanding of VLSI design flow, timing analysis, power/area optimization,

clock-tree synthesis (CTS), routing, signal & power integrity, DRC/LVS rules, and
manufacturability constraints.

Excellent analytical, problem-solving, and communication skills; ability to collaborate

across design, verification and manufacturing teams.

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Physical Design Engineer