431 Drc Jobs

BE Mechanical/Electrical with 6-10 years of experience in the Energy/Manufacturing sector/Auto Sector Preferred candidates from high voltage industry Candidates will be responsible for - Procurement from Import and Domestic (Timely placement of PO's, ensuring on time delivery, incoterm, optimizing freight, timely forecasting etc) Procurement of casting ,machining, sheet metal, fabrication, electrical articles & equipment's (CT/VT/Panels etc)for production (assembly) ensuring freight optimization & product cost out for high voltage GIS(Gas Insulated Switchgear) upto 400kv. Inventory management -Ensuring ITR targets Built safety stocks for Delivery, quality critical parts ensuring lead times Initiate & drive cost out measures Explore new suppliers & expedite development Maintain business relationship with all supplier for best outcome Travelling /Visit to suppliers required. (As per business requirement) Excellent Communication skills (Written/Oral)

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Aprisa offers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. The detail-route-centric architecture and hierarchical database enable fast design closure and optimal quality of results at a competitive runtime. This role is based in Bangalore. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. This is your role Lead a Team of Engineers working on solving the latest design challenged in Logic Synthesis Collaborate with RnD and drive the roadmap for next generation RTL2GDSII solution. Work with design community in solving critical designs problems to achieve desired performance, area and power targets. Deployment of Synthesis solution with various customers working on cutting edge technologies (7nm and forward). Develop & deploy training and technical support to customers using Siemens EDA tools. We don’t need superheroes, just superminds! Typically requires minimum of 9+ years of experience in Logic Synthesis flows Proficiency in Verilog, System Verilog & VHDL. Strong knowledge of RTL2GDSII flow with strong fundamentals in digital design & implementation. Prior experience in IC digital design flows and front-end EDAT tools including Synthesis, DFT, Formal Verification, Logic Equivalence Checks Hands-on experience using commercial synthesis tools like Synopsys-DC/FC, Cadence-Genus is a must. Experience with advance technology nodes 7nm and below. Hands-on experience in debug & deliver solutions to critical design issues related to synthesis. TCL, Perl or Python scripting is a plus. Self-motivated team player with a zeal to drive high team performance. Good problem solving and debugging skills. Strong verbal & written communication skills We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #LI-EDA #LI-Hybrid

Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Required technical and professional expertise 5-8 years industry experience in physical design methodology. Good knowledge andhands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical verification ( LVS,DRC. etc), Noise analysis, Power analysis and electro migration . Team player with good problem solving skills, communication skills and leadership skills. Preferred technical and professional experience Automation skills in PYTHON, PERL , and/or TCL

The role is that of an ‘Civil Engineer’ and Senior Manager Level Position that will report to the Directors.: The position will require a candidate with good experience in Liaison, preparing BOQs, supervising and getting projects executed. Candidates must have good experience in SRA and/or good comprehension of DRC rules. Candidates must have good knowledge of excel and be proficient in using computers. The Qualifications and the Requirements of the Candidate: Must have Masters Degree in Civil Engineer Must have at least 5 years of experience as an Civil Engineer in Real Estate Industry with Residential & Commercial Projects Knowledge of various building norms, material specifications, market costing Knowledge of AutoCAD and Revit is a must Must be updated in latest market trends and technology advances applicable to the field of Architecture Must have done drawing for Municipal submission and be capable of liaising which liaisons staff for completing municipal required drawing Must have knowledge of preparation of Municipal drawings Fluent in English Job Type: Full-time Pay: ₹600,000.00 - ₹1,200,000.00 per year Benefits: Health insurance Provident Fund Schedule: Day shift Supplemental Pay: Performance bonus Yearly bonus Education: Diploma (Preferred) Experience: Real Estate: 3 years (Required) total work: 5 years (Preferred) Language: English (Required)

Summary About the role: Strive for sustainable growth through supporting and negotiating deals within APMA. Partner with APMA Region and countries Business Development & Licensing teams to analyze, support and successfully close BD&L opportunities which are aligned with APMA business strategy as well as monitor existing deals across deal parameters. Deal types include Exclusive Promotion and Distribution, Co-marketing, Selective Co-promotion (Digital, Channel management), TM divestments and information needs for global in-licensing deals, etc. About the Role Key Requirements: Trusted member of the Deal Team. Support APMA BD Directors and country BD leads by providing independent, high quality financial support to all BD&L transactions including EPDA, Licensing, Divestments, Co-Promotion and other strategic business initiatives. Makes recommendations for financial structure and terms to maximize value to Novartis while minimizing risk. Leads analysis of financial models underpinning deal terms; analyzes deal economics quickly to identify key value drivers and looks at key sensitivities. Specifically responsible for preparation of P&L’s, and financial slides for APMA/Cluster DRC business cases. Collect input from key finance (CFO, FRA, Tax, Funds Flow) stakeholders and incorporate their feedback in term sheet/contract in a timely manner. Takes proactive role in informing negotiations leader of financial issues. Constructively and proactively challenges deal terms which do not meet internal targets or are perceived to be inappropriate in terms of risk to Novartis. Provides key financial inputs to prioritize portfolio strategy and help ascertain short-/mid-/long-term partnering view. Provides financial oversights on existing deals in terms of reporting, tracking and flagging deviations on agreed deal parameters. Responsible to APMA finance dashboard data integrity and timely updates. Support APMA BD Directors for BD activities, including countries teams financial upskilling and capabilities building. Strong communicator with an ability to digest, simplify and present BD&L financials to countries and region management. Essential Requirements: Excellent communication skills, both oral and written, are needed due to coordination and dissemination of important and confidential information. Strong interpersonal skills with ability to build strong partnerships and trust with counterparts. Ability to diplomatically challenge stakeholders within Novartis, from other companies, and from external organizations. Team leadership, project management, and negotiation skills are required. Business knowledge of the pharmaceutical industry including customers and competition is a plus. Desirable Requirements: Minimum of 8-10 years’ experience in finance, accounting, and business operations, MBA will be a plus. Demonstrated superior financial analysis capabilities and superior skills in Excel. 1-2 years of Finance transaction/deal experience is a strong plus, as well as a solid understanding of accounting principles and current IFRS as it relates to BD&L transactions. Candidate must demonstrate initiative, creativity, and ability to work under pressure, often to tight deadlines. Why Novartis: Helping people with disease and their families takes more than innovative science. It takes a community of smart, passionate people like you. Collaborating, supporting and inspiring each other. Combining to achieve breakthroughs that change patients’ lives. Ready to create a brighter future together? https://www.novartis.com/about/strategy/people-and-culture Join our Novartis Network: Not the right Novartis role for you? Sign up to our talent community to stay connected and learn about suitable career opportunities as soon as they come up: https://talentnetwork.novartis.com/network Benefits and Rewards: Read our handbook to learn about all the ways we’ll help you thrive personally and professionally: https://www.novartis.com/careers/benefits-rewards Division Finance Business Unit Universal Hierarchy Node Location India Site Mumbai (Head Office) Company / Legal Entity IN10 (FCRS = IN010) Novartis Healthcare Private Limited Functional Area BD&L & Strategic Planning Job Type Full time Employment Type Regular Shift Work No Accessibility and accommodation Novartis is committed to working with and providing reasonable accommodation to individuals with disabilities. If, because of a medical condition or disability, you need a reasonable accommodation for any part of the recruitment process, or in order to perform the essential functions of a position, please send an e-mail to [email protected] and let us know the nature of your request and your contact information. Please include the job requisition number in your message. Novartis is committed to building an outstanding, inclusive work environment and diverse teams' representative of the patients and communities we serve.

Responsibilities: Assist in the development and validation of PDKs for various process nodes. Support the integration of technology files, DRC/LVS decks, and device models into EDA tools (e.g., Cadence, Synopsys). Write and maintain automation scripts (e.g., Python, TCL, Shell) to streamline PDK development processes. Collaborate with layout, design, and modeling teams to ensure PDK accuracy and usability. Troubleshoot and fix issues in PDK components related to DRC, LVS, parasitic extraction, and schematic symbols. Document PDK features, known issues, and development changes. Show more Show less

Tenstorrent is at the forefront of cutting-edge AI technology, redefining what’s possible in performance, usability, and cost. As AI transforms the computing landscape, it demands integrated innovation across software models, compilers, platforms, networking, and semiconductors. Our team—diverse, curious, and driven—has built a high-performance RISC-V CPU from the ground up and shares a collective passion for advancing AI. We thrive on collaboration and tackling tough challenges, and we’re expanding our team across all experience levels. We’re looking for an experienced CPU/IP / SoC Physical Verification Engineer who can take ownership of full-chip and block-level physical verification across our complex RISC-V based designs. This role is ideal for someone who thrives in a fast-paced, collaborative environment, enjoys solving challenging problems across advanced technology nodes, and is passionate about building clean, manufacturable silicon. What You’ll Be Doing Drive physical verification activities (DRC, LVS, ERC, PERC, Antenna, DFM) from block to full-chip level. Collaborate closely with RTL, PD, CAD, and packaging teams to ensure sign-off readiness. Debug verification issues and work hands-on with tools like Calibre and ICV to root-cause violations. Support ESD planning, padring integration, and bump/RDL layout strategies. Contribute to PV methodology improvements and automation scripts. Lead PV closure for key tapeouts and provide mentorship to junior engineers on the team. Interface with foundry teams for rule deck alignment and tapeout planning. What We’re Looking For 6 to 14 years of hands-on experience in CPU/IP / SoC physical verification. Solid command of physical verification tools and flows (Calibre, ICV, ICC2, Innovus, etc.). Strong understanding of advanced node requirements (7nm, 5nm, 3nm), including FinFET challenges. Proficiency in checking and resolving DRC, LVS, ERC, and PERC violations. Comfortable scripting in Python, TCL, or Perl to automate workflows and debug processes. Awareness of ESD, IR drop, EM, and reliability considerations in full-chip designs. Clear communication and a strong sense of ownership — you enjoy working across teams and taking designs across the finish line. Show more Show less

We are looking for a skilled Standard Cell Layout Engineer with 3 – 5 Years of experience in standard cell, Analog, mixed-signal, and custom digital block layout design using advanced CMOS technologies . The candidate should have strong hands-on experience with Cadence Virtuoso for schematic and layout editing and be proficient in physical verification (DRC/LVS) using tools like Mentor Calibre Position: Standard Cell Layout Engineer Location: Phoenix Aquila, Hyderabad Joining Timeline: Immediate to 15 Days (strict) Key Responsibilities: Develop and optimize standard cell layouts. Perform physical verification and ensure DRC / LVS clean designs. Collaborate with circuit designers and CAD teams. Solve layout issues related to area, performance, and power. Mandatory Skills: Standard cell layout Cadence Virtuoso (Layout L / XL) Physical verification (Mentor Calibre) Knowledge of Electro-Migration, Latch-UP, Coupling, Crosstalk, IR – Drop, Parasitic Analysis, Matching, Shielding Good to Have: Skill coding / layout automation Experience in advanced nodes (e.g., 28nm and below) Strong problem-solving and communication skills Show more Show less

Description Invent the future with us. Recognized by Fast Company’s 2023 100 Best Workplaces for Innovators List, Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team — we’d love to have you apply. Come invent the future with us. About The Role Ampere is seeking a highly skilled and experienced candidate with proven expertise in PHY hardening, particularly in DDR and SerDes, with a focus on digital implementation and convergence. We are looking for a self-motivated individual with a proven track record in hardening state-of-the-art PHYs and contributing to the development of cutting-edge expertise. What You’ll Achieve As a PHY Hardening Engineer, you will collaborate with architects, RTL designers, packaging and PCB design teams, and post-silicon validation groups. This is an exceptional opportunity to showcase your engineering skills in a dynamic, fast-paced environment that fosters innovation and operates at the forefront of technology. High-Speed Digital Design Develop high-speed digital layouts, including DDR and other high-speed interfaces. Expertise in floor planning, bump planning, routing, power grid design, clock design/distribution, and optimization for high-speed digital circuits. Optimize layouts to minimize signal integrity issues, reduce power consumption, and meet timing, power, and manufacturability requirements. Coordinate with PHY vendors for hardening activities and deliverables. Estimate effort and timelines for PHY hardening tasks and provide feedback on timing/PDV. Chip-Level Physical Design Perform chip-level tasks such as floor planning, partitioning, and power/clock distribution. Handle chip assembly and ensure seamless integration of multiple IP blocks into the top-level design. Proficiency in using EDA tools for chip-level physical verification (DRC, LVS, ERC). Collaborate with the packaging team to refine bump placement and package routing considerations. Signal and Power Integrity Familiarity with signal and power integrity concepts in high-performance memory systems. Expertise in managing high-speed signals to mitigate issues like crosstalk, reflection, and signal degradation. Perform thermal and power integrity analysis to ensure reliable designs. Knowledge of advanced packaging techniques and considerations, an added plus Design-for-Test (DFT) Basic understanding of DFT structures, including scan chains, MBIST, and loopback mechanisms. Contribute to DFT-based timing closure activities. About You Bachelor's degree & 8 years of related experience or Master's degree & 6 years of related experience Expertise in floor planning, bump planning, routing, power grid design, clock design/distribution, and optimization for high-speed digital circuits Experience developing high-speed digital layouts, including DDR and other high-speed interfaces Handling chip assembly and ensure seamless integration of multiple IP blocks into the top-level design Proficiency in using EDA tools for chip-level physical verification (DRC, LVS, ERC) Worked with architects and RTL teams to develop physical constraints and optimize their design Integrate PHYs, controllers, and memory stacks into the top-level design Expertise in managing high-speed signals to mitigate issues like crosstalk, reflection, and signal degradation Experience with advanced packaging technologies, such as 2.5D/3D integration, TSV, and interposer-based designs Handle micro-bump design to ensure proper alignment and minimize resistance Understand the SIPI impacts of bump placement Basic understanding of DFT structures, including scan chains, MBIST, and loopback mechanisms Strong communication and articulation skills are required to excel in this role What We’ll Offer At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits Highlights Include Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process. Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law. Show more Show less

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER Full Chip Low Power Design and Signoff Engineer Overview WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities MTS SILICON DESIGN ENGINEER ( Full Chip Low Power Design & Signoff Engineer ) The Role As a member of the Strategic Silicon Solution Group Full Chip Low Power Design and Signoff team, you will help bring to life cutting-edge designs. You will work closely with the Full Chip/Subsystem Floorplan / Netlist, Tile/Block/Partition level Physical Design, Full Chip Static Timing Analysis and Constraints teams, to achieve first pass silicon success. The Person A successful candidate should have minimum 8 to 15 years approximate work experience. He will work closely with Fellows, Principal Engineers, Architects, collaborate with cross functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power design/signoff, and mentor/coach/guide Design Engineers. The candidate should be highly accurate and detail-oriented, possessing good communication and problem-solving skills. Key Responsiblities Expertise in Full Chip Power Delivery Network Design, Implementation and Signoff Must have good understanding of RDL & Power grid design. Must know the NPV Static, Dynamic & SEM Run. Must have good experience of Vectored dynamic, CPM & Ramp up time analysis and current analysis. Must have experience on Full chip, Sub-system level & tile/block/partition level EMIR analysis and signoff Should have good knowledge of package level EMIR analysis. Expertise in low power design and implementation such as clock gating, power gating, power switch implementation and other low power techniques to reduce total power consumption. Should have good knowledge on simulation of special cell’s with target power analysis. Should possess good knowledge of Power switch insertion, Secondary PG design towards improvising PPA. Mentor/coach/guide design engineers to achieve the project goal. Should have hands on experience on tools like Redhawk-SC, ICC2 & Prime Time or equivalent industry standard tools. Should have good scripting experience in Shell, Python, Perl, TCL, UNIX Preferred Experience Understanding of ICC2 or Fusion Compiler Physical Design flows/methodologies or equivalent tools. Expertise on tool expected. Experience in TCL/Python and other languages needed. Should be strong in scripting and decode/debug old existing scripts. Experience with RHSC, PTPX, ICC2, Fusion Compiler Experience with mentoring a team on lower tech node (5/3nm) projects on PDN (EMIR) Experience in Full Chip/Sub-system level Physical Verification including DRC, LVS, DFM, ESD, High voltage checks etc, Academic Credentials Bachelors or Master's degree in Computer/Electronics/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Show more Show less

If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. Our work culture values diversity, social responsibility, open communication, mutual trust and respect. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates. Requisition ID: 74461 Job Description Architects, designs and verifies circuits, logic, systems, algorithms, etc. to meet product requirements Determine design approaches and parameters Develops innovative new designs for patenting or protecting as trade secret Demonstrates good judgment in solving a broad range of issues, based on an advanced understanding of industry practices and company policies and procedures Responsible for custom layout, including overseeing the work of layout designers Reports on design results through design reviews, in accordance with company quality requirements and resolves action items generated as a result of these reviews Attends design reviews to provide input and learn from other designers’ experiences Research design techniques through technical publications and seminars Supports marketing in product definition Having a wide-ranging experience uses professional concepts and company objectives to resolve complex issues in creative and effective way Determines methods and procedures on new assignments and may coordinate the activities of other personnel Job Requirements A technology-related master’s degree or equivalent training and 8 or more years of analog/mixed-signal design experience developing mixed-signal ICs Proven leadership in analog/mixed signal design projects Strong knowledge of engineering fundamentals Advanced knowledge of CMOS fabrication processes Advanced knowledge of MOS transistors and analog/digital circuit design Knowledge of complex AD/DC analysis (poles, zeros, compensation) Advanced signal analysis knowledge Basic understanding of CMOS and BCD parasitic junctions and the risks associated with them Strong parasitic analysis knowledge (capacitance, resistance, power grid) Advanced knowledge of circuit building blocks (e.g., OPAMP, gm-C filters, switch capacitors, ADC, DAC, state-machines, and bus interfaces) Advanced design skills in system modeling Strong knowledge of UNIX, Matlab, and circuit simulation tools Proficiency in layout verification, DRC, LVS Additional skills (one or more of these are highly desirable) Working knowledge of device physics Working knowledge of digital design and design flows System knowledge (e.g., High Performance PLLs) Knowledge of scripting language (python, shell, skill) Advanced laboratory measurement skills (analog, digital) Knowledge of MS Office documentation, spreadsheet, presentation tools or equivalent tools Excellent written and verbal presentation skills Skyworks is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law. Show more Show less

About Nxtwave: NxtWave is founded by Rahul Attuluri (Ex-Amazon, IIIT Hyderabad), Sashank Reddy (IIT Bombay), and Anupam Pedarla (IIT Kharagpur). In February 2023, NxtWave raised ₹275 crore led by Greater Pacific Capital, a leading international private equity firm . The startup is also backed by Orios Ventuares, Better Capital, and marquee angels, including founders of some of India’s unicorns. NxtWave is one of India’s fastest-growing Ed-Tech startups , revolutionizing the 21st-century job market by transforming youth into highly skilled tech professionals irrespective of their educational background with its CCBP 4.0 programs. As an official partner for NSDC under the Ministry of Skill Development & Entrepreneurship, Government of India, and recognized by NASSCOM, Ministry of Commerce and Industry, Government of India, and Startup India, NxtWave has earned a reputation for excellence. The startup has received accolades such as ‘The Greatest Brand in Education’ in a research-based listing by URS Media, a leading international media house. NxtWave has also been honored with the "Startup Spotlight Award 2023" by T-Hub on its 8th Foundation Day. Recently, NxtWave’s founders, Anupam Pedarla and Sashank Gujjula, were honored in the 2024 Forbes India 30 Under 30 for their exceptional contribution to transforming the tech education landscape in India. The edtech brand eliminates the entry barrier to learning tech skills by offering vernacular content and interactive learning. Learning in one’s mother tongue helps achieve higher comprehension, deeper attention, longer retention, and greater outcomes. Presently, NxtWave has paid subscribers from 647+ districts across India. In just 2.5 years, CCBP 4.0 learners have been hired by 1700+ companies , including Google, Amazon, Nvidia, Goldman Sachs, Oracle, Deloitte, and more. Know more about NxtWave: https://www.ccbp.in Our LinkedIn page: Link Next wave of opportunities with 1700+ companies - Link 33M funding news - Link Youtube Channel - Link Impact Stores on LinkedIn - Link Read more about us in the news - Economic Times | CNBC | Yourstory | VCCircle About the Role We are seeking a meticulous and technically proficient Sound Engineer to join our in-house video production team. In this role, you will take ownership of the audio production pipeline , from on-set recording to post-production mixing and mastering. You’ll play a crucial role in ensuring our video content —whether educational masterclasses, brand films, testimonials, or explainers—delivers pristine, immersive audio that complements our high-caliber visuals. Your expertise will directly impact the viewer experience , ensuring clarity , consistency , and professional broadcast quality sound across all our productions. Key Responsibilities On-Set Audio Recording Plan and execute location sound recording , ensuring clean dialogue capture , minimal ambient noise, and optimal mic placement for various video formats. Operate and manage professional audio recording equipment , including shotgun microphones , lavalier systems , audio recorders , boom poles , and wireless audio kits . Conduct sound checks , monitor levels in real time, and troubleshoot issues on set to ensure uncompromised audio capture . Implement best practices for soundproofing and ambient control , particularly in studio environments. Audio Post-Production Perform audio editing , clean-up , mixing , and mastering for all types of video content. Reduce noise, hums, and unwanted frequencies using industry-standard software like Adobe Audition , Pro Tools , or DaVinci Resolve Fairlight . Synchronize audio with video footage, ensuring lip sync accuracy and audio continuity . Design and incorporate sound effects , room tone , and background scores , collaborating with composers or sourcing royalty-free libraries when required. Sound Quality & Consistency Maintain a consistent audio signature and brand sound identity across all videos. Ensure voice clarity , balanced tone , and correct loudness levels , optimized for various platforms (YouTube, LMS, social media, etc.). Implement Loudness Standards (LUFS), Dynamic Range Control (DRC) , and EQ balancing appropriate for the content type. Equipment Management & Workflow Optimization Manage, maintain, and upgrade audio equipment inventory , including microphones, audio interfaces, mixers, and monitoring systems. Recommend and integrate new technologies or tools that enhance recording quality or workflow efficiency. Document and refine audio production workflows , ensuring smooth handoffs between recording, post, and delivery teams. What We’re Looking For Experience : 2+ years as a Sound Engineer , Location Sound Recordist , or Audio Post-Production Specialist in professional video production environments. Technical Proficiency : Mastery of audio recording tools (Zoom F series, Sound Devices MixPre, Rode, Sennheiser, Shure, or equivalent professional microphones). Strong command over DAWs (Adobe Audition, Pro Tools, Fairlight, Logic Pro). Familiarity with audio plugins for noise reduction , de-reverb , EQ , compression , and limiting . Attention to Detail : Acute sensitivity to audio imperfections , pacing , volume consistency , and tonal balance . Problem Solving : Ability to troubleshoot live sound issues swiftly and effectively, ensuring minimal downtime on shoot days. Collaborative Spirit : Comfort working in close coordination with cinematographers , directors , and editors , with a proactive approach to creative problem-solving . Nice to Have Experience with 5.1 Surround and immersive audio formats . Knowledge of Foley recording , ADR , and voiceover session direction . Familiarity with audio for animation and motion graphics projects. Understanding of broadcast standards and delivery formats for OTT, YouTube, and LMS platforms. Why Join Us? At NxtWave , we believe sound is not just an accessory—it’s a driving force behind emotional impact and engagement. As a Sound Engineer , you will have the opportunity to shape the sonic identity of our content, ensuring that every word, every note, and every silence contributes to an exceptional learning and brand experience . You’ll be part of a creative, future-forward team , working on projects that redefine education through cinematic storytelling . Show more Show less

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: MTS SILICON DESIGN ENGINEER THE ROLE: The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 12+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering #LI-PK2 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

JOB DESCRIPTION About KPMG in India KPMG entities in India are professional services firm(s). These Indian member firms are affiliated with KPMG International Limited. KPMG was established in India in August 1993. Our professionals leverage the global network of firms, and are conversant with local laws, regulations, markets and competition. KPMG has offices across India in Ahmedabad, Bengaluru, Chandigarh, Chennai, Gurugram, Jaipur, Hyderabad, Jaipur, Kochi, Kolkata, Mumbai, Noida, Pune, Vadodara and Vijayawada. KPMG entities in India offer services to national and international clients in India across sectors. We strive to provide rapid, performance-based, industry-focused and technology-enabled services, which reflect a shared knowledge of global and local industries and our experience of the Indian business environment. NA Equal employment opportunity information KPMG India has a policy of providing equal opportunity for all applicants and employees regardless of their color, caste, religion, age, sex/gender, national origin, citizenship, sexual orientation, gender identity or expression, disability or other legally protected status. KPMG India values diversity and we request you to submit the details below to support us in our endeavor for diversity. Providing the below information is voluntary and refusal to submit such information will not be prejudicial to you. QUALIFICATIONS BE/BTech

JOB DESCRIPTION About KPMG in India KPMG entities in India are professional services firm(s). These Indian member firms are affiliated with KPMG International Limited. KPMG was established in India in August 1993. Our professionals leverage the global network of firms, and are conversant with local laws, regulations, markets and competition. KPMG has offices across India in Ahmedabad, Bengaluru, Chandigarh, Chennai, Gurugram, Jaipur, Hyderabad, Jaipur, Kochi, Kolkata, Mumbai, Noida, Pune, Vadodara and Vijayawada. KPMG entities in India offer services to national and international clients in India across sectors. We strive to provide rapid, performance-based, industry-focused and technology-enabled services, which reflect a shared knowledge of global and local industries and our experience of the Indian business environment. NA Equal employment opportunity information KPMG India has a policy of providing equal opportunity for all applicants and employees regardless of their color, caste, religion, age, sex/gender, national origin, citizenship, sexual orientation, gender identity or expression, disability or other legally protected status. KPMG India values diversity and we request you to submit the details below to support us in our endeavor for diversity. Providing the below information is voluntary and refusal to submit such information will not be prejudicial to you. QUALIFICATIONS BE/BTech

Description Invent the future with us. Recognized byFast Company’s 2023 100 Best Workplaces for Innovators List,Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team — we’d love to have you apply. Come invent the future with us. About The Role Ampere is seeking a highly skilled and experienced candidate with proven expertise in PHY hardening, particularly in DDR and SerDes, with a focus on digital implementation and convergence. We are looking for a self-motivated individual with a proven track record in hardening state-of-the-art PHYs and contributing to the development of cutting-edge expertise. What You’ll Achieve As a PHY Hardening Engineer, you will collaborate with architects, RTL designers, packaging and PCB design teams, and post-silicon validation groups. This is an exceptional opportunity to showcase your engineering skills in a dynamic, fast-paced environment that fosters innovation and operates at the forefront of technology. High-Speed Digital Design Develop high-speed digital layouts, including DDR and other high-speed interfaces. Expertise in floor planning, bump planning, routing, power grid design, clock design/distribution, and optimization for high-speed digital circuits. Optimize layouts to minimize signal integrity issues, reduce power consumption, and meet timing, power, and manufacturability requirements. Coordinate with PHY vendors for hardening activities and deliverables. Estimate effort and timelines for PHY hardening tasks and provide feedback on timing/PDV. Chip-Level Physical Design Perform chip-level tasks such as floor planning, partitioning, and power/clock distribution. Handle chip assembly and ensure seamless integration of multiple IP blocks into the top-level design. Proficiency in using EDA tools for chip-level physical verification (DRC, LVS, ERC). Collaborate with the packaging team to refine bump placement and package routing considerations. Signal and Power Integrity Familiarity with signal and power integrity concepts in high-performance memory systems. Expertise in managing high-speed signals to mitigate issues like crosstalk, reflection, and signal degradation. Perform thermal and power integrity analysis to ensure reliable designs. Knowledge of advanced packaging techniques and considerations, an added plus Design-for-Test (DFT) Basic understanding of DFT structures, including scan chains, MBIST, and loopback mechanisms. Contribute to DFT-based timing closure activities. About You Bachelor's degree & 8 years of related experience or Master's degree & 6 years of related experience Expertise in floor planning, bump planning, routing, power grid design, clock design/distribution, and optimization for high-speed digital circuits Experience developing high-speed digital layouts, including DDR and other high-speed interfaces Handling chip assembly and ensure seamless integration of multiple IP blocks into the top-level design Proficiency in using EDA tools for chip-level physical verification (DRC, LVS, ERC) Worked with architects and RTL teams to develop physical constraints and optimize their design Integrate PHYs, controllers, and memory stacks into the top-level design Expertise in managing high-speed signals to mitigate issues like crosstalk, reflection, and signal degradation Experience with advanced packaging technologies, such as 2.5D/3D integration, TSV, and interposer-based designs Handle micro-bump design to ensure proper alignment and minimize resistance Understand the SIPI impacts of bump placement Basic understanding of DFT structures, including scan chains, MBIST, and loopback mechanisms Strong communication and articulation skills are required to excel in this role What We’ll Offer At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits Highlights Include Premium medical, dental, vision insurance, parental benefits includingcrechereimbursement, as well as a retirement plan,so thatyou can feel secure in your health,financial futureand child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process. Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law. Show more Show less

Project Role : Application Developer Project Role Description : Design, build and configure applications to meet business process and application requirements. Must have skills : SAP FI S/4HANA Accounting Good to have skills : NA Minimum 3 Year(s) Of Experience Is Required Educational Qualification : 15 years full time education Summary: SAP Tax Accounting Senior Consultant Roles & Responsibilities: 1 Hands on experience in SAP S4HANA/ECC implementation in SAP indirect and direct taxation 2 Implementation experience in Tax codes and Tax conditions 3 Strong knowledge in integration topic from Tax perspective with Procurement and Sales. 4 Implementation experience in Taxation tool like – DRC and E-Invoicing/E-Document. 5 Good knowledge on Taxation localization requirements across the globe 6 Integration experience with third party taxation tool like – Onesoure/Thomson Reuters/Vertex etc. 7 Should have implementation experience in SAP Taxation with minimum 5 years of experience. Professional & Technical Skills: 1 SAP Indirect and Direct Taxation 2 Taxation Functional Expertise 3 SAP S4HANA Financial Accounting. Additional Information: 1 Minimum 15 years full time in education. Show more Show less

Job Details: : Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design. Participates in the definition of architecture and microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Works with IP providers to integrate and validate IPs at the SoC level. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: A bachelors degree in electrical/computer engineering, Computer Science or related field with 6+ years of experience (or) a masters degree with 4+ years of experience. Preferred Qualification: Relevant experience with skills in SoC flows, RTL integration and Globals (Clocking, Boot/Reset/Fabrics, DfD, Fuse, etc). Experience in subsystem design and HSIO protocols such as PCIe, UCIe is a plus. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Job Details: : You will be part of ACE India , in the P- Core design team driving Intels latest CPUs in the latest process technology. In this position, you will be working in a team of enthusiastic engineers on High Speed Designs in PNR from RTL to GDSII. Your responsibilities will include but not limited to:Meet the design targets of high performance and low-power digital design.Static timing analysis.Power Optimization.Design Convergence Experience at IP, SoC level.Ability to work in a highly dynamic environment across geographies.Back end design and implementation of new features.7Post silicon performance push activities. Qualifications: You must possess a Masters Degree in Electrical or Computer Engineering with atleast 6 or more years of experience in related field or a Bachelors Degree with at least 8 years of experience. Technical Expertise in Synthesis, Placement, CTS, Post-Route Optimization and P and R tools (CDNS and SNPS) . Preferred Qualifications- Familiarity with Verilog/ VHDL - Tcl, Perl, Python scripting. Strong verbal and written communication skills Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. *

Job Details: : Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams. Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT. Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU. Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. Qualifications: Qualifications: B.Tech with 3+ years or M.Tech with 2+ Years of hands-on experience with end-to-end SD flow - synthesis to GDS using industry standard EDA tool, with a proven track record of successful projects. Has good understanding on timing methodology, constraints building etc. Experience in floorplaning concepts and actual work, and integration of hierarchical design Good understanding and experience with multiple power domains designs. Have hands on experience on LV flow and clean up. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Job Summary PCB Layout Engineer is needed to join our growing team. The ideal candidate must have a strong understanding of PCB design principles and a proven track record of creating high-quality, reliable PCB layouts. Responsibilities include schematic review, layout creation, verification, and documentation. Experience and skills Required: Expertise in High Speed, Mixed signal design, Power board and RF board design single, double, multilayer (upto 20 layers) and Flex PCBs. Hands on Experience in Schematics and PCB Layout designs using Cadence Allegro design tool (Mandatory). Expertise in PCB footprint and Symbol creation also monitor, review and drive the library deliverables. Individual Contributor and take ownership for Schematics design, library, multilayer PCB Layout, BOM generation till Gerber release. Design experience: RF, Analog, High-speed digital circuits - DDR3 & 4, HDMI, PCIe, SATA, MIPI, USB 2,3.x, GigE. Good understanding of PCB manufacturing processes and industry standards. Experience in PCB DFM, DFA and best design practices. Knowledge of relevant industry standards (IPC-2221, IPC-7351). Ability to work effectively in a fast-paced, collaborative environment. Responsibilities: Design and layout of Printed Circuit Boards (PCBs) using Orcad tools. Create detailed PCB layouts based on provided schematics and specifications. Perform design rule checking (DRC) and other verification procedures to ensure design integrity. Collaborate with engineers from different disciplines (e.g., mechanical, firmware) to ensure designs meet system requirements. Generate and maintain comprehensive documentation of PCB design, including technical drawings and reports. Effectively troubleshoot design issues and implement necessary corrections. Adhere to established design guidelines and best practices. Support prototype development and testing phases. Maintain a strong understanding of current industry design trends and technologies. CAM validations and interact with manufacturer and assembly unit for any suggestions/clarifications. Work with circuit design & development engineer in understanding the end application requirements and design the PCB to meet the all critical requirements (Thermal, Signal integrity etc...). Coordinate with the internal hardware team during initial board bring-up tests. Work closely with manufacturing partners to ensure seamless transition from design to production. Conduct design reviews and implement design improvements based on feedback and analysis. Qualifications and other related experience: Diploma or Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field. 3+ years of professional experience in PCB layout design. Any related experience with aerospace and defence industry is added advantage. Show more Show less

Job Description The candidate will be responsible for implementing the place and route of design blocks including floorplanning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc. The candidate will also be responsible for block-level physical design closure in terms of timing, power, DRC/LVS, etc. Requirements 3-8years of experience in ASIC Physical Design Have good knowledge of the entire physical design process from floorplan to GDSII generation Good Exposure to Physical Verification Process Have hands-on experience in the latest sub-micron technologies below 10 nm Hands–on experience in leading PnR tools Synopsys ICC/ICC2 Experience in low power designs and handling congestion or timing critical tiles will be preferred Should be a quick learner and have good attention to detail Experience in ECO implementation preferred Scripting skills in Perl/Tcl/Python etc Must have good communication & problem-solving skills. Should be able to handle PnR tasks with minimal supervision Show more Show less

Summary About the role: Strive for sustainable growth through supporting and negotiating deals within APMA. Partner with APMA Region and countries Business Development & Licensing teams to analyze, support and successfully close BD&L opportunities which are aligned with APMA business strategy as well as monitor existing deals across deal parameters. Deal types include Exclusive Promotion and Distribution, Co-marketing, Selective Co-promotion (Digital, Channel management), TM divestments and information needs for global in-licensing deals, etc. About The Role Key Requirements: Trusted member of the Deal Team. Support APMA BD Directors and country BD leads by providing independent, high quality financial support to all BD&L transactions including EPDA, Licensing, Divestments, Co-Promotion and other strategic business initiatives. Makes recommendations for financial structure and terms to maximize value to Novartis while minimizing risk. Leads analysis of financial models underpinning deal terms; analyzes deal economics quickly to identify key value drivers and looks at key sensitivities. Specifically responsible for preparation of P&L’s, and financial slides for APMA/Cluster DRC business cases. Collect input from key finance (CFO, FRA, Tax, Funds Flow) stakeholders and incorporate their feedback in term sheet/contract in a timely manner. Takes proactive role in informing negotiations leader of financial issues. Constructively and proactively challenges deal terms which do not meet internal targets or are perceived to be inappropriate in terms of risk to Novartis. Provides key financial inputs to prioritize portfolio strategy and help ascertain short-/mid-/long-term partnering view. Provides financial oversights on existing deals in terms of reporting, tracking and flagging deviations on agreed deal parameters. Responsible to APMA finance dashboard data integrity and timely updates. Support APMA BD Directors for BD activities, including countries teams financial upskilling and capabilities building. Strong communicator with an ability to digest, simplify and present BD&L financials to countries and region management. Essential Requirements Excellent communication skills, both oral and written, are needed due to coordination and dissemination of important and confidential information. Strong interpersonal skills with ability to build strong partnerships and trust with counterparts. Ability to diplomatically challenge stakeholders within Novartis, from other companies, and from external organizations. Team leadership, project management, and negotiation skills are required. Business knowledge of the pharmaceutical industry including customers and competition is a plus. Desirable Requirements Minimum of 8-10 years’ experience in finance, accounting, and business operations, MBA will be a plus. Demonstrated superior financial analysis capabilities and superior skills in Excel. 1-2 years of Finance transaction/deal experience is a strong plus, as well as a solid understanding of accounting principles and current IFRS as it relates to BD&L transactions. Candidate must demonstrate initiative, creativity, and ability to work under pressure, often to tight deadlines. Why Novartis: Helping people with disease and their families takes more than innovative science. It takes a community of smart, passionate people like you. Collaborating, supporting and inspiring each other. Combining to achieve breakthroughs that change patients’ lives. Ready to create a brighter future together? https://www.novartis.com/about/strategy/people-and-culture Join our Novartis Network: Not the right Novartis role for you? Sign up to our talent community to stay connected and learn about suitable career opportunities as soon as they come up: https://talentnetwork.novartis.com/network Benefits and Rewards: Read our handbook to learn about all the ways we’ll help you thrive personally and professionally: https://www.novartis.com/careers/benefits-rewards Show more Show less

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. CAD Staff Engineer Our vision is to transform how the world uses information to enrich life. Join an inclusive team focused on one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we create helps make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while contributing to integrity, sustainability, and giving back to our communities. Because doing so can spark the very innovation we are pursuing. Job Description As a CAD Staff Engineer at Micron Technology, Inc., you will be working in a collaborative, production support role evaluating, improving EDA and debugging both in-house and commercial Electronic Design Automation (EDA) tools and flows for the physical layout, verification and design of CMOS integrated circuits. You will work closely with the Layout design teams to increase their productivity and work efficiency. Responsibilities And Tasks Include, But Not Limited To Work closely with memory layout teams and solve their daily challenges and provide complete solutions for the future. Proactively identify problem areas for improvement, propose, and develop innovative solutions. Develop methodologies for highly reliable layout with faster Time to Market approach. Continuously evaluate and implement new tools and technologies to improve the current layout development flows. Provide guidance and mentorship to junior members of the team. Qualifications 8+ years of experience in Layout automation, Physical Verification, or related domains. Experience in customizing a design environment, automation methodologies and utilities to increase memory layout productivity. Working experience in Place and Router flows for custom memory layouts with industry standard tools like Cadence Virtuoso, Synopsys Custom Compiler, Pulsic Unity, Itools etc. Working experience in PDN analysis tools like Totem/VoltusXFA/XA is preferable. Working experience of Physical Verification flow and analyzing/debugging DRC, ERC, LVS, DFM, Antenna Calibre/ICV rule deck issues is plus. Good understanding of advanced CMOS process manufacturing and layout design rules, EMIR, RC-Extraction, ESD, and Latch-up. Good understanding of programming fundamentals, as well as exposure to various programming languages including Skill (Cadence), Perl, Python, Tcl. Working knowledge of Linux is a must. Excellent problem-solving skills with attention to detail. Ability to work in a dynamic environment. Proficiency in working effectively with global teams and stakeholders. Education A bachelor’s or a master’s degree in Electronics, Electrical or Computer Engineering. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. Show more Show less

The candidate will be responsible for implementing the place and route of design blocks including floor planning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc. The candidate will also be responsible for block level physical design closure in terms of timing, power, DRC/LVS etc. REQUIREMENTS: 4-9 years of experience in ASIC Physical Design Have good Hands on entire physical design process from floorplan till GDS generation Good Exposure to Physical Verification Process Have hands-on experience in latest sub-micron technologies below 7nm Hands –on experience in leading PnR tools Synopsys ICC/ICC2 Experience in low power designs and handling congestion or timing critical tiles will be preferred Should be a quick learner and have good attention to detail Experience in ECO implementation preferred Scripting skills in Perl/Tcl/Python etc Must have good communication & problem-solving skills. Should be able to handle PnR tasks with minimal supervision Location :: Hyderabad & Bangalore *Adds on advantage atleast one or two projects has worked in AMD projects in his / her carier. Thanks, P Mohankrishna, Mohankrishna.p@Altcognitosystems.com Show more Show less