715 Drc Jobs

Category Engineering Hire Type Employee Job ID 10898 Remote Eligible No Date Posted 29/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and meticulous engineer with a deep commitment to excellence in analog and high-speed mixed signal layout design. With a minimum of 2 years of hands-on experience in advanced technology nodes (5nm and below), you thrive in dynamic, collaborative environments where quality, precision, and innovation are valued above all. You are well-versed in the intricacies of SerDes, CTLE, AFE, PLL, LDO, and transmitter/receiver sub-blocks, and you relish the challenge of delivering robust designs for cutting-edge semiconductor products. You are motivated by the opportunity to work alongside some of the brightest minds in the industry, continuously learning and contributing your expertise. You are eager to be part of a team that values diversity, inclusion, and the relentless pursuit of innovation, and you bring a growth mindset that seeks to elevate those around you. Your ability to communicate effectively, adapt to evolving requirements, and deliver under tight timelines sets you apart as a trusted contributor and future leader. What You’ll Be Doing: Designing and implementing high-quality analog and mixed signal layouts for advanced technology nodes (5nm and below). Collaborating closely with circuit design, verification, and physical implementation teams to optimize layout performance and manufacturability. Executing full custom layout of SerDes blocks including CTLE, AFE, PLL, LDO, and transmitter/receiver sub-blocks. Performing layout verification tasks such as DRC, LVS, and parasitic extraction to ensure compliance with design and process requirements. Participating in design reviews and providing technical input to ensure the robustness and reliability of delivered IP blocks. Documenting layout methodologies, design decisions, and best practices to drive organizational knowledge sharing. Supporting silicon debug and post-silicon validation activities as needed. The Impact You Will Have: Drive the successful delivery of high-performance, low-power analog and mixed signal IP for next-generation semiconductor products. Enable rapid time-to-market for customer solutions by ensuring first-pass silicon success through meticulous layout practices. Enhance Synopsys’ reputation as a leader in advanced technology node design by delivering innovative, reliable, and manufacturable layouts. Influence the development of best-in-class methodologies and automation for layout design and verification. Contribute to cross-functional learning and mentorship within a diverse, inclusive team environment. Support customer engagements and help resolve complex technical challenges, ensuring satisfaction and repeat business. What You’ll Need: Minimum of 2 years of experience in analog and high-speed mixed signal layout at 5nm or below technology nodes. Proven expertise in full custom layout of SerDes blocks (CTLE, AFE, PLL, LDO, transmitter/receiver sub-blocks). Strong command of industry-standard EDA tools for layout and verification (e.g., Cadence Virtuoso, Mentor Calibre, Synopsys IC Compiler). Demonstrated ability to interpret and implement complex circuit schematics into robust, high-quality layouts. Hands-on experience with DRC, LVS, and parasitic extraction flows and methodologies. Who You Are: Detail-oriented, with a strong commitment to quality and continuous improvement. Collaborative and communicative, able to work seamlessly across multidisciplinary teams. Self-motivated and proactive, taking ownership of deliverables and driving them to completion. Flexible and adaptive, thriving in fast-paced, evolving environments. Curious, eager to learn, and enthusiastic about sharing knowledge with peers. Committed to diversity, equity, and inclusion in the workplace. The Team You’ll Be A Part Of: You will join a diverse and highly skilled team of analog and mixed signal design professionals who are passionate about pushing the boundaries of semiconductor technology. The team collaborates closely with global engineering, product, and customer teams, focusing on delivering best-in-class IP for advanced technology nodes. We foster a culture of innovation, mentorship, and continuous learning, where every voice is heard and every contribution matters. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and detail-oriented engineer with a drive to deliver high-quality, innovative hardware solutions. You thrive in collaborative, cross-functional environments and are energized by working on world-class microprocessor IP that powers some of the most advanced embedded systems on the planet. With a strong foundation in electronics engineering or computer science, you bring at least five years of hands-on experience in ASIC physical design, particularly in physical verification and IR analysis. Your expertise enables you to navigate complex design flows, and you are keen to expand your knowledge by engaging with the latest industry tools and methodologies. You are comfortable scripting in Unix, Perl, and TCL, and you have a working knowledge of hardware description languages like Verilog or VHDL. You possess excellent written and verbal communication skills, allowing you to work effectively with international teams and assist in customer engagements. Your methodical and analytical mindset helps you troubleshoot and optimize designs for performance, power, and area. Eager to learn, you look forward to being involved in both in-house test chip projects and customer-facing design-ins, gaining exposure to a wide range of applications for Synopsys’ ARC processor IP. You are committed to continuous personal and professional growth, and you value the opportunity to contribute to a team that is shaping the future of microprocessor technology. What You’ll Be Doing: Developing and optimizing physical design implementation flows for ARC family microprocessor IPs, ensuring best-in-class performance and power efficiency. Performing comprehensive physical verification, including LVS, DRC, and IR drop analysis, to ensure first-pass silicon success. Collaborating with cross-functional teams, including logic design, verification, and library development, to drive seamless integration and qualification of IP. Supporting benchmarking, test chip implementation, and qualification activities for new microprocessor IP families. Assisting with customer support, design-ins, and technical sales engagements, providing insights into implementation best practices. Automating and enhancing existing design flows using scripting languages such as Perl and TCL to improve efficiency and reproducibility. Participating in internal knowledge-sharing initiatives and contributing to the continuous improvement of team processes and methodologies. The Impact You Will Have: Enable Synopsys customers to achieve rapid, successful integration of advanced ARC processor IP into their SoC designs. Drive the delivery of highly optimized, silicon-proven IP, reducing time-to-market for embedded and high-performance applications. Enhance the robustness and scalability of Synopsys’ implementation flows, setting industry benchmarks for physical design quality. Support the development and qualification of next-generation microprocessor IP, fueling innovation in diverse application domains. Strengthen customer relationships by providing expert technical guidance and support during pre- and post-sales engagements. Contribute to the continuous improvement of Synopsys’ engineering excellence, maintaining our leadership in silicon design. What You’ll Need: Bachelor’s degree in electronics engineering or computer science (Master’s preferred). Minimum 5 years of hands-on experience in ASIC physical design, with a focus on physical verification and IR analysis. Proficiency in scripting languages such as Unix shell, Perl, and TCL to automate design tasks. Exposure to hardware description languages such as Verilog or VHDL. Strong analytical and troubleshooting skills, with attention to detail in solving complex design challenges. Who You Are: A collaborative team player who communicates effectively with colleagues across the globe. Methodical and analytical, with a passion for continuous learning and improvement. Adaptable and open to new ideas, technologies, and design methodologies. Self-motivated and proactive in identifying and resolving technical issues. Customer-focused, with the ability to translate technical concepts into actionable solutions. The Team You’ll Be A Part Of: You’ll join a diverse, international team of experts dedicated to developing and delivering industry-leading microprocessor IP for the ARC family. The team works at the intersection of hardware design, implementation, and customer enablement, supporting a full suite of Synopsys memory compilers and standard cell libraries. You will collaborate closely with colleagues across logic design, verification, and applications engineering, learning from and contributing to a vibrant culture of innovation, knowledge sharing, and technical excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Knowledge in Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Good knowledge of Tcl/Perl Scripting Strong problem-solving skills and good communication skills. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3- 6yrs years of experience in Physical Design/Implementation Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Bachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution 2-10 years of experience in Physical Design/Implementation Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate, and advance faster than ever. Ready to join a growing team!!! Micron Technology's vision is to transform how the world uses information to enrich life, and our dedication to people, innovation, tenacity, teamwork, and customer focus allows us to fulfill our mission to be a global leader in memory and storage solutions. This means conducting business with integrity, accountability, and professionalism while supporting our global community. We are the only company manufacturing today's major memory and storage technologies: DRAM, NAND, and Emerging memory. We are looking for an energetic, ambitious individual with a strong work ethic and integrity to join us as the Scribe Design Engineer. The Scribe Design Non-Array (SDNA) team is responsible for the design, layout, and verification of CMOS electrical test structures that enable CMOS device development, Compact modeling, Reliability modeling, and Fab process monitoring. In this role, you will work with a group of Engineers in India, Japan, and the US. As part of a global team, you will contribute to physical layout, floor planning, and verifying through DRC and in-house verification tools. This role will allow you to work on all technology types at Micron. Specific Responsibilities Include But Not Limited To: - Understand the technology challenges and work with partner groups to provide CMOS Test Structure design and layout solutions for N, N+1, and N+2 process technology nodes. - Verify the integrity of the TEG design through LVS, DRC, E-simulation, and in-house verification tools. - Ability to drive forums with customers to maintain high customer satisfaction. - Attend necessary area meetings to understand the scope and coordinate activities related to Scribe scheduling, design, improvement, and Tape Out. - Learn and apply Micron Layout methodology, simulations, and automation for TEG solutions. - Understand the Fab Quality performance of our Scribe designs. - Strive to continuously improve the accuracy and repeatability of our Structures. - Use Metrics and data to drive decisions and improve performance. - Provide advice and counsel to senior management on significant technical issues related to CMOS TEG design solutions and automation. - Define and lead complex and multi-disciplinary projects that are critical for SCRIBE Design solutions. - Strong knowledge in different families of CMOS devices (Planar/Finfet). - Mentor junior-level engineers in the scribe team. - Ability to understand the existing methodologies quickly and provide enhancements in quality and CT improvement. - Ability to create innovative ideas to improve the process and solve existing problems. About Micron Technology, Inc.: We are an industry leader in innovative memory and storage solutions, transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron and Crucial brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com. Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.,

Category Engineering Hire Type Employee Job ID 12379 Remote Eligible No Date Posted 28/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and detail-oriented engineer with a drive to deliver high-quality, innovative hardware solutions. You thrive in collaborative, cross-functional environments and are energized by working on world-class microprocessor IP that powers some of the most advanced embedded systems on the planet. With a strong foundation in electronics engineering or computer science, you bring at least five years of hands-on experience in ASIC physical design, particularly in physical verification and IR analysis. Your expertise enables you to navigate complex design flows, and you are keen to expand your knowledge by engaging with the latest industry tools and methodologies. You are comfortable scripting in Unix, Perl, and TCL, and you have a working knowledge of hardware description languages like Verilog or VHDL. You possess excellent written and verbal communication skills, allowing you to work effectively with international teams and assist in customer engagements. Your methodical and analytical mindset helps you troubleshoot and optimize designs for performance, power, and area. Eager to learn, you look forward to being involved in both in-house test chip projects and customer-facing design-ins, gaining exposure to a wide range of applications for Synopsys’ ARC processor IP. You are committed to continuous personal and professional growth, and you value the opportunity to contribute to a team that is shaping the future of microprocessor technology. What You’ll Be Doing: Developing and optimizing physical design implementation flows for ARC family microprocessor IPs, ensuring best-in-class performance and power efficiency. Performing comprehensive physical verification, including LVS, DRC, and IR drop analysis, to ensure first-pass silicon success. Collaborating with cross-functional teams, including logic design, verification, and library development, to drive seamless integration and qualification of IP. Supporting benchmarking, test chip implementation, and qualification activities for new microprocessor IP families. Assisting with customer support, design-ins, and technical sales engagements, providing insights into implementation best practices. Automating and enhancing existing design flows using scripting languages such as Perl and TCL to improve efficiency and reproducibility. Participating in internal knowledge-sharing initiatives and contributing to the continuous improvement of team processes and methodologies. The Impact You Will Have: Enable Synopsys customers to achieve rapid, successful integration of advanced ARC processor IP into their SoC designs. Drive the delivery of highly optimized, silicon-proven IP, reducing time-to-market for embedded and high-performance applications. Enhance the robustness and scalability of Synopsys’ implementation flows, setting industry benchmarks for physical design quality. Support the development and qualification of next-generation microprocessor IP, fueling innovation in diverse application domains. Strengthen customer relationships by providing expert technical guidance and support during pre- and post-sales engagements. Contribute to the continuous improvement of Synopsys’ engineering excellence, maintaining our leadership in silicon design. What You’ll Need: Bachelor’s degree in electronics engineering or computer science (Master’s preferred). Minimum 5 years of hands-on experience in ASIC physical design, with a focus on physical verification and IR analysis. Proficiency in scripting languages such as Unix shell, Perl, and TCL to automate design tasks. Exposure to hardware description languages such as Verilog or VHDL. Strong analytical and troubleshooting skills, with attention to detail in solving complex design challenges. Who You Are: A collaborative team player who communicates effectively with colleagues across the globe. Methodical and analytical, with a passion for continuous learning and improvement. Adaptable and open to new ideas, technologies, and design methodologies. Self-motivated and proactive in identifying and resolving technical issues. Customer-focused, with the ability to translate technical concepts into actionable solutions. The Team You’ll Be A Part Of: You’ll join a diverse, international team of experts dedicated to developing and delivering industry-leading microprocessor IP for the ARC family. The team works at the intersection of hardware design, implementation, and customer enablement, supporting a full suite of Synopsys memory compilers and standard cell libraries. You will collaborate closely with colleagues across logic design, verification, and applications engineering, learning from and contributing to a vibrant culture of innovation, knowledge sharing, and technical excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Ready to join a growing team!!! Micron Technology’s vision is to transform how the world uses information to enrich life and our dedication to people, innovation, tenacity, teamwork, and customer focus allows us to fulfill our mission to be a global leader in memory and storage solutions. This means conducting business with integrity, accountability, and professionalism while supporting our global community. We are the only company manufacturing today's major memory and storage technologies: DRAM, NAND and Emerging memory. We are looking for an energetic, ambitious, individual with strong work ethic and integrity to join us as the Scribe Design Engineer. The Scribe Design Non-Array (SDNA) team is responsible for the design, layout, and verification of CMOS electrical test structures that enable CMOS device development, Compact modeling, Reliability modeling and Fab process monitoring. In this role you will work with a group of Engineers in India, Japan, and the US. As part of a global team, you will contribute to physical layout, floor planning and verifying through DRC and in-house verification tools. This role will allow you to work on all technology types at Micron. Specific responsibilities include but not limited to: Understand the technology challenges, work with partner groups to provide CMOS Test Structure design and layout solution for N, N+1 and N+2 process technology nodes Verify integrity of the TEG design through LVS, DRC, E-simulation, and in-house verification tools Ability to drive the forums with customers to maintain high customer satisfaction. Attend necessary area meetings to understand the scope and Coordinate activities related to Scribe scheduling, design, improvement and Tape Out. Learn and apply Micron Layout methodology, simulations and automation for TEG solutions. Understand the Fab Quality performance of our Scribe designs Strive to continuously improve the accuracy and repeatability of our Structures Use Metrics and data to drive decisions and improve performance. Provide advice and counsel to senior management on significant technical issues related to CMOS TEG design solutions and automation. Define and lead complex and multi-disciplinary projects that are critical for SCRIBE Design solutions Strong knowledge in different families of cmos devices(Planar/Finfet) Mentor to the junior level engineers in the scribe team. Ability to understand the existing methodologies quickly and provide enhancements in quality and CT improvement. Ability to create innovative ideas to improve the process and solve the existing problems. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. AI alert : Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

At PwC, our people in business application consulting specialise in consulting services for a variety of business applications, helping clients optimise operational efficiency. These individuals analyse client needs, implement software solutions, and provide training and support for seamless integration and utilisation of business applications, enabling clients to achieve their strategic objectives. Those in SAP finance at PwC will specialise in providing consulting services for SAP finance applications. You will analyse client requirements, implement software solutions, and offer training and support for seamless integration and utilisation of SAP finance applications. Working in this area, you will enable clients to optimise financial processes, improve financial reporting, and achieve their strategic objectives. Enhancing your leadership style, you motivate, develop and inspire others to deliver quality. You are responsible for coaching, leveraging team member’s unique strengths, and managing performance to deliver on client expectations. With your growing knowledge of how business works, you play an important role in identifying opportunities that contribute to the success of our Firm. You are expected to lead with integrity and authenticity, articulating our purpose and values in a meaningful way. You embrace technology and innovation to enhance your delivery and encourage others to do the same. Skills Examples of the skills, knowledge, and experiences you need to lead and deliver value at this level include but are not limited to: Analyse and identify the linkages and interactions between the component parts of an entire system. Take ownership of projects, ensuring their successful planning, budgeting, execution, and completion. Partner with team leadership to ensure collective ownership of quality, timelines, and deliverables. Develop skills outside your comfort zone, and encourage others to do the same. Effectively mentor others. Use the review of work as an opportunity to deepen the expertise of team members. Address conflicts or issues, engaging in difficult conversations with clients, team members and other stakeholders, escalating where appropriate. Uphold and reinforce professional and technical standards (e.g. refer to specific PwC tax and audit guidance), the Firm's code of conduct, and independence requirements. Job Summary - A career in our Managed Services team will give you an opportunity to collaborate with many teams to help our clients implement and operate new capabilities, achieve operational efficiencies, and harness the power of technology. Our Application Evolution Services team will provide you with the opportunity to help organizations harness the power of their enterprise applications by optimizing the technology while driving transformation and innovation to increase business performance. We assist our clients in capitalizing on technology improvements, implementing new capabilities, and achieving operational efficiencies by managing and maintaining their application ecosystems. We help our clients maximize the value of their SAP investment by managing the support and continuous transformation of their solutions in the areas of sales, finance, supply chain, engineering, manufacturing and human capital Minimum Degree Required (BQ) *: Bachelor’s Degree Required Field(s) Of Study (BQ) Preferred Field(s) of Study: Minimum Year(s) of Experience (BQ) *: US Minimum Of 10-16 Years Of Experience Preferred Skills/Certification(s) Preferred: SAP Certification in FICO/CFIN Experience in S/4 HANA (Public Cloud) Exposure to interfaces like ALE/IDOC or EDI/IDOC with little technical knowledge Preferred Knowledge As a manager, you’ll work as part of a team of problem solvers with extensive consulting and industry experience, helping our clients solve their complex business issues from strategy to execution. Specific responsibilities include but are not limited to: Proactively assist in the management of a portfolio of clients, while reporting to Senior Managers and above. Be involved in the financial metrics. Be actively involved in business development activities to help identify and research opportunities on new/existing clients. Contribute to the development of your own and team’s technical acumen. Use data and insights to inform conclusions and support decision-making. Adherence to SLAs, experience in incident management, change management and problem management. Develop new skills and strategies to solve complex technical challenges. Assist in the management and delivering of large projects. Train, coach, and supervise staff to recognize their strengths and encourage them to take ownership of their personal development. Act to resolve issues which prevent the team working effectively. Keep up to date with local and national business and economic issues. Continue to develop internal relationships and the PwC brand. Build a strong team environment that includes client interactions, workstream management, and cross-team collaboration. Actively engage in cross competency work and contribute to COE activities. Demonstrating project management skills including the ability to manage multiple projects simultaneously while being detail oriented. Technical Skills Responsible for planning and executing SAP Implementation / Development / Support activities regarding SAP Finance and Controlling (FI-CO) along with Central Finance (CFIN). Understand client requirements, provide solutions, functional specifications and configure the system accordingly. Ability to configure SAP FI-CO and CFIN, deliver work products / packages confirming to the Client's Standards & Requirements. Integration of the FI-CO module with other SAP modules and with external applications. Hands on experience in configuring / defining the following in the FICO / CFIN: SAP FI – General Ledger Accounting SAP FI – Accounts Receivable & Accounts Payable SAP FI – Asset Accounting SAP FI – Fixed Assets SAP CO – Cost Centers and Profit Centers SAP CO – Internal Orders SAP CO – Product Costing Master Data – GL, FA, CO, Consolidations Treasury Process – Master Data and Transactions Month End Close – Activities and foreign currency valuations Cost Management and Profitability Analysis – Financial Plan Data Upload File, FP&A, Margin Analysis, Overhead Cost Accounting, Universal Allocation Central Finance -Initial Loads Central Finance - Error Cockpit ICMR -Configuration, Matching Methods, Reconciliation Case, Matching Rules/Matching Expressions TAX – Indirect Tax – Tax Engine Vertex, US Sales and Tax Reporting, Exemption Certificate Management, S4 ProCo Alignment Vertex/Alteryx/SAP S4, VAT: Transactional Tax Determination and Tax Accounting in S4 (Non-US VAT in different countries), Electronic Tax Invoicing using SAP DRC (for India and Mexico) using SAP DRC, Indirect Tax Reporting using SAP DRC (Non-US VAT), SAP Deferred tax transfer program. TAX – Direct Tax – Income TAX Accounting (Provision), Income Tax Compliance, Withholding Tax, Tax Technology / Operations. Transfer Pricing – Intercompany Cost Allocations, Intercompany Services, Cost Sharing, Reporting and Analytics Cash Basis Ledger – Data Transfer, Transaction Posting, Reports Interfaces Delivery Lead Experience Constantly looking to identify impediments early, actively working to resolve those impediments, and escalate when needed. Management and tracking of cross team/squad dependencies. Hands-on experience working on reporting and preparing presentations as part of WSR & MSR. Management and tracking of all high-integrity commitments. Provides proactive visibility and effectively communicates delivery targets, commitments and progress. Works to minimize meetings and ceremonies, but when they are needed, they are well-run and efficient. Encourages a culture of team-driven decision making and commitment. Encourages team trust and facilitates team building events. Where appropriate, coaches the teams to improve collaboration and outcomes (coaching is the primary responsibility of teams’ managers) Qualification Proficiency with SAP BTP (Business Technology Platform) Strong understanding of architecture considerations for SAP (cloud, on-premises, hybrid). Experience with SAP BTP security and authorization. Ability to design new architectural frameworks and influence their execution. Good knowledge of SAP S/4HANA architecture and functionality ITIL 4 Certification Soft Skills Self-driven with a can-do attitude, with an excellent communication and client-facing skills Problem-solving mindset and ability to work in a collaborative environment. Strong relationship builder within the organization and with external partners.

Job Summary Physical verification engineer for SOC/blocks Key Responsibilities Physical verification for SOCs, cores, and blocks, including DRC, LVS, ERC, ESD, DFM, and tapeout processes. Address critical design and execution challenges associated with physical verification and sign-off. Have a comprehensive understanding of physical verification and sign-off workflows and methodologies. Partner with PNR engineers to achieve sign-off at various stages of the design process. Qualifications and Skills Proficient in physical verification for SoC/full-chip and block-level processes, including DRC, LVS, ERC/PERC, DFM, OPC, and tapeout. Comprehensive experience and understanding of all stages of the IC design process from RTL to GDS2. Skilled in troubleshooting LVS issues at the chip level, particularly with complex analog-mixed signal IPs. Familiar with low-power design techniques, including level shifters, isolation cells, power domains/islands, and substrate isolation. Experienced in physical verification of I/O rings, corner cells, seal rings, RDL routing, bumps, and other full-chip components. Capable of developing sign-off methodologies/flows and providing support to larger teams. Knowledge of ERC rules, PERC rules, and ESD rules is a valuable asset. Experience in floorplanning is a plus. Show more Show less

We Are: Drive technology innovations that shape the way we live and connect Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world, Apprenticeship Experience: At Synopsys, Apprentices dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide?and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path Join us and start shaping your future today! Mission Statement: Our mission is to fuel todays innovations and spark tomorrows creativity Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive?both at work and beyond, What Youll Be Doing: Contribute towards developing IC Validator DRC, LVS, Fill and PERC runsets Collaborate with R&D team on technologies/solution roadmaps to help them focus on the most critical design challenges Work with other Synopsys field teams, ensuring overall consistency of IC Validator solutions and that they meet customer needs, What Youll Need: Should be a graduate engineer (2024/2025) in Electronic Engineering, Computer Science, Familiarity with physical verification tool like IC Validator, Calibre, PVS or any other PV tool Understanding of DRC, LVS, Fill and multi-patterning concepts Excellent problem-solving skills Understanding of physical design layouts Good knowledge of scripting languages like Python, TCL or Perl Key Program Facts: Program Length: 12 months Location: Hyderabad Working Model: On-site Full-Time/Part-Time: Full-Time Start Date: Aug/Sep 2025 Equal Opportunity Statement: Synopsys is committed to creating an inclusive workplace and is an equal opportunity employer We welcome all qualified applicants to apply, regardless of age, color, family or medical leave, gender identity or expression, marital status, disability, race and ethnicity, religion, sexual orientation, or any other characteristic protected by local laws If you need assistance or a reasonable accommodation during the application process, please reach out to us, Show

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an IC Layout Manager, you will work with an exceptionally talented, passionate core team based in India, lead the team to design IC layout working for intensive applications such as artificial intelligence and high-performance computing solution, High Bandwidth Memory. As an IC Layout Manager, you will be collaborating with peer teams crossing Micron global footprint, to meet scheduled milestones in a multiple projects-based environment. Responsibilities Provide leadership in building and growing a Custom layout team from the ground up to support Micron’s global DRAM layout requirement. Provide leadership in developing Analog and custom layout to meet schedule and milestone; Provide leadership in training the team’s technical skills and cultural healthiness. Effectively communicating with engineering teams in the US, Japan and China to assure the success of the layout project. Organize, prioritize, and manage logistic on tasks and resource allocations for multiple projects. Manage performance and development of team members. Managing hiring and retention. As a critical member of the core DRAM leadership team in India, contribute to the overall success of the Micron DRAM India operation. Qualification/Requirements 14+ year experience in analog/custom layout in advanced CMOS process, in various technology nodes (Planar, FinFET) Minimum 1+ years people management experience. Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. Must have strong skills in layout and floor planning skills and manual routing. Strong ability to build , and continuously develop a premier analog/mixed-signal layout team. Experienced in managing multiple Custom IC layout projects. Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design. The ability to work and communicate effectively in a team and to be able to multi-task effectively in a fast-paced working environment. Excellent verbal and written communication skills required. Independent with strong analytical skills, creative thinking and self-motivated. Capable of working in a cross functional , multi-site team environment in multiple time zones. Previous work experience in DRAM/NAND layout design is desirable however not mandatory. Strong passion and ability to attract, hire, retain engineers by motivating them and by inculcating innovation culture. Ability to collaborate with overseas Teams to define strategy, plan, and execute across the larger, global organization. Be accountable for the proper technical solutions implemented by your team. Education BE or MTech in Electronic/VLSI Engineering. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. AI alert : Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

Job Title - Consutant/Manager Location: Gurgaon, Mumbai, Bangalore, Pune, Hyderabad Must have skills: SAP FICO Implementation Good to have skills: Generic FICO, PS+Investment mgt, DRC, FSCM, CO, VIM+FI, OCR, Functional MDG, AFC/FCC, SAP ICMR, Intercompany, SAP CFIN Job Summary: Have been part of at least 4 end to end SAP implementations. Out of which 2+ in S4 Understand the SAP roadmap for S/4 HANA and become a trusted advisor for clients in driving their S/4 HANA adoption. Have experience in defining a Business Case for S4 Transformation and RoI calculations. Have worked in the capacity of Solution Architect / Design Authority in Past and have done lot of advisory work for ERP’s for e.g. Product selection, Value realization, Fit Gap Assessment etc. Work closely with clients to understand their issues, define IT strategies, architecture solutions, win buy-in for your recommendations. Professional & Technical Skills: MBA from a Tier-1 or Tier-2 B-school. CA or CPA Deep knowledge and experience in Finance and Controlling Org structure and design, S/4 HANA Implementation and rollout point of views, approach and design principles, roadmap, and business case definition. Ability to drive large scale digital finance transformation initiatives during the entire life cycle of the project. 8+ years’ experience in SAP S/4 HANA design to implementation projects At least 6+ years of consulting experience in a big4 or similar firms Extensive experience in GTM/Presales and writing proposals.

As a PCB Layout Designer/ CAD Design Engineer with 2+ years of experience in High Speed, Complex Board Layout, and PCB designing, your responsibilities will include having a good understanding of Datasheets, creating Libraries for Complex Logical and Footprints, adhering to IPC Standards for Footprint Creation and Layout processes, and managing the entire PCB Designing flow from Library creation to Gerber release to FAB. Additionally, you will be responsible for setting high-speed constraints and routing, working on High-Speed signal routing, and designing High-speed, Multilayer PCB designs. You should have hands-on experience in Designing High-speed, Multilayer PCB designs, performing DFM checks, and possessing expertise in standard High-Speed Digital, Analog & Mixed signal Design including I2C, SPI, USB2.0/3.0, Ethernet, PoE, BLE, Wi-fi, GSM, TFT LCD, DDR2/DDR3/DDR4, SD Card, NAND, MIPI, Optical interface, among others. Your role will also involve handling DRC and Post-processing tasks such as Gerber Settings, FAB & Assembly files generation, and conducting quality checks for Footprints, PCB Layout files, FAB & Assembly files. Moreover, you will be expected to interact with various teams including Design, Mechanical, SI, PI, Thermal, FAB, and Assembly house for Clarifications and Reviews, and should be capable of handling projects independently. Proficiency with EDA Tools such as Mentor Expedition, Valor, and Gerber tools for reviews will be required for this role. To qualify for this position, you should hold a BE/ B.Tech degree in EC or Electronics. If you are an innovative and technology-driven individual with a passion for designing cutting-edge telecom and security solutions, we encourage you to apply for this exciting opportunity. We look forward to connecting with you soon.,

We are looking for highly skilled Physical Verification Engineers to join our team. The ideal candidates will have extensive experience in physical verification tasks such as DRC, LVS, and parasitic extraction using tools like Mentor Graphics Calibre. You will be working on cutting-edge technologies and collaborating with cross-functional teams to ensure seamless tapeouts and compliance with foundry design rules. Your main responsibilities will include implementing Physical Verification with a focus on hard macro/core finishing activities. You must have led and been primarily responsible for physical verification checks, fixing, and sign-off. It is essential to have an excellent understanding of the Physical Verification flow, with experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues primarily using the Calibre tool. Additionally, a deep understanding of ESD, latch-up, etc., is required. You will be responsible for owning and executing Physical Verification activities at the Top/Block level. Collaborating closely with the PD team to address their PV issues and suggest solutions is a key aspect of the role. Working with CAD team to refine existing flows/methodologies and resolve issues is also part of the job scope. Experience in IO, Bump planning, RDL routing Strategy, and developing/implementing timing and logic ECOs are considered advantageous. Knowledge of tools like Innovus/FC for DRC fixing, Python, PERL/TCL scripting, and the ability to plan, work independently, and coordinate with cross-functional teams are essential. Closing sign off DRC based on PNR markers is a plus. The ideal candidate should have experience with physical verification checks such as DRC, LVS, Antenna, ERC, PERC, ESD, etc. Experience with PnR tools like ICC/Innovus and understanding sign-off PDV tools like PDK Concepts, SVRF, Calibre, and ICV is required. A good overall understanding of the Custom IC design flow, layouts, and backend tool flow would be beneficial. Hands-on experience with tools like Innovus/Fusion Compiler, Tech lef is preferable. People management, floorplanning, power planning, and PDN experience are considered a big plus. The ability to script in TCL/PERL and familiarity with physical convergence in PnR tools are also advantageous. In return, we offer a competitive salary, performance-based bonuses, comprehensive benefits package including health insurance, retirement plans, and paid time off. Additionally, you will have opportunities for professional development and career growth in a collaborative and innovative work environment with state-of-the-art facilities.,

As an ASIC Physical Design Engineer at Synopsys, you will play a key role in driving innovations that shape the future of technology. Your expertise in delivering high-quality, timing-clean designs will be essential in empowering the creation of high-performance silicon chips and software content. You will be responsible for owning the complete physical implementation process at both block and chip levels, ensuring DRC, LVS, and IR closure, and collaborating closely with the frontend design team to resolve design issues. Your role will involve delivering timing-clean blocks and chip-level designs that meet specified targets, evaluating and setting up physical design flows, and managing all chip-level tasks including P&R, STA, PV, and IR. Your proficiency in scripting with Tcl and Perl will enhance your ability to optimize design flows and achieve project goals efficiently. Additionally, you will contribute to the successful delivery of high-performance silicon chips, enhance the efficiency and reliability of physical design processes, and drive innovation in chip design and integration. To excel in this role, you will need an MSEE/BSEE with 5+ years of related experience in ASIC physical design, in-depth understanding of physical design specialization, strong problem-solving skills, and experience with scripting languages such as Tcl and Perl. Your ability to mentor junior engineers, collaborate effectively in team-driven projects, and network with senior personnel will be crucial in strengthening Synopsys" reputation as a leader in semiconductor technology. Joining our dynamic and innovative team, you will have the opportunity to push the boundaries of chip design and integration. Together, we focus on delivering high-performance silicon chips through collaborative efforts and cutting-edge technologies. We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs, including both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.,

You have a job opportunity available in Bangalore where you will be responsible for collaborating cross-functionally to comprehend architecture needs across various business units. As the ideal candidate for this position, you must have expertise in SAP S/4Hana, SAP CFIN, Tax codes, WHT, DRC, Plants abroad, CIT, etc. Your responsibilities will include configuring and maintaining TAX processes like indirect taxes, direct taxes, tax reporting, tax reconciliation, and ensuring compliance with local and global tax regulations within the Central Finance (CFIN) system. It is crucial to align these processes with business requirements and industry best practices. You will also be involved in gathering requirements from stakeholders, documenting functional specifications, and translating them into system configurations. Furthermore, you will need to integrate TAX processes seamlessly within the CFIN system and other enterprise systems like ERP, SAP TC, to ensure smooth data flow and process automation across platforms. Providing user support and training, conducting testing and validation, optimizing processes, and driving continuous improvement will be key aspects of this role. To qualify for this position, you should hold a Bachelor's degree in any stream and possess 5+ to 18 years of relevant experience. Advanced knowledge of leading architecture solutions in the industry area, strong interpersonal and collaboration skills, and the ability to communicate technical concepts to non-technical audiences are essential. This position is based in Bangalore. If you meet the requirements and are interested in this opportunity, please apply by sending your resume to rashwinder.kaur@qmail.quesscorp.com.,

About The Opportunity Join a forward-thinking enterprise in the ERP and SAP solutions sector, committed to excellence in SAP data management and process optimization. Based in India, this on-site role is integral to ensuring efficient document release processes and system integrity. We work in a dynamic, high-performance environment where innovation and compliance go hand in hand. Role & Responsibilities Coordinate and manage end-to-end SAP document release processes ensuring timely data deployment. Oversee and streamline workflows within the SAP environment to maintain data accuracy and system compliance. Collaborate with cross-functional teams to schedule and monitor release cycles and system updates. Ensure adherence to SAP compliance standards, company protocols, and regulatory guidelines. Troubleshoot system issues and implement corrective actions to enhance process efficiency. Provide on-site training and continuous support for end-users on SAP DRC functionalities. Must-Have Skills & Qualifications Bachelor's degree in Information Technology, Business Administration, or a related field. Proven experience in SAP environments, specifically in SAP Document Release Coordination or similar roles. Strong analytical, troubleshooting, and organizational skills with keen attention to detail. Excellent communication skills with the ability to liaise effectively across multiple teams. Solid understanding of compliance protocols and regulatory requirements in SAP systems. Preferred SAP certification in relevant modules and experience with workflow automation. Prior experience in on-site support roles in a fast-paced ERP environment. Benefits & Culture Highlights Competitive compensation package with comprehensive benefits. A collaborative work environment that supports professional growth and career development. Engage in a culture of innovation with leadership that values input and fosters continuous improvement. Skills: charted accountant,compliance assurance,data coordination,sap,compliance protocols knowledge,organizational skills,drc,analytical skills,workflow automation,fico,workflow management,troubleshooting,communication skills,hana,sap document release coordination

About The Opportunity Join a forward-thinking enterprise in the ERP and SAP solutions sector, committed to excellence in SAP data management and process optimization. Based in India, this on-site role is integral to ensuring efficient document release processes and system integrity. We work in a dynamic, high-performance environment where innovation and compliance go hand in hand. Role & Responsibilities Coordinate and manage end-to-end SAP document release processes ensuring timely data deployment. Oversee and streamline workflows within the SAP environment to maintain data accuracy and system compliance. Collaborate with cross-functional teams to schedule and monitor release cycles and system updates. Ensure adherence to SAP compliance standards, company protocols, and regulatory guidelines. Troubleshoot system issues and implement corrective actions to enhance process efficiency. Provide on-site training and continuous support for end-users on SAP DRC functionalities. Must-Have Skills & Qualifications Bachelor's degree in Information Technology, Business Administration, or a related field. Proven experience in SAP environments, specifically in SAP Document Release Coordination or similar roles. Strong analytical, troubleshooting, and organizational skills with keen attention to detail. Excellent communication skills with the ability to liaise effectively across multiple teams. Solid understanding of compliance protocols and regulatory requirements in SAP systems. Preferred SAP certification in relevant modules and experience with workflow automation. Prior experience in on-site support roles in a fast-paced ERP environment. Benefits & Culture Highlights Competitive compensation package with comprehensive benefits. A collaborative work environment that supports professional growth and career development. Engage in a culture of innovation with leadership that values input and fosters continuous improvement. Skills: charted accountant,compliance assurance,data coordination,sap,compliance protocols knowledge,organizational skills,drc,analytical skills,workflow automation,fico,workflow management,troubleshooting,communication skills,hana,sap document release coordination

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Job Overview: This position centers on floor-planning expertise at both block and top levels for industry-leading CPU core designs, with a strong emphasis on scalability and achieving aggressive Power, Performance, and Area (PPA) targets. The role involves working on cutting-edge technology nodes and applying advanced physical design techniques to push the boundaries of CPU performance and efficiency. Preferred Qualifications: Masters degree in Electrical/Computer Engineering 8+ years of direct top level floor-planning large and high frequency IP experience In depth end to end experience from RTL2GDS, taping out at least 5 complex designs Direct hands-on experience with bus/pin/repeater planning for entire IP Key responsibilities include: Driving floorplan architecture and optimization in collaboration with PD/RTL teams to maximize PPA Engaging in cross-functional collaboration with Physical design, timing, power, and packaging teams to ensure holistic design convergence Partnering with EDA tool vendors and internal CAD teams to develop and enhance automation flows and methodologies for improved design efficiency Making strategic trade-offs in design decisions to achieve optimal PPA outcomes while maintaining schedule and quality targets End to End Physical verification closure for subsystem. The ideal candidate will have/demonstrate the following: Experience in Physical design which includes floor-planning, placement, clock implementation, routing for complex, big and high speed designs Experience with physical synthesis and implementation tools - Cadence Innovus/Genus and Synopsys Fusion Compiler. Must have good knowledge of static timing analysis, reliability, and power analysis Strong understanding of CMOS circuit design and design techniques to push Power, Performance and Area of complex designs Ability to think outside the box for innovative solutions to improve power and eliminate performance bottlenecks Strong understanding of CPU micro-architecture and collaborate with RTL designers to improve bottlenecks for power and performance Solid working knowledge of scripting skills including tcl, perl or python Excellent communication skills and collaborating in a team environment is a must Excellent understanding of Physical Verification flow with in-depth experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues. (Mostly Working on Calibre tool) Experience in IO, Bump planning and RDL routing Strategy. Preferred Skills: Clock implementation, power delivery network design choices, process technology, prior experience in flow and methodology development, block closure Close interaction with design and architecture teams to influence scalable floor-plans and optimal bus/pin/repeater planning for entire IP and its sub-blocks Hands on experience with Synthesis, DFT, Place and Route, Timing and Reliability Signoff Hands on experience working with very complex designs that push the envelope of Power, Performance and Area Hands on experience working with sub-micron technology process nodes eg. 5nm, 4nm and below is highly advantageous Hands on experience on Innovus/FC tool based scripting & python/TCL scripting. Prior experience in flow and methodology development is an advantage Excellent debug and analytical skills and demonstrated successes in floor-planning large IP and high frequency designs Ability to drive Physical Implementation teams in Floor-planning and work well in a collaborative environment with multi-disciplined teams Minimum Qualifications: Bachelors degree in Electrical/Computer Engineering 8+ years of direct top level floor-planning large and high frequency IP experience which includes bus/pin/repeater planning at the top level Strong background in VLSI design, physical implementation and scripting Strong background and experience working with industry standard Synthesis and Place and Route tools including Signoff tools Hands on experience taping out designs in sub-micron technology node design Expect strong self-motivation and time management skills Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail or call Qualcomm's toll-free number found . Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact .

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. As CPU Integration CAD engineer, you will enable the floor-planning, physical design (PD), physical design verification (PDV), and signoff of Qualcomms class-leading Oryon CPU cores . You will build and support agile flows and methodologies that enable the first time right development of products with industry-leading power, performance and area. Experience 6 to 15 years of experience with good academics . Roles and Responsibilities Work closely with worldwide cross-functional teams such as CPU physical design, CPU and SOC Integration, Technology and Central CAD Develop, integrate and release flows and methodologies for floor planning, power planning, pin placement, chip assembly, PDV analysis Develop and maintain unit and system tests to enable correct-by-construction floorplans and physical layouts Architect and recommend methodology improvements to ensure our silicon has the best power, performance and area Maintain and support implementation flows, and resolve project-specific issues Work with EDA vendors to define roadmap and to resolve tool issues Preferred Qualifications: Bachelors/Masters degree in Electrical/Electronics Engineering or Computer Science 10+ years of hands-on experience in development of high-performance chips - either in a design or CAD role High level of programming proficiency ( Python and TCL ). Knowledge of data structures and algorithms Experience with automation Experience with a broad variety of Physical Design tasks - ranging all the way from place-and-route, analysis, timing sign-off and PDV Experience with advanced technology nodes (5nm or lower) Strong user of industry-standard PDV tools such as Siemens/Mentor Calibre Strong user of industry-standard place-and-route tools such as Cadence Innovus Proven track record of managing and regressing place-and-route flows Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Synthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation. Development of signoff quality constraints and the development of power intent constraints. May also include running RTL Lint, CLP, MEMBIST, DFT DRC etc. TCL script development in addition to running/analyzing/debugging designs. Hands on with Synopsys DCG/Genus/Fusion Compiler. Hands on with Synopsys Prime Time including constraint development for complex blocks with multiple clock domains. Hands on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development Experience with either RTL development or Physical Design is also a plus 6+ years experience Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: General Summary Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. As a CPU Micro-architecture and RTL Design Engineer, you will work with chip architects to conceive of the micro-architecture, and also help with architecture/product definition through early involvement in the product life-cycle. Roles And Responsibilities Performance exploration. Explore high performance strategies working with the CPU modeling team. Microarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification. RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals. Functional verification support. Help the design verification team execute on the functional verification strategy. Performance verification support. Help verify that the RTL design meets the performance goals. Design delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and po Preferred Qualifications Thorough knowledge of microprocessor architecture including expertise in one or more of the following areasinstruction fetch and decode, branch prediction, instruction scheduling and register renaming, out-of-order execution, integer and floating point execution, load/store execution, prefetching, cache and memory subsystems Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools Knowledge of logic design principles along with timing and power implications Understanding of low power microarchitecture techniques Understanding of high performance techniques and trade-offs in a CPU microarchitecture Experience using a scripting language such as Perl or Python Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Roles and Responsibilities Perform various electrical analyses at block and top levels, including static/dynamic IR, power/signal EM, and ESD Drive block and top-level electrical verification closure Develop power grid specs based on power/performance/area targets of different SOC blocks. Implement power grids in industry standard PnR tool environments. Work closely with the PI team to optimize the overall PDN performance. Work with CAD and tool vendors to develop and validate new flows and methodologies. Preferred qualifications BS/MS/PhD degree in Electrical Engineering; 4+ years of practical experience In-depth knowledge of EMIR tools such as Redhawk and Voltus Experience in developing and implementing power grid Good knowledge of system-level PDN and power integrity Practical experience with PnR implementation, verification, power analysis and STA Proficient in scripting languages (TCL/Perl/Python) Experience with industry standard EMIR tools such as Redhawk and Voltus Basic knowledge of the physical design flow and industry standard PnR tools Experience with scripting languages such as TCL, Perl and Python Ability to communicate effectively with cross-functional teams 4+ yrs exp in STA Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Experience - 4 to 7 Years in EM/IR/PDN Roles and Responsibilities Perform various electrical analyses at block and top levels, including static/dynamic IR, power/signal EM, and ESD Drive block and top-level electrical verification closure Develop power grid specs based on power/performance/area targets of different SOC blocks. Implement power grids in industry standard PnR tool environments. Work closely with the PI team to optimize the overall PDN performance. Work with CAD and tool vendors to develop and validate new flows and methodologies. Preferred qualifications BS/MS/PhD degree in Electrical Engineering; 4+ years of practical experience In-depth knowledge of EMIR tools such as Redhawk and Voltus Experience in developing and implementing power grid Good knowledge of system-level PDN and power integrity Practical experience with PnR implementation, verification, power analysis and STA Proficient in scripting languages (TCL/Perl/Python) Experience with industry standard EMIR tools such as Redhawk and Voltus Basic knowledge of the physical design flow and industry standard PnR tools Experience with scripting languages such as TCL, Perl and Python Ability to communicate effectively with cross-functional teams Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 7-14 yrs experience in Physical Design and timing signoff for high speed cores. Should have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology. Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design. Experience in leading block level or chip level Physical Design, STA and PDN activities. Work independently in the areas of RTL to GDSII implementation. Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.) Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.) Tcl/Perl scripting Willing to handle technical deliveries with a small team of engineers. Strong problem-solving skills. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.