930 Tcl Jobs

BE Mechanical/Electrical with 6-10 years of experience in the Energy/Manufacturing sector/Auto Sector Preferred candidates from high voltage industry Candidates will be responsible for - Procurement from Import and Domestic (Timely placement of PO's, ensuring on time delivery, incoterm, optimizing freight, timely forecasting etc) Procurement of casting ,machining, sheet metal, fabrication, electrical articles & equipment's (CT/VT/Panels etc)for production (assembly) ensuring freight optimization & product cost out for high voltage GIS(Gas Insulated Switchgear) upto 400kv. Inventory management -Ensuring ITR targets Built safety stocks for Delivery, quality critical parts ensuring lead times Initiate & drive cost out measures Explore new suppliers & expedite development Maintain business relationship with all supplier for best outcome Travelling /Visit to suppliers required. (As per business requirement) Excellent Communication skills (Written/Oral)

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Aprisa offers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. The detail-route-centric architecture and hierarchical database enable fast design closure and optimal quality of results at a competitive runtime. This role is based in Bangalore. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. This is your role Lead a Team of Engineers working on solving the latest design challenged in Logic Synthesis Collaborate with RnD and drive the roadmap for next generation RTL2GDSII solution. Work with design community in solving critical designs problems to achieve desired performance, area and power targets. Deployment of Synthesis solution with various customers working on cutting edge technologies (7nm and forward). Develop & deploy training and technical support to customers using Siemens EDA tools. We don’t need superheroes, just superminds! Typically requires minimum of 9+ years of experience in Logic Synthesis flows Proficiency in Verilog, System Verilog & VHDL. Strong knowledge of RTL2GDSII flow with strong fundamentals in digital design & implementation. Prior experience in IC digital design flows and front-end EDAT tools including Synthesis, DFT, Formal Verification, Logic Equivalence Checks Hands-on experience using commercial synthesis tools like Synopsys-DC/FC, Cadence-Genus is a must. Experience with advance technology nodes 7nm and below. Hands-on experience in debug & deliver solutions to critical design issues related to synthesis. TCL, Perl or Python scripting is a plus. Self-motivated team player with a zeal to drive high team performance. Good problem solving and debugging skills. Strong verbal & written communication skills We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #LI-EDA #LI-Hybrid

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 1-3 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Project Role : Application Developer Project Role Description : Design, build and configure applications to meet business process and application requirements. Must have skills : SAP S/4HANA Embedded Production Planning and Detailed Scheduling (EPPDS) Good to have skills : NAMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary Experience in Production Planning and Detailed Scheduling in SAP S/4HANA embedded PP/DS Planning Demand in the Supply Chain Roles & ResponsibilitiesExperience in Production Planning and Detailed Scheduling in SAP S/4HANA embedded PP/DS.- Expected to be an SME.- Collaborate and manage the team to perform.- Responsible for team decisions.- Engage with multiple teams and contribute on key decisions.- Provide solutions to problems for their immediate team and across multiple teams.- Facilitate knowledge sharing sessions to enhance team capabilities.- Monitor project progress and ensure timely delivery of application features. Professional & Technical Skills: Production Planning Results Evaluation:Production Planning executing and evaluating the Planning Run Results with Alerts Planning Procedure:Configuring Basic Parameters for Planning / Executing the Production Planning Run / Planning a Product Using the Planning Procedure Order Creation with Product Heuristics:Using Demand Management in PP/DS / Planning Make-to-Order Production Using PP/DS / Using Firming in PP/DS / Configuring Product Heuristics Scheduling in Production Planning:Determining the Source of Supply of the Order / Scheduling Operations with the Strategy Profile / Scheduling a Planned Order for Production Pegging in Production Planning:Configuring Dynamic and Fixed Pegging Scheduling Operations with the Detailed Scheduling Planning BoardPlanning Production with Detailed Scheduling Strategies and Heuristics / Managing Setup Times with the Setup Matrix / Managing Scheduling with the PP/DS Optimizer. Qualification 15 years full time education

As a Logic design lead in the IBM Systems division, you will be responsible for the micro architecture, design and development of a high-bandwidth, low-latency on-chip interconnect (NoC) and chip-to-chip interconnect and integration into high-performance IBM Systems. Design and architect different interconnect topologies as driven by bandwidth, latency and RAS requirements Develop the features, present the proposed architecture in the High level design discussion Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW teams to develop the feature Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in silicon bring-up and validation of the hardware Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8+ years of relevant experience - At least 1 generation of processor interconnect design delivery leadership (eg UPI, axi, amba, NoC). - Expertise of SMP coherency - Experience in different on-chip interconnect topologies (e.g., mesh, crossbar) - Understanding of various snoop and data network protocols - Understanding of latency & bandwidth requirements and effective means of implementation - Working knowledge of queuing theory - numa/nuca architecture - Proficient in HDLs- VHDL / Verilog - Experience in High speed and Power efficient logic design -Experience in working with verification, validation, physical design teams for design closure including test plan reviews and verification coverage - Good understanding of Physical Design and able to collaborate with physical design team for floor planning, wire layer usage and budgets, placement of blocks for achieving high-performance design - Experience in leading uarch, RTL design teams for feature enhancements.

Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Required technical and professional expertise 5-8 years industry experience in physical design methodology. Good knowledge andhands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical verification ( LVS,DRC. etc), Noise analysis, Power analysis and electro migration . Team player with good problem solving skills, communication skills and leadership skills. Preferred technical and professional experience Automation skills in PYTHON, PERL , and/or TCL

Manage, organise, plan and lead a team of expert testing & instrumentation engineers for successful fulfillment of project requirements for various clients in the domains of Vehicle Dynamics, Brakes, NVH testing and training services under the supervision of the Head of Chassis & Active Safety. Perform dynamic tests on proving grounds and public roads as required for passenger cars and light commercial vehicle's projects independently Perform dynamic test data analysis, mainly through in-house developed software's include pre/post processing of the experimental data to check the vehicle dynamics behavior of the tested vehicle and being able to explain the root of the phenomena happening independently. Demonstrate, present and justify technical decisions based on test & report data to internal teams & clients for vehicle attribute development under the guidance of the Head of Chassis & Active Safety. Manage client interaction, client project reporting and support with sales presentations under the supervision of the Head of Chassis & Active Safety. Ensure occupational health and safety and IDIADA quality process is adhered to at all times in the department under the guidance of the Head of Chassis & Active Safety. Train and develop a team of vehicle dynamics instrumentation and test engineers to meet IDIADA global testing standards and monitor skill matrix and technical competency development

About the job Responsibilities Exciting opportunity to work on Digital Flows/Methodologies architecture and development in energetic EDA team. Enable EDA flows and ensure tools are qualified on cutting edge IPs before rolling them to the wider community. Develops, maintains, debugs and tests SOC Design Methodologies using Commercial EDA tools Defines and creates flows/scripts to help design teams execute Front-End (RTL) to Back-End (GDS) flows seamlessly Take ownership, lead project and deliver results while guiding other engineers Verify CAD flows are generating correct results (flow signoff) and setup tool regressions Work closely with Engg IT and Database Mgmt teams to setup flows which work well with the Engineering Compute Infra in MaxLinear Datacenters Drive consensus across business units on tool & design methodology Work closely with technology and design teams to resolve signoff criteria Support design engineers on the flow setup and resolve their queries Qualifications MS/BS in Electrical/Computer Engineering with demonstrated experience in CAD or EDA tools flows architecture, development and support Demonstrated experience with various EDA software, flows and architectures & driving EDA vendors to improve tools to implement new functionality to solve problems or to optimize existing methods Must have worked on Digital flows/methodologies development in the domain of PD or DV. Should have proficient skills with one of PD related tools Genus/ Innovus /Tempus/ Calibre /FC/PT/DC. ( Or ) Should have proficient skills with one of DV related tools Xcelium /Questa/VCS/ vManager or equivalent. Must have strong scripting abilities in Python and/or Perl, tcl ; Must have UNIX knowledge and experience with data-management software Must have experience in taking ownership, leading projects along with guiding other engineers and producing results Ability to document design methodologies & provide training on tools and workflows to design teams Experience with Front-end Digital Design and/or PD and/or Digital Verification methodologies with a focus on digital and mixed-signal solutions Experience in defining and developing PD flow methodologies using Cadence/Synopsys/Siemens tools Strong skills in debugging and analyzing techniques to understand existing scripts/flows; Ability to work independently and explore new domains Proven track record of pushing Prior experience debugging vendor tool problems Strong written and verbal interpersonal skills and track record of success in a collaborative team environment Show more Show less

We are seeking a skilled and detail-oriented EDA Software Quality Assurance Engineer to join our team on a contract basis. The ideal candidate will be responsible for writing unit tests, validating Vivado FPGA Implementation Software, and ensuring that existing software tests do not regress. This role requires a strong understanding of software testing methodologies and experience in the EDA domain, particularly with Vivado FPGA tools. Key Responsibilities: • Develop and maintain unit tests for EDA software focused on Vivado FPGA implementation to ensure high-quality code. • Validate Vivado FPGA software functionality and performance through rigorous testing. • Monitor and ensure that existing software tests do not regress, maintaining the integrity of the software. • Collaborate with development teams to identify and resolve software defects. • Document test cases, test results, and any issues identified during testing. • Provide feedback and recommendations for improving software quality and testing processes. Required Qualifications and Skills: • Bachelor's degree in Computer Science or Electronics Engineering • Proven experience in software testing, particularly in EDA domain and Vivado tools. • Excellent problem-solving skills and attention to detail. • Ability to work independently and as part of a team. • Strong communication skills, both written and verbal. Preferred Qualifications: • Experience with specific EDA tools and software, especially Vivado FPGA. • Knowledge of programming languages commonly used in EDA software development (e.g., C++, Python, Tcl). • FPGA hardware testing experience is a plus. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job Summary: We are looking for a candidate with excellent communication skills and ability to ramp up on new technologies quickly and independently. This an excellent opportunity to work in a supportive and friendly work environment, where we are vested in each other’s success, and are passionate about technology and innovation. Qualifications: BE/BTech/ME/MS/MTech in Computer Science/Electronics/Electrical Engineering Job Responsibilities: Develop and enhance EDA software. Write functional specifications as necessary Experience and Technical Skills required 2+ years of software development experience in C++ coding, with hands-on project experience with distributed computing/multithreading. Good algorithm background, and implementation experience in dealing and processing of large amount of data Knowledge in UNIX shell and scripting language like TCL/Perl/Python Knowledge and implementation experience with computational geometry, layout connectivity, parasitic extraction, LEF/DEF is a big plus Behavioral skills required Work effectively across functions and geographies Possess good written, verbal and presentation skills We’re doing work that matters. Help us solve what others can’t.

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Responsibilities & Skills Lattice is seeking candidates for the position of Sr EDA SW Dev Engineer. This is a full-time position located in Pune, India. Accountabilities Develop and deliver state-of-art design, architecture and device database and software infrastructure for world-class ease-of-use Lattice FPGA software tool for small, mid-range and large FPGA products. Develop software capabilities for next generation of Lattice FPGA products. Support and maintain existing Lattice FPGA design tools. Learn and contribute to Spec and Plan process - review marketing requirement documents, generate functional specifications and developer unit test plans to ensure quality software. Improve development methodologies and processes. Qualifications BS/MS/PhD Electrical Engineering or Computer Science 5+ years of experience in large-scale software development for engineering application domains, preferably in FPGA/ASIC Design Automation Must be proficient with C++. Modern C++ proficiency is a plus Strong background in Software Architecture, object-oriented programming, data structures and algorithms, Design Patterns Experience of working on multiple platforms – at least Linux and Windows – is required. Knowledge of shell, Tcl or Python scripting is a plus. Familiarity with commercial FPGA software tools and design flow is a plus. Knowledge in FPGA logic design is a plus. Must be detail oriented and possess independent problem-solving skills. Must be able to drive projects and lead a discussion. Strong written and verbal communication skills, and collaboration skill with the ability to work with multiple groups. Show more Show less

Ciena is committed to our people-first philosophy. Our teams enjoy a culture focused on prioritizing a personalized and flexible work environment that empowers an individual’s passions, growth, wellbeing and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. How You Will Contribute CIENA's Packet Optical products portfolio comprises of a broad family of products for Aggregation, Metro and Core Optical networks. Successful candidate for the role of SVT/PV Engineer will be responsible for developing feature and solution test strategies, test plans, and test execution for Ciena’s Packet Optical products based on technologies such as OTN Transport/Switching, Control Plane, and associated Network Management System. Essential Duties And Responsibilities Knowledge of Product Architecture, Product Features & associated Standards, Network Use-Case Scenarios and Test Automation Develop Test Plans to validate Telecom Network Use Cases and product capabilities. Identify Test Scenarios for Automated Test Execution, work with Automation team on new APIs and develop Automation Test Suites for new features. Participate in Test Plan reviews and contribute to reviews held by Test and Design Teams Execute test cases, analyze test results, file defect reports, and verify defect fixes. Analyze and characterize defects found during test execution and work closely with the design on debugging and closure of issues. Must Have Expertise in OTN Transport, Switching, Control Plane technologies, Automation Development using TCL/Python. Exposure to photonics/DWDM, NMS and packet technologies would be a plus. Ability to understand customers’ needs, expectations, and perspective. Knowledge of Transport Network Design of Telecom Service Providers and Content Provider Networks, and experience of working with R&D team on product defects in Customer Networks. Experience in test effort estimation and captive resource planning based on Requirement Specifications would be a plus Experience in Test Planning to validate Telecom Network Solutions and Use Case Scenarios that include interactions of different product features, including NMS Experience in developing Automation Scripts in tcl and/or Python Strong analytical and problem-solving skills; experience of working closely with design engineers for debugging of product defects. Strong communication and inter-personal skills to effectively communicate and collaborate with Test and Design teams in India and North America. Knowledge of relevant ITU-T, IETF, IEEE and ANSI standards. Proficient with a wide range of test equipment. Bachelors or Masters in Electronics Engineering, Computer Science, or Optical Communications with 4+ years of relevant experience of system test in telecommunications domain Not ready to apply? Join our Talent Community to get relevant job alerts straight to your inbox. At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require. Show more Show less

Responsibilities: Assist in the development and validation of PDKs for various process nodes. Support the integration of technology files, DRC/LVS decks, and device models into EDA tools (e.g., Cadence, Synopsys). Write and maintain automation scripts (e.g., Python, TCL, Shell) to streamline PDK development processes. Collaborate with layout, design, and modeling teams to ensure PDK accuracy and usability. Troubleshoot and fix issues in PDK components related to DRC, LVS, parasitic extraction, and schematic symbols. Document PDK features, known issues, and development changes. Show more Show less

Position: DFT Engineer (ASIC) Experience: 2 to 8 years Location: Hyderabad Job Summary: We are seeking a talented DFT (Design for Testability) Engineer with expertise in ASIC design and a strong background in EDA tools such as Synopsys . The ideal candidate will have hands-on experience in developing, implementing, and optimizing DFT architectures to ensure high test coverage and manufacturability. Key Responsibilities: Design and implement DFT methodologies for ASIC projects, including scan insertion, ATPG, and BIST. Work with EDA tools from Synopsys (such as TetraMAX, DFT Compiler, TestMAX, etc.) to achieve high test coverage and efficient test solutions. Develop and validate test strategies for scan-based testing, MBIST, and boundary scan. Collaborate with RTL and physical design teams to ensure seamless DFT integration. Perform fault simulations , analyze test results, and drive improvements in test efficiency. Optimize DFT architectures for low-power, high-performance, and manufacturability . Support silicon bring-up and debug of test patterns on actual hardware. Work closely with foundries and test teams to ensure smooth production testing. Keep up to date with the latest DFT methodologies, trends, and innovations. Required Skills & Qualifications: 4+ years of experience in DFT implementation for ASIC designs. Proficiency in Synopsys EDA tools for test implementation and validation. Solid understanding of digital design, scan insertion, ATPG, and BIST . Experience with fault modeling, test coverage analysis, and debugging . Strong scripting skills in Python, Perl, or TCL for automation. Ability to work in a multi-disciplinary team and communicate technical concepts effectively. Preferred Qualifications: Experience with Post-Silicon Debug and ATE Testing . Knowledge of Verilog/VHDL and simulation tools . Familiarity with industry-standard DFT flows and methodologies . Show more Show less

Tenstorrent is at the forefront of cutting-edge AI technology, redefining what’s possible in performance, usability, and cost. As AI transforms the computing landscape, it demands integrated innovation across software models, compilers, platforms, networking, and semiconductors. Our team—diverse, curious, and driven—has built a high-performance RISC-V CPU from the ground up and shares a collective passion for advancing AI. We thrive on collaboration and tackling tough challenges, and we’re expanding our team across all experience levels. We’re looking for an experienced CPU/IP / SoC Physical Verification Engineer who can take ownership of full-chip and block-level physical verification across our complex RISC-V based designs. This role is ideal for someone who thrives in a fast-paced, collaborative environment, enjoys solving challenging problems across advanced technology nodes, and is passionate about building clean, manufacturable silicon. What You’ll Be Doing Drive physical verification activities (DRC, LVS, ERC, PERC, Antenna, DFM) from block to full-chip level. Collaborate closely with RTL, PD, CAD, and packaging teams to ensure sign-off readiness. Debug verification issues and work hands-on with tools like Calibre and ICV to root-cause violations. Support ESD planning, padring integration, and bump/RDL layout strategies. Contribute to PV methodology improvements and automation scripts. Lead PV closure for key tapeouts and provide mentorship to junior engineers on the team. Interface with foundry teams for rule deck alignment and tapeout planning. What We’re Looking For 6 to 14 years of hands-on experience in CPU/IP / SoC physical verification. Solid command of physical verification tools and flows (Calibre, ICV, ICC2, Innovus, etc.). Strong understanding of advanced node requirements (7nm, 5nm, 3nm), including FinFET challenges. Proficiency in checking and resolving DRC, LVS, ERC, and PERC violations. Comfortable scripting in Python, TCL, or Perl to automate workflows and debug processes. Awareness of ESD, IR drop, EM, and reliability considerations in full-chip designs. Clear communication and a strong sense of ownership — you enjoy working across teams and taking designs across the finish line. Show more Show less

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: FPGA Engineer Location : Hyderabad Work Type: Onsite Job Type: Full time Job Description: Design, implementation, test, integration, and delivery of system level digital designs for FPGA blocks timing verification Perform task of debugging design timing related issues on different FPGA families Perform the work of manifold segmentation of the FPGA designs. Run internal scripts for performance testing and update scripts when necessary Required skill Basic STA knowledge along with tools like Vivado. Experience on FPGA platforms like AMD(XILINX)/Altera. Expertise in digital hardware designing using Verilog on large AMD(Xilinx)/altera FPGAs Experience in scripting language like perl, python and tcl Working experience on Linux. Ensure to complete design and timing verification tasks within allotted timelines. Ability to work individually and in a team TekWissen® Group is an equal opportunity employer supporting workforce diversity. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job Summary: We are looking for a candidate with excellent communication skills and ability to ramp up on new technologies quickly and independently. This an excellent opportunity to work in a supportive and friendly work environment, where we are vested in each other’s success, and are passionate about technology and innovation. Qualifications BE/BTech/ME/MS/MTech in Computer Science/Electronics/Electrical Engineering Job Responsibilities Develop and enhance EDA software. Write functional specifications as necessary Experience And Technical Skills Required 2+ years of software development experience in C++ coding, with hands-on project experience with distributed computing/multithreading. Good algorithm background, and implementation experience in dealing and processing of large amount of data Knowledge in UNIX shell and scripting language like TCL/Perl/Python Knowledge and implementation experience with computational geometry, layout connectivity, parasitic extraction, LEF/DEF is a big plus Behavioral Skills Required Work effectively across functions and geographies Possess good written, verbal and presentation skills We’re doing work that matters. Help us solve what others can’t. Show more Show less

Job Description Job Description : We are looking for a highly skilled & experienced PD expert to join our Flows & Methodologies team. The candidate must be experienced, hands-on and have robust understanding of physical design including Floorplan, Power-plan, Place & Route, UPF, CTS. This role requires strong analytical skills, attention to detail, and the ability to work collaboratively with cross-functional teams. Proficiency in relevant EDA tools and a solid understanding of digital design principles are essential for success in these positions Scope Of Responsibilities As part of the Design Enablement team of the organization, you need to work closely with SoC cross functional teams to develop and define Physical Design methodology to meet SoC & IP level objectives on low geometry nodes (3/5/16nm) Your scope of work will cover tools and flows definition, requirement management for SoC Place & Route, UPF, Formal Verification, Floorplan & Power-Plan You will work with EDA Vendors to proactively review latest tools and flows offerings in Physical Implementation domains. Evaluate latest offerings and benchmark with organization used tools, flows, and methodologies. Work with EDA Vendors to review and resolve blocking issues You will be an actor of change for deploying new tools & methodologies across the organization Qualifications Specific skills & knowledge : Bachelor or Master or Ph.D. in Electronics Engineering and specialization in VLSI domain 10+ years of hands-on experience in Physical Design : UPF, Formal & Physical verification, floorplan, power-plan, Place & Route Proven experience in delivering physical implementation closure methodology ensuring timing & physical convergence Experience in Synopys & Cadence tool sets (Fusion Compiler, Innovus) , low geometry node issues, working with EDA team in reviewing & resolving blocking issues in project Experience in customizing flows & methodology to meet low power & area objectives of SoC Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Can – do attitude, openness to new environment, people and culture Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus Ability to work independently and as part of a team Additional Information Renesas Electronics Corporation empowers a safer, smarter and more sustainable future where technology helps make our lives easier. The leading global provider of microcontrollers, Renesas combines our expertise in embedded processing, analog, power and connectivity to deliver complete semiconductor solutions. These Winning Combinations accelerate time to market for automotive, industrial, infrastructure and IoT applications, enabling billions of connected, intelligent devices that enhance the way people work and live. Learn more at www.renesas.com. Renesas’ mission, To Make Our Lives Easier, is underpinned by our company culture, TAGIE. TAGIE stands for Transparent, Agile, Global, Innovative and Entrepreneurial. Our goal is to embed this unique culture in everything we do to succeed as a company and create trust with our diverse colleagues, customers and stakeholders. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Renesas Electronics Corporation empowers a safer, smarter and more sustainable future where technology helps make our lives easier. The leading global provider of microcontrollers, Renesas combines our expertise in embedded processing, analog, power and connectivity to deliver complete semiconductor solutions. These Winning Combinations accelerate time to market for automotive, industrial, infrastructure and IoT applications, enabling billions of connected, intelligent devices that enhance the way people work and live. Learn more at www.renesas.com. Renesas’ mission, To Make Our Lives Easier, is underpinned by our company culture, TAGIE. TAGIE stands for Transparent, Agile, Global, Innovative and Entrepreneurial. Our goal is to embed this unique culture in everything we do to succeed as a company and create trust with our diverse colleagues, customers and stakeholders. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Show more Show less

Job Role: Teamcenter Developer Job Location: Chennai, Bangalore, Hyderabad, Pune Exp level: 4+years relevant into required PLM skill. Education : Bachelor’s degree in Engineering or relevant discipline Technical/Functional Skills Must have hands-on experience working with Teamcenter 10 Java / J2EE and C / C++ programming languages – Advanced Eclipse framework IDE – Functional Siemens Teamcenter PLM BMIDE (Business Model Integrated Dev. Environment) – Functional Siemens Teamcenter PLM ITK (Integrated Toolkit) – Advanced Siemens Teamcenter PLM SOA (Service Oriented Architecture) – Functional Siemens Teamcenter PLM Workflow / Custom Handler development – Advanced NX UFUNC programming Experience with scripting languages like Shell/Perl/python/TCL. Roles & Responsibilities Develop and customize Teamcenter PLM solutions based on business requirements. Create and maintain Teamcenter modules, workflows, and processes. Implement customizations using BMIDE (Business Modeler IDE) and other tools to extend Teamcenter functionality. Work on Teamcenter integrations with other enterprise systems such as ERP, CAD, and MES. Develop and implement custom API and web services for seamless communication between Teamcenter and external systems. Utilize programming languages such as Java, C++, and ITK (Integration Toolkit) for customization and extension of Teamcenter. Provide day-to-day technical support to users and troubleshoot issues related to Teamcenter. Resolve system errors, performance issues, and software bugs in a timely manner. Perform system upgrades and patches as needed. Develop test plans, test cases, and perform system testing to ensure Teamcenter solutions meet business requirements and quality standards. Document code, processes, and customizations to ensure maintainability and consistency. Collaborate with business analysts and project managers to understand requirements and translate them into technical solutions. Work closely with cross-functional teams such as IT, PLM specialists, and business users to ensure proper implementation and adoption of Teamcenter solutions. Assist in training and mentoring junior developers and team members. Show more Show less

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! We are seeking an innovative Senior Physical Design & Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and SoCs. This position is a broad opportunity to optimize performance, yield, and reliability through increasingly comprehensive modeling, insightful analysis, and automation. This work will influence the entire next generation computing landscape through critical contributions across NVIDIA's many product lines ranging from consumer graphics to self-driving cars and the growing domain of artificial intelligence. We have crafted a team of highly motivated people whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. If you are fascinated by the immense scale of precision, craftsmanship, and artistry required to make billions of transistors function on every die at technology nodes as deep as 3 nm, this is an ideal role. What You Will Be Doing Collaborate with technology leads, circuits and systems teams, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies of signing off timing in design for world-class silicon performance. Understand corner case timing sign-off risks in the latest 3nm and deeper technology nodes. Develop strategies to mitigate and margin for them. Develop tools and methodologies to improve design performance, predictability, and silicon reliability beyond what industry standard tools can offer. Extensively work with our ASIC Physical Design team to help develop methodologies, flows, and tools across a wide spectrum of domains - STA, constraints, floorplanning, timing and power optimization. Develop world class work flow solutions to aid analysis and improve flow efficiency. What We Need To See Master’s Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent work experience 4+ years of relevant work experience Deep understanding of backend design process, especially advanced STA. In depth understanding of PT and/or Tempus Expertise in coding -- TCL, Perl, Python. C++ is a plus! Strong communication and interpersonal skills Ways To Stand Out From The Crowd Expertise in developing advanced STA flows JR1995670 Show more Show less

Company Description Pushing the Edge VANTIVA, headquartered in Paris, France and formerly known as Technicolor, is a global technology leader in designing, developing and supplying innovative products and solutions that connect consumers around the world to the content and services they love – whether at home, at work or in other smart spaces. VANTIVA has also earned a solid reputation for optimizing supply chain performance by leveraging its decades-long expertise in high-precision manufacturing, logistics, fulfillment and distribution. With operations throughout the Americas, Asia Pacific and EMEA, VANTIVA is recognized as a strategic partner by leading firms across various vertical industries, including network service providers, software companies and video game creators for over 25 years. Our relationships with the film and entertainment industry goes back over 100 years by providing end-to-end solutions for our clients. VANTIVA is committed to the highest standards of corporate social responsibility and sustainability across all aspects of their operations. For more information, please visit www.vantiva.com and follow us on LinkedIn and Twitter. Job Description 6 - 8 years of experience in CPE testing, with a focus on functional testing, performance, and reliability. Strong understanding of Oops concept & Hands on in Java programming | Selenium knowledge is strong plus. Proficient in debugging and troubleshooting complex issues with solid understanding of networking technologies like, CMTS, OLT, 5G and DSLAM. Strong believer in creating impact thru Test automation with hands on experience in Java/Selenium | Python scripting experience is a plus Hands-on experience in WiFi, Ethernet and voice testing is a strong plus. Excellent stake holding & communication skills (written & verbal). Key Responsibilities Perform WIFI, Ethernet and voice testing, in the RDK-B or OpenWRT based firmware. Test and validate functionality of the broadband devices with the core components like CMTS/OLT/DSLAM/5G equipment. Work with CWMP suite of protocol for remote management and configuration of customer-premises equipment (CPE). Perform with ‘Intent to break’ approach in testing, Strong analytical skills with curiosity to triage/debug for root cause analysis/troubleshooting on issues uncovered, and intent work with the engineering team to resolve them. Ability to parallel tasking under tight timeline, result driven approach with adequate contingency planning Stay updated with the latest industry trends and technologies to continuously improve testing methodologies. Qualifications Key Skills: Strong knowledge in WiFi testing (all standard, preferably 802.11BE), DOCSIS or GPON/XGS-PON, TR-069 protocol, and Python/Java automation. Handson Expertise in throughput testing of WLAN solution, specifically 802.11be with MLO technology Good understanding of OpenWRT, and RDK platforms. Proficiency in Easy Mesh R4,5,6 standards and hands on experience on testing various network topologies Familiar with TR69/USP, Routing, UPnP, Firewall, content sharing, NAT, TR398, TR181 Routing protocols will be an added advantage Hands on expertise with any of the testing tools like STC, IXIA IP Performance testing, AirPcaP with Wireshark, ixCharoit, CD Router, Octoscope etc., Java Programming experience along with Scripting knowledge in either Selenium / Python for test automation. Good understanding of network testing procedures and methodologies. Additional Skills/Experiences Experience in Automatics or TCL programming is welcome advantage. Strong expertise in networking protocols and concepts, including TCP/IP, Ethernet, and Wi-Fi standards. Additional Information Vantiva is an EOE/Veterans/Disabled/LGBT employer : Vantiva is proud to be an equal opportunity workplace. We will consider all qualified applicants for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other basis protected by applicable law. Our most important asset is our People Vantiva’s success greatly relies on our people’s energy, motivation, and talent. We are dedicated to cultivating a workforce that embraces and celebrates diversity as we believe our differences drive our creativity, and innovation. We are proactive in supporting equality and maintaining an inclusive work environment, developing, and enhancing career opportunities for all. If you require a reasonable accommodation at any step of the application process, please let us know by answering the dedicated question in this application form. Our most important asset is our People Vantiva’s success greatly relies on our people’s energy, motivation, and talent. We are dedicated to cultivating a workforce that embraces and celebrates diversity as we believe our differences drive our creativity, and innovation. We are proactive in supporting equality and maintaining an inclusive work environment, developing, and enhancing career opportunities for all. If you require a reasonable accommodation at any step of the application process, please let us know by answering the dedicated question in this application form. Show more Show less

The HiLabs Story HiLabs is a leading provider of AI-powered solutions to clean dirty data, unlocking its hidden potential for healthcare transformation. HiLabs is committed to transforming the healthcare industry through innovation, collaboration, and a relentless focus on improving patient outcomes. HiLabs Team Multidisciplinary industry leaders Healthcare domain experts AI/ML and data science experts Professionals hailing from the worlds best universities, business schools, and engineering institutes including Harvard, Yale, Carnegie Mellon, Duke, Georgia Tech, Indian Institute of Management (IIM), and Indian Institute of Technology (IIT). Responsibilities Interpret business requirements, define technical alternatives, and participate in information gathering for interface requirements Develop, test, implement and document the technical solution to address the defined business requirements Develop and implement EDI HL7 and XML interfaces in accordance to Department Process/Standards Configuration and maintenance of Global Monitor and Security Work with other team members to define effort estimates, timetables, and project plans Participate with the development team and IT staff as appropriate in the design of solutions Educates and directly interacts with stakeholders to help them understand the benefits and limitations of their specific EMR/LIS-Interface during implementation Collaborate with other technical areas to integrate across tiers, platforms, and Responsibilities Ensure that expected application performance levels are achieved Plans and conducts module and basic integration testing Manage technical aspects of application to ensure timely and effective implementations Understand and comply to Project Life Cycle Methodology in all planning steps Responsible for multiple implementations or conversion projects Provides direct interaction with client and client’s vendor Designs and oversees interface implementation project plan Desired Profile Bachelor’s degree in appropriate discipline is preferred Cloverleaf Level 2 Certified 5 or more years of relevant experience is considered an experienced and seasoned professional Extensive experience with Cloverleaf Integration Services Experience building CCDA, VRL, HL7v2 ,HL7 FHIR (JSON) interface in CL 19.*v and beyond Knowledge on HL7 standards (v2,CDA, FHIR) Experience with VM-based Unix/Linux platforms Experience with data formats including HL7, XML, JSON Knowledge of scripting languages including TCL, TDOM programming, Java, JavaScript, experience in building webservice, Restful API interfaces Knowledge of Clinical integrations Experience working on Cloverleaf Consolidator (ICC) Tool Strong experience with a commercial Integration Engine Product (i.e., Cloverleaf) Experience using Jira Experience with HIE and integration platforms used within the health services industry (e.g., InterSystems, Medicity, Orion, etc.) Relevant experience in a healthcare setting working with the following HL7 transaction sets: ADT, VXU, ORM, MDM, SIU Familiarity with relational & non-relational databases such as MySQL, Postgres, Oracle, SQL Server, Mongo DB, Cassandra, IRIS/Caché Experience working in Agile development team Experience with SFTP is preferred CCPA disclosure notice - https://www.hilabs.com/privacy HiLabs Total Rewards Competitive Salary, Accelerated Incentive Policies, H1B sponsorship, Comprehensive benefits package that includes ESOPs, financial contribution for your ongoing professional and personal development, medical coverage for you and your loved ones, 401k, PTOs & a collaborative working environment, Smart mentorship, and highly qualified multidisciplinary, incredibly talented professionals from highly renowned and accredited medical schools, business schools, and engineering institutes. CCPA disclosure notice - https://www.hilabs.com/privacy Show more Show less

Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com. Job Description PostgreSQL Database admin Proficient with Postgres installation and configuration, particularly Postgres Plus Advanced Server from EnterpriseDB and AWS RDS Aurora PostgreSQL. Proficient with Postgres monitoring and alerting tools/processes, specifically PEM from EnterpriseDB. Proficient in the setup, configuration, and monitoring of PostgreSQL binary and logical data replication solutions (Binary Streaming, XDB, Bi-Directional Replication - BDR, etc.). Proficient with collecting diagnostics and tuning PostgreSQL as well as SQL tuning. Proficient with Postgres procedural languages (PL/pgSQL, PL/Tcl, PL/Perl, PL/Python) and SQL. Proficient in designing and supporting Postgres clustered environments. Monitoring and observability with tools like Splunk and Dynatrace. Experience in Postgres replication technologies. Perform debugging, tuning, and performance enhancement, as well as automation of operational and continuous integration aspects of the Postgres platforms. Proficient with the Linux operating system, specifically Oracle Linux Enterprise. Intermediate understanding of logical and physical data models.E Exp - 10 + years CBR - 130K Location - pune Notice - Immediate ͏ Do Provide adequate support in architecture planning, migration & installation for new projects in own tower (platform/dbase/ middleware/ backup) Lead the structural/ architectural design of a platform/ middleware/ database/ back up etc. according to various system requirements to ensure a highly scalable and extensible solution Conduct technology capacity planning by reviewing the current and future requirements Utilize and leverage the new features of all underlying technologies to ensure smooth functioning of the installed databases and applications/ platforms, as applicable Strategize & implement disaster recovery plans and create and implement backup and recovery plans Manage the day-to-day operations of the tower Manage day-to-day operations by troubleshooting any issues, conducting root cause analysis (RCA) and developing fixes to avoid similar issues. Plan for and manage upgradations, migration, maintenance, backup, installation and configuration functions for own tower Review the technical performance of own tower and deploy ways to improve efficiency, fine tune performance and reduce performance challenges Develop shift roster for the team to ensure no disruption in the tower Create and update SOPs, Data Responsibility Matrices, operations manuals, daily test plans, data architecture guidance etc. Provide weekly status reports to the client leadership team, internal stakeholders on database activities w.r.t. progress, updates, status, and next steps Leverage technology to develop Service Improvement Plan (SIP) through automation and other initiatives for higher efficiency and effectiveness ͏ Team Management Resourcing Forecast talent requirements as per the current and future business needs Hire adequate and right resources for the team Train direct reportees to make right recruitment and selection decisions Talent Management Ensure 100% compliance to Wipro’s standards of adequate onboarding and training for team members to enhance capability & effectiveness Build an internal talent pool of HiPos and ensure their career progression within the organization Promote diversity in leadership positions Performance Management Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below Employee Satisfaction and Engagement Lead and drive engagement initiatives for the team Track team satisfaction scores and identify initiatives to build engagement within the team Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team Exercise employee recognition and appreciation ͏ Deliver No Performance Parameter Measure 1 Operations of the tower SLA adherence Knowledge management CSAT/ Customer Experience Identification of risk issues and mitigation plans Knowledge management 2 New projects Timely delivery Avoid unauthorised changes No formal escalations ͏ Mandatory Skills: PostgreSQL Database Admin. Experience: 5-8 Years. Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com. Job Description Physical Deisgn Lea Location: Bangalore / Hyderabad / Pune Experience - 8+ YoE In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl. Must have hands-on experience on Synopsys/Cadence tools. (Innovus, ICC2, Primetime, PT-PX, Calibre). Well versed with timing constraints, STA and timing closure. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl · Well versed with timing constraints, STA and timing closure. ͏ Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify designs or repair equipment as needed e. Allocates modules for testing and verification and reviews data and project documentation f. Provides guidance on technical escalations and review regression testing data g. Prepares documentation containing information such as test case and product scripts for IP and publishes it to the client for feedback and review h. Ensures all project documentation is complete and uploaded as per technical specifications required by the client 2. Provide customer support & governance of VLSI components & hardware systems a. Identify and recommend system improvements to improve technical performance b. Inspect VLSI components & hardware systems to ensure compliance with all applicable regulations and safety standards c. Be the first point of contact to provide technical support to client and help debug specific, difficult in-service engineering problems d. Evaluate operational systems, prototypes and proposals and recommend repair or design modifications based on factors such as environment, service, cost, and system capabilities ͏ 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipro’s standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for ‘will’ based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation ͏ Deliver No. Performance Parameter Measure 1. Verification Timeliness, Quality and coverage of verification, Compliance to UVM standards, Customer responsiveness 2. Project documentation and MIS 100% on time MIS & report generation Complete Project documentation (including scripts and test cases) 3. Team % trained on new skills, Team attrition %, Employee satisfaction score (ESAT) ͏ Mandatory Skills: VLSI Physical Place and Route. Experience: 5-8 Years. Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

The role This position is a unique opportunity to exercise your hardware verification skills on cutting edge designs within the prestigious PowerVR Hardware Graphics group. Here you will exercise your skills on key components that meet latest demands and improvements for graphics IP. You will: Oversee all verification activities for a GPU component or subsystem, from initial planning to final sign-off. Develop verification plans and build, maintain UVM testbench components. Monitor, track, and report verification metrics to ensure closure. Provide verification-focused feedback during design specification discussions. Implement UVM testbenches, including writing tests, sequences, functional coverage, assertions, and verification plans. Take ownership of task definition, effort estimation, and progress tracking. Contribute to the enhancement and evolution of GPU verification methodologies. Lead, mentor, and support team members in verification activities. Engage in design and verification reviews, suggesting improvements where necessary. About You Committed to making your customers, stakeholders and colleagues successful, you’re an excellent communicator, listener and collaborator who builds trusted partnerships by delivering what you say, when you say. You’re curious, solutions orientated and a world-class problem solver who constantly seeks opportunities to innovate and achieve the best possible outcome to the highest imaginable standard. You'll have: Demonstrated experience in developing verification environments for complex RTL designs. Strong understanding of constrained-random verification methodologies and the challenges of achieving verification closure. Ability to define verification requirements, determine implementation approaches, and design testbenches. Expertise in root-cause analysis of complex issues, with the ability to resolve them efficiently. Deep knowledge of SystemVerilog and UVM. Capability to develop and enhance verification flows. Familiarity with ASIC design methodologies, flows, and tools. Proficiency in planning, estimating, and tracking personal tasks. Experience managing multiple projects simultaneously. Strong communication skills for effectively conveying technical issues, both verbally and in writing. You might also have: Experience leading teams. Knowledge of Graphics, GPU, CPU, or SoC architectures. Experience with broader verification technologies, including formal property-based verification (FPV). Proficiency in coding and scripting using Python, TCL, Perl, SystemC, or C++. Understanding of functional safety standards such as ISO26262. Who We Are Imagination is a UK-based company that creates silicon and software IP designed to give its customers an edge in competitive global technology markets. Its GPU and AI technologies enable outstanding power, performance, and area (PPA), fast time-to-market, and lower total cost of ownership. Products based on Imagination IP are used by billions of people across the globe in their smartphones, cars, homes, and workplaces. We need your skills to help us continue to deliver technology that will impress the industry and our customers alike, ensuring that people everywhere can enjoy smarter and faster tech than ever before. So come join us if you're wanting that something more Bring your talent, curiosity and expertise and we’ll help you do the rest. You’ll be part of one of the world’s most exciting companies who are one of the leaders in semiconductor IP solutions. As a part of our team, you can help us transform, innovate, and inspire the lives of millions through our technology. Additional Information If you encounter accessibility barriers in the application process or if you have access needs and require support or adjustments to participate equitably in the recruitment process, please email recruitment@imgtec.com. Show more Show less