1559 Tcl Jobs

Work Experience 1. Good fundamentals in analog and mixed signal circuit concepts and topologies. 2. Experience working with mixed signal verification environment, simulation, and regression tools such as Cadence Virutuoso, Spectre, xCelium, Incisive, vManager, IMC 3. Ability to read analog schematics and extract related main functionality. 4. Familiar with Verilog based RTL coding and ASIC design methodology. 5. Experience in System Verilog for advanced verification methodologies such as assertions, constrained randomization, metric driven, and UVM. 6. Familiar with behavioral modelling of analog blocks using System Verilog (RNM) and VerilogAMS. 7. Experience in modelling analog & mixed signal blocks. 8. Some knowledge of UNIX shell scripting, Perl, Python and TCL scripting.

Job Description The position involves design verification of next generation IP’s /SoC’s with emphasis on verifying and signing off performance and power along with functionality by developing the needed RNM models . This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies including simulation, GLS . Candidate will require close interactions with Design, SoC , Validation, Synthesis & PD teams for design convergence. Candidate must be able to take ownership of IP/Block/SS verification. Responsibilities: To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems/IPs. Leading a project for AMS requirements is a value add. Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS) Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected Experience working on AMS Verification on multiple SOC’s or sub-systems Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations Candidates should have a good knowledge of analog and mixed signal electronics, test-plan development, tools and flows. Develop and execute top-level test cases, self-checking test benches and regressions suites Developing and validating high-performance behavior models Verifying of block-level and chip-level functionality and performance Team player with good communication skills and previous experience in delivering solutions for a multi-national client Tool suites : Predominantly analog (Cadence - Virtuoso). SPICE simulator experience Fluent with Cadence-based flow- Create schematics, Simulator/Netlist options etc. Ability to extract simulation results, capture in a document and present to the team for peer review Supporting silicon evaluation and comparing measurement results with simulations UVM and assertion knowledge would be an advantage Experience Level: 3-15 years in Industry , Work Location: Hyderabad , Bangalore. Education Requirements: Bachelor or Master’s degree in Electrical and/or Computer Engineering Minimum Qualifications: Proficient in at least one of the following languages: Verilog, SystemVerilog, VerilogAMS. Strong understanding of analog circuits, digital design processes, and top-level integration. Basic knowledge of PMIC and DC-DC converters. Excellent simulation debugging skills, with the ability to analyze waveforms and identify issues in schematics, models, or RTL. Proficient in Unix environment and shell scripting, with a basic understanding of Python.

About The Company Tata Communications Redefines Connectivity with Innovation and IntelligenceDriving the next level of intelligence powered by Cloud, Mobility, Internet of Things, Collaboration, Security, Media services and Network services, we at Tata Communications are envisaging a New World of Communications Job Description The role is responsible for commercial modelling and (or) bid management process of large and complex opportunities for a region. The role owns the commercial/financial build of major sales opportunities in the region. This would involve understanding of customer s commercial expectations, understanding of TCL product offering & solution proposed and developing a Win-Win commercial propositions. The role also facilitates effective bid qualification and is responsible for obtaining all necessary authorization for the successful completion of the bid. This is a tactical role with a significant mid-term impact on business unit overall results. Responsibilities Facilitate contract negotiations with legal, sales, commercial manager, and the customer, as needed. Reviewing key proposal from commercial governance perspective and advising sales team on deviations Manage the production of customer proposals, ensuring a win strategy is developed and executed to produce proposals and contain a compelling proposition to the customer, presentation of our solution and the value it brings to our customers. Initiate corrective action where necessary by forward planning and forecasting, to ensure optimum utilization of company resources and promote customer satisfaction. Manage high value financial contracts and assess changes potentially impacting the underlying business case. Awareness of commercial and legal risks and consequences. Facilitate effective bid qualification and obtain all necessary authorization for the successful completion of the bid. Working with sales teams to assist in bid / no bid decisions, bid strategies and partnering decisions. Own and maintain the bid risk register and the development of the mitigation strategies required. Flag any issues or risks to the appropriate resources within the business. The role may be an individual contributor or may lead a small team. Minimum Qualification & Experience experience in Finance preferred Desired Skill sets Experience in commercial operations or bid management roles Financial & business acumen, knowledge of the industry Analytical skills & strategic acumen Strong presentation & communication skills Proficiency in using MS Excel Ability to work with complex data sets. Highly analytical role that requires techno-commercial acumen Experience in developing complex pricing models and pricing strategies. Financial forecasting Conversant with financial accounting practices, such as taxation, balance sheet and overhead treatments.

Role Description Role Proficiency: Independently execute mid sized customer projects in any field of VLSI Frontend Backend or Analog design with minimal supervision Outcomes Work as an individual contributor owning any one task of RTL Design/Module. Provide support and guidance to engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc. Anticipate diagnose and resolve problems; coordinating as necessary with cross-functional teams On time quality delivery approved by the project manager and client Automate the design tasks flows and write scripts to generate reports Come up with novel ideas to reduce design cycle time and cost accepted by UST Manager and client Measures Of Outcomes Quality –verified using relevant metrics by UST Manager / Client Manager Timely delivery - verified using relevant metrics by UST Manager / Client Manager Reduction in cycle time cost using innovative approaches Number of papers published Number of patents filed Number of mandatory trainings attended adhering to training goals Outputs Expected Quality of the deliverables: Ensure zero bugs are present in the design / circuit design. Clean delivery of the design/module in-terms of ease in integration at the top level Meeting functional spec / design guidelines 100% without any deviation or limitation Documentation of tasks and work performed Timely Delivery Ensure project timelines as laid out by the client or program manager are met Meet intermediate tasks delivery for other team members to progress Calling out for help and support in the case of delay in tasks delivery New Skills Development Participate in training – skilling someone and also getting skilled in newer technologies Take up new areas of project development learn on the job and deliver Team Work Participation in team work and supporting team members at the time of need Able to take up additional tasks in-case of any team member(s) not available Able to hand hold junior team members to explain the project tasks and support to deliver Work dedication to go beyond the call of duty to ensure deadlines and quality are met Innovation & Creativity Approach towards repeated work by automating tasks to save design cycle time Participation on technical discussion training forum white paper etc Skill Examples Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (experience in one or more tools) Technical Knowledge:a. IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Strong Physical Design / Circuit Design / Analog Layout Knowledged. Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione. Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below Strong communication skills and ability to interact with team members and clients equally Strong analytical reasoning and problem-solving skills with attention to details Ability to understand the standard specs and functional documents Ability to deliver the tasks on-time in a quality fashion per quality guidelines and GANTT Well versed with the available EDA tools and able to use them efficiently Required technical skills and prior design knowledge to execute the assigned tasks Ability to learn new skills in-case required technical skills are not present at a level needed to execute the project Knowledge Examples Knowledge of project(s) in any of the design by executing – RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc. Understanding of the design flow and methodologies used in the designing Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the client / manager as per known skills Additional Comments Responsibility- Primary responsibility includes I/O, Macro Characterization, EDA View generation (Functional, Electrical and Physical) & Full package validation. He/she needs to be in constant contact with IP design experts to understand the IP design (schematic, Layout) & IP specification (more electrical characteristics and functional aspect). Must have skills: Excellent understanding of digital design concepts and CMOS fundamentals. Ability to quickly comprehend the functional and electrical specifications of custom/full custom IPs. Proficient in IO/Standard cells/Memory characterization flow using industry-standard tools such as Kronos, Liberate, and Silicon Smart. Strong understanding of various formats of liberty files, including NLDM, CCS, and LVF. Skilled in custom layout and schematic design/updates. Experienced in IP physical model generation (LEF, sign-off GDS, CDL) and conducting validation checks (DRC, LVS, ERC) with debugging skills. Proficient in behavioral modeling using Verilog/SystemVerilog and testbench writing. Experience in IBIS (Input/Output Buffer Information Specification) modeling is a plus. Excellent team player who is disciplined, adaptable, and possesses strong communication skills. Qualification & Experience B. Tech / M. Tech – Electronics/VLSI Engineering 3 to 7 years of professional experience in EDA/CAD View generation domain. Prior ST experience even as intern is preferred. Skills CAD Design engineer,Standard Cell,Cmos

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Responsibilities & Skills We are looking for a QA Engineer to join our Radiant QA team with a focus on programmer-related QA tasks . This role is ideal for someone with a strong interest in scripting, automation, and backend validation of FPGA programming flows. You will work closely with senior QA engineers and developers to ensure the reliability, performance, and correctness of the Radiant programming tools and flows. Key Responsibilities Execute and maintain test cases for Radiant’s device programming flows, including bitstream generation and device configuration. Validate programmer-related features such as cable detection, device recognition, and programming success/failure handling. Develop and maintain automation scripts to streamline testing of programming tools and command-line utilities. Assist in debugging issues related to device programming, hardware-software interaction, and tool integration. Work with hardware platforms to validate programming across different devices and configurations. Document test results, file bug reports, and verify fixes in collaboration with development teams. Contribute to regression test suites and participate in continuous integration testing. Required Qualifications Bachelor’s degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field. 3+ years of hands-on experience in software QA, preferably in EDA, embedded systems, or hardware-related domains. Basic understanding of FPGA architecture, device programming, or embedded systems. Familiarity with scripting languages such as Python, Tcl, or Shell. Exposure to software testing principles and QA methodologies. Strong problem-solving skills and attention to detail. Good communication and collaboration skills.

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Responsibilities & Skills We are looking for a highly skilled and detail-oriented Senior QA Manager to lead the quality assurance strategy for Radiant Place and Route software. This role is pivotal in ensuring the accuracy, performance, and usability of our EDA tools, with a strong emphasis on Quality of Results (QoR) and GUI validation . You will oversee a team of QA engineers, define test strategies, and work closely with R&D to maintain the highest standards of product quality in production environments. Key Responsibilities Place & Route Testing Lead QA efforts for Radiant’s Place and Route engine, ensuring correctness, performance, and scalability. Develop test plans that validate timing, congestion, routing efficiency, and design rule compliance. Collaborate with algorithm and layout teams to identify edge cases and regression risks. Quality of Results (QoR) Define and monitor QoR metrics such as timing closure, area utilization, power, and runtime. Build automated pipelines to track QoR trends across software releases. Investigate QoR regressions and work with engineering to drive continuous improvements. GUI Testing Oversee functional and usability testing of the Radiant GUI, ensuring intuitive workflows and visual accuracy. Implement automated GUI testing frameworks and visual regression tools. Validate cross-platform compatibility and responsiveness. Leadership & Strategy Manage and mentor a team of QA engineers with domain expertise in EDA. Establish best practices for testing in production and pre-release environments. Drive a quality-first mindset across development and product teams. Collaboration & Reporting Work closely with product managers, developers, and support teams to align QA efforts with user needs. Provide detailed QA reports, dashboards, and risk assessments to stakeholders. Lead root cause analysis for production issues and implement preventive measures. Required Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 15+ years of QA experience in EDA or semiconductor software, with at least 3 years in a leadership role. Deep understanding of digital design flows, especially Place and Route. Strong grasp of QoR metrics and their impact on design closure. Experience with GUI testing tools and automation frameworks. Familiarity with scripting languages (Python, Tcl) and version control systems (Git). Excellent analytical, organizational, and communication skills. Preferred Qualifications Hands-on experience with Radiant Software or similar FPGA/ASIC design tools. Knowledge of timing analysis, floorplanning, and routing algorithms. Experience with CI/CD pipelines and production monitoring tools. ISTQB or equivalent QA certification.

You should have strong working experience in scripting languages such as Python, TCL, or Perl. Additionally, you should possess basic to intermediate working experience with L2/L3 protocols testing, including but not limited to VLAN, STP, LAG, OSPF, BGP, IPv4, IPv6, and Multicast. Your expertise should include L2 protocols like STP, VLAN, VTP, port channel, switching concepts, and Mac learning. Proficiency in Python scripting programming is essential, encompassing data types, functions, regular expressions, classes and objects, exceptional handling, file handling, libraries, and packages. Furthermore, you should have a solid understanding of L3 protocols such as TCP/IP, RIP, OSPF, ARP, BGP, OSI Layer, along with Python scripting programming in data types, functions, regular expressions, classes and objects, exceptional handling, file handling, libraries, and packages. Ideally, you should have 3 to 15 years of experience in this field. The job is based in Bangalore and offers a budget of Exp*2X/2.5X. The notice period for this full-time position is immediate/15 days/30 days. This job falls under the L2 category.,

You should have a Bachelor's or Master's Degree in Computer Science, Computer Engineering, Information Technology, or a related field with 3-6 years of experience in software development. Specifically, you should have 3-6 years of experience working with the Dassault Systmes 3DEXPERIENCE platform. Your role will require a strong proficiency in EKL scripting for 3DEXPERIENCE environments, along with demonstrated experience in customizing Know-how Apps using KML and EKL libraries. You should have a deep understanding of 3DEXPERIENCE Apps such as RFLP, System 3D Allocation, etc., and their underlying data structures. It is essential to have a good understanding of the Dassault Systmes 3DEXPERIENCE platform architecture, including components like ENOVIA, DELMIA, and SIMULIA. You should also be familiar with 3DEXPERIENCE People, Roles, Projects, and Organizations (P&O). Proficiency in at least one object-oriented programming language like C++, Java, or Python is required for integration and tooling purposes. Experience with Knowledge Web Dialog & Widget development would be a plus. Additionally, familiarity with web technologies such as HTML, CSS, JavaScript, and RESTful APIs is advantageous. Knowledge of MQL (Matrix Query Language) and TCL (Tool Command Language) would also be beneficial. Experience with 3DEXPERIENCE Data Model Customization (DMC) and EKL packaging is a plus. A basic understanding of PLM concepts, experience in bug tracking, and issue tracking using tools like Jira/Version One are necessary for this role. You should have a keen eye for detail and a passion for software and technologies that address problems. A curious and team player attitude, with a desire to grow alongside your team, is essential. An advanced level of English proficiency is required, and knowledge of French would be an added advantage for this position.,

At Cadence, we are committed to hiring and developing leaders and innovators who aspire to create an impact in the technology industry. We are currently seeking a Lead Application Engineer for our GCS team based in Bangalore or Noida. As a pivotal leader in electronic design, Cadence leverages over 30 years of computational software expertise to deliver cutting-edge software, hardware, and IP solutions that bring design concepts to life. Our customers, who are among the most innovative companies worldwide, rely on us to deliver exceptional electronic products across various dynamic market applications. Joining Cadence offers you the opportunity to work with state-of-the-art technology in an environment that fosters creativity, innovation, and impact. Our employee-friendly policies prioritize the well-being and career development of our employees, providing ample opportunities for learning and growth. Our inclusive "One Cadence - One Team" culture celebrates diversity and equity, enabling us to innovate, grow, and succeed with our customers. As a Lead Application Engineer in the GCS Organization for MSA (Multiphysics System Analysis), your role involves collaborating with Cadence customers globally to offer post-sales technical consultation for IC level Power System analysis products. You will work closely with customers to resolve complex issues, help them leverage the latest tools, and guide them in implementing software within their design methodologies. This role allows you to broaden and deepen your technical knowledge, gain exposure to industry best practices, and contribute high-impact knowledge content. Additionally, you will have the opportunity to contribute to the development of key technology solutions and provide feedback to enhance product offerings. You will work in a supportive and flexible environment, where your success is a collective effort and passion for technology and innovation drives us forward. **Job Responsibilities:** - Provide technical support for Voltus product from the Multiphysics System Analysis (MSA) toolset, focusing on productivity and customer satisfaction - Support multiple tools/methods, requiring general domain knowledge and business experience - Assist in creating impactful knowledge content in the MSA domain - Work independently at Cadence or customer facilities to deliver quality results according to schedule requirements - Work on problems of moderate scope that may require analysis of situations, data, or tool problems **Qualifications:** - Bachelors Degree in Electrical/Electronics/Electronics and Communication/VLSI Engineering with 5-7 years of related experience - OR Masters with 3-4 years of related experience - OR PhD with 1 year of related experience **Experience And Technical Skills Required:** - 3-7 years of relevant industry experience in EMIR analysis, PDN analysis with digital signoff tools, and Digital Physical implementation - Strong background in Digital logic Design, CMOS logic Design, Power IR drop analysis, Circuit Design and Analysis, Digital and Behavioral simulation fundamentals - Proficiency in debugging Low power and multiple power domain analysis for chip power integrity sign-off - Understanding of Digital design toolsets of Cadence (Genus/Innovus/Tempus/Conformal) and hardware description languages like VHDL, Verilog, System Verilog - Knowledge of TCL, Perl, or Python scripting **Behavioral Skills Required:** - Strong written, verbal, and presentation skills - Ability to establish a close working relationship with both customer peers and management - Creative problem-solving skills and ability to explore unconventional solutions - Effective collaboration across functions and geographies - Commitment to raising the bar while maintaining integrity Join us at Cadence, where we are dedicated to tackling meaningful challenges and pushing the boundaries of what is possible in technology. Let's solve problems that others can't.,

You will be joining Quest Global, an organization known for its innovation and rapid growth in engineering services. With expertise in various industries and a commitment to excellence, we are on a journey to become a centenary company. We are seeking individuals who are both humble and brilliant, believing that engineering can turn the impossible into possible. As part of our diverse team of engineers, you will play a crucial role in designing a brighter future through your work. We are looking for innovators who are driven by technology and constantly strive to design, develop, and test solutions for our Fortune 500 clients. Collaboration and continuous learning are at the core of our values, as we believe in collective success and growth. The ideal candidate for this role should possess the following characteristics and skills: - Proficiency in physical design at a block level with a thorough understanding of the PnR cycle - Strong grasp of physical design fundamentals - Hands-on experience with industry-standard PnR tools such as ICC2/Innovus - Familiarity with signoff tools like Prime Time, Redhawk, and Calibre - Ability to mentor junior engineers in resolving technical issues - Proficiency in tools such as ICC/Innovus, Prime Time, StarRC, Redhawk, Calibre DRC/LVS - Experience with scripting languages like TCL and Perl If you are an achiever who thrives on challenges and is passionate about driving innovation, we invite you to be a part of our team. Your contributions will be valued, and your growth will be supported as we work together towards success.,

You should have 3+ years of experience in RTL, UPF & Physical aware Synthesis for cutting-edge technology nodes, logic equivalence checking, Scripting, and Netlist Timing Signoff. Proficiency in Python/Tcl is required. You should be familiar with Synthesis tools such as Fusion Compiler/Genus and have fair knowledge in LEC, LP signoff tools. Proficiency in VLSI front-end design steps including Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking is essential. Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus. You should be sincere, dedicated, and willing to take up new challenges. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Qualcomm is an equal opportunity employer that provides reasonable accommodations for individuals with disabilities during the application/hiring process. If you require accommodations, you may contact Qualcomm at disability-accommodations@qualcomm.com. Qualcomm expects its employees to adhere to all applicable policies and procedures, including security and confidentiality requirements regarding Company confidential information and other proprietary data. Please note that Qualcomm's Careers Site is for individuals seeking jobs at Qualcomm. Staffing and recruiting agencies are not authorized to use this site for submissions. Qualcomm does not accept unsolicited resumes or applications from agencies. For more information about this role, kindly contact Qualcomm Careers. 3074295,

🔧 Job Title: Physical Verification Engineer 🏢 Industry: Semiconductor 📍 Location: Noida 🧠 Experience: 5+ Years 📅 Employment Type: Full-time 📢 Urgent Requirement We must fill this position immediately. Apply only if you are available to join immediately or have a notice period of 30 days or less. Please do not apply if your notice period exceeds 30 days. Key Responsibilities: Own and execute Physical Verification flow across block, sub-system, and full-chip levels. Perform and debug checks such as DRC, LVS, ERC, DFM, Antenna, PERC , and ESD using Calibre or IC Validator (ICV) . Analyze and debug rule deck issues and implement solutions in collaboration with layout and integration teams. Execute PV closure and contribute to SoC-level sign-off activities . Apply runtime optimization techniques and support quality tapeouts. Script and automate PV flows using Perl, Python, Tcl, SVRF , and Unix/Linux shell. Required Qualifications: 5+ years of hands-on experience in Physical Verification in advanced process nodes (7nm, 5nm preferred). Strong expertise in DRC, LVS, ERC, Antenna, PERC, ESD verification checks. Proven debugging and fixing experience in Innovus and/or Fusion Compiler environments. Deep knowledge of multi-patterning layers (double/triple patterning) and base/metal layer DRC resolution. Experience in LVS/Antenna debugging and fixes . Strong scripting capabilities in Tcl, Perl, Python , and Unix/Linux shell . Familiarity with full-chip integration and sign-off flows is a plus. 📢 Urgent Requirement We must fill this position immediately. Apply only if you are available to join immediately or have a notice period of 30 days or less. Please do not apply if your notice period exceeds 30 days. 📩 DM me or share your resume at razia.begum@talentcorner.in 📱 WhatsApp (No Calls): +91 87904 31010

Location: IN - Hyderabad Telangana Goodyear Talent Acquisition Representative: Kerr Bianca Beech Sponsorship Available: No Relocation Assistance Available: No The Software Developer / Engineering Technologist will be a motivated individual to develop and deliver integrated FEA (Finite Element Analysis) software solutions to the customer in support of business needs. You will work in SDLC environment with a cross-functional, cross-continental group of engineers who are creating and refining links between tire design and vehicle performance. Typical activity will include developing new solutions to support Virtual tire development, adding new software functionality to existing tools, identifying, and fixing software issues, delivering service requests, providing incident coverage, and deploying software releases. The candidate will be part of a global software development team that implements IT solutions to support the tire design and manufacturing processes for three different technical centers globally. Primary Responsibilities Develop software applications to support key business functions for R&D. Coordinate, plan, and execute software deployments to production, test, and development platforms using documented procedures and tests. Troubleshoot and investigate. Develop solutions to problems involving causes that are not obvious. Respond to problems by diagnosing and correcting errors that do not have a known cause. Perform tasks necessary to ensure data integrity and system stability. Write and maintain all documentation supporting the primary area of responsibility. Apply knowledge of current technologies and methodologies with business subject matter to develop technical solutions. Confer with stakeholders to gain an understanding of the situation requiring intervention. Translate process into practice through the current Information Technology toolsets. Obtain advice from higher-level Information Technology associates when precedents are unclear. Participate actively in the software release process. Required Education And Experience Bachelors’ degree in Computer Science, Information Technology or Mechanical Engineering. In lieu of a degree, 8 years of relative experience. 3 or more years of experience in Information Technology Basic knowledge of the current Office Product Suite. Understanding of Business Process Area supported - Continued growth in understanding company culture and business practices professional programming experience in Python, modern C++, TCL/TK, preferably in Linux environment desired Desired Skills And Abilities Experience in CAD, FEA, and simulation is a plus Experience with CI, code reviews, and Git Experience using LINUX/UNIX Demonstrated experience in the development and deployment of software applications using Python, modern C++, TCL/TK and Linux scripting. Experience with client-server application development, Java, and Rich Client Platform (RCP) in Eclipse is a plus Knowledge of one or both of the following technologies like VTK, and Qt would be nice to have. Knowledge of High-Performance Computing is an asset Excellent debugging and troubleshooting skills. Goodyear is an Equal Employment Opportunity and Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to that individual's race, color, religion or creed, national origin or ancestry, sex (including pregnancy), sexual orientation, gender identity, age, physical or mental disability, ethnicity, citizenship, or any other characteristic protected by law. Goodyear is one of the world’s largest tire companies. It employs about 74,000 people and manufactures its products in 57 facilities in 23 countries around the world. Its two Innovation Centers in Akron, Ohio and Colmar-Berg, Luxembourg strive to develop state-of-the-art products and services that set the technology and performance standard for the industry. For more information about Goodyear and its products, go to www.goodyear.com/corporate

About the role: As a Senior DevOps Engineer focused on Vulnerability Remediation within Infrastructure Engineering and Cloud Operations (IECO), you will contribute to the development of our solution delivery platforms supporting our web-based applications on the latest cloud technologies within a DevSecOps culture. You will have the opportunity to utilize automation technologies and private/public cloud technologies to provide world-class solutions that serve the non-profit industry and ensure the security of the environment. What you'll do: Build automation leveraging CI/CD processes, automated testing, unit testing, code coverage and other software development best practices Contribute to reusable automation scripts, libraries, services, and tools to increase system and process efficiencies Partnering with the security teams and tools to continually review and understand new industry security threats, associated technologies and quickly addressing vulnerabilities Partnering with the application management teams to continually review and understand the impact of resolving open vulnerabilities and execute those resolutions. Pursue opportunities to further operational excellence by increasing efficiency and reducing risk, complexity, waste and cost Partner with key stakeholders to establish technical direction and negotiate technical decision points to drive innovative solutions Drive technical design and validation, while ensuring implementation aligns with our technical strategies and strategic business goals Develop architectural designs for applications building something to delight clients while managing costs to deliver these applications What you’ll bring: 5+ years of experience with common web technologies required – C#, .NET, Java or other equivalent Object-Oriented language 5+ years of experience in the implementation of cloud technologies (Microsoft Azure) and an understanding of SAAS, PAAS, and IAAS models Experience building high performance, scalable, robust, 24x7 environments and/or applications Experience creating scripts or automation, such as Perl, PowerShell, Python, TCL/TK, Ruby or similar for cloud orchestration required (PowerShell preferred) Available on a 24x7x365 basis when needed for production impacting incidents or key customer events. Ability to create quality code that is secure and operable at scale. Stay up to date on everything Blackbaud, Blackbaud is a digital-first company which embraces a flexible remote or hybrid work culture. Blackbaud supports hiring and career development for all roles from the location you are in today! Blackbaud is proud to be an equal opportunity employer and is committed to maintaining an inclusive work environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, physical or mental disability, age, or veteran status or any other basis protected by federal, state, or local law.

Job Posting Description About the role: As a Principal DevOps Engineer focused on Vulnerability Remediation within Infrastructure Engineering and Cloud Operations (IECO), you will contribute to the development of our solution delivery platforms supporting our web-based applications on the latest cloud technologies within a DevSecOps culture. You will have the opportunity to utilize automation technologies and private/public cloud technologies to provide world-class solutions that serve the non-profit industry and ensure the security of the environment. What you'll do: Build automation leveraging CI/CD processes, automated testing, unit testing, code coverage and other software development best practices Contribute to reusable automation scripts, libraries, services, and tools to increase system and process efficiencies Partnering with the security teams and tools to continually review and understand new industry security threats, associated technologies and quickly addressing vulnerabilities Partnering with the application management teams to continually review and understand the impact of resolving open vulnerabilities and execute those resolutions. Pursue opportunities to further operational excellence by increasing efficiency and reducing risk, complexity, waste and cost Partner with key stakeholders to establish technical direction and negotiate technical decision points to drive innovative solutions Drive technical design and validation, while ensuring implementation aligns with our technical strategies and strategic business goals Develop architectural designs for applications building something to delight clients while managing costs to deliver these applications What you’ll bring: 10+ years of experience with common web technologies required – C#, .NET, Java or other equivalent Object-Oriented language 10+ years of experience in the implementation of cloud technologies (Microsoft Azure) and an understanding of SAAS, PAAS, and IAAS models Experience building high performance, scalable, robust, 24x7 environments and/or applications Experience creating scripts or automation, such as Perl, PowerShell, Python, TCL/TK, Ruby or similar for cloud orchestration required (PowerShell preferred) Available on a 24x7x365 basis when needed for production impacting incidents or key customer events. Ability to create quality code that is secure and operable at scale. Stay up to date on everything Blackbaud, Blackbaud is a digital-first company which embraces a flexible remote or hybrid work culture. Blackbaud supports hiring and career development for all roles from the location you are in today! Blackbaud is proud to be an equal opportunity employer and is committed to maintaining an inclusive work environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, physical or mental disability, age, or veteran status or any other basis protected by federal, state, or local law.

About the role As a Staff DevOps Engineer focused on Site Reliability within Infrastructure Engineering and Cloud Operations (IECO), you will contribute to the development of our solution delivery platforms supporting our web-based applications on the latest cloud technologies within a DevSecOps culture. You will have the opportunity to utilize automation technologies and private/public cloud technologies to provide world-class solutions that serve the non-profit industry. What you'll do Build automation leveraging CI/CD processes, automated testing, unit testing, code coverage and other software development best practices Contribute to reusable automation scripts, libraries, services, and tools to increase system and process efficiencies Partnering with the security teams and tools to continually review and understand new industry security threats, associated technologies and quickly addressing vulnerabilities Pursue opportunities to further operational excellence by increasing efficiency and reducing risk, complexity, waste and cost Partner with key stakeholders to establish technical direction and negotiate technical decision points to drive innovative solutions Drive technical design and validation, while ensuring implementation aligns with our technical strategies and strategic business goals Develop architectural designs for applications building something to delight clients while managing costs to deliver these applications What you’ll bring 2+ years of experience with common web technologies required – Javascript, C#, .NET, HTML, AJAX or other equivalent Object-Oriented language 2+ years of experience in the implementation of cloud technologies (Microsoft Azure) and an understanding of SAAS, PAAS, and IAAS models Experience building high performance, scalable, robust, 24x7 environments and/or applications Experience creating scripts or automation, such as Perl, PowerShell, Python, TCL/TK, Ruby or similar for cloud orchestration required (PowerShell preferred) Available on a 24x7x365 basis when needed for production impacting incidents or key customer events Ability to develop quality code that is secure and operable at scale Stay up to date on everything Blackbaud, Blackbaud is a digital-first company which embraces a flexible remote or hybrid work culture. Blackbaud supports hiring and career development for all roles from the location you are in today! Blackbaud is proud to be an equal opportunity employer and is committed to maintaining an inclusive work environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, physical or mental disability, age, or veteran status or any other basis protected by federal, state, or local law.

Senior Software Engineer (Python/C++) 1 Location: Gachibowli Hyderabad, TG, IN Company: Goodyear Location: IN - Hyderabad Telangana Goodyear Talent Acquisition Representative: Kerr Bianca Beech Sponsorship Available: No Relocation Assistance Available: No The Software Developer / Engineering Technologist will be a motivated individual to develop and deliver integrated FEA (Finite Element Analysis) software solutions to the customer in support of business needs. You will work in SDLC environment with a cross-functional, cross-continental group of engineers who are creating and refining links between tire design and vehicle performance. Typical activity will include developing new solutions to support Virtual tire development, adding new software functionality to existing tools, identifying, and fixing software issues, delivering service requests, providing incident coverage, and deploying software releases. The candidate will be part of a global software development team that implements IT solutions to support the tire design and manufacturing processes for three different technical centers globally. Primary Responsibilities Develop software applications to support key business functions for R&D. Coordinate, plan, and execute software deployments to production, test, and development platforms using documented procedures and tests. Troubleshoot and investigate. Develop solutions to problems involving causes that are not obvious. Respond to problems by diagnosing and correcting errors that do not have a known cause. Perform tasks necessary to ensure data integrity and system stability. Write and maintain all documentation supporting the primary area of responsibility. Apply knowledge of current technologies and methodologies with business subject matter to develop technical solutions. Confer with stakeholders to gain an understanding of the situation requiring intervention. Translate process into practice through the current Information Technology toolsets. Obtain advice from higher-level Information Technology associates when precedents are unclear. Participate actively in the software release process. Required Education and Experience Bachelors’ degree in Computer Science, Information Technology or Mechanical Engineering. In lieu of a degree, 8 years of relative experience. 3 or more years of experience in Information Technology Basic knowledge of the current Office Product Suite. Understanding of Business Process Area supported - Continued growth in understanding company culture and business practices professional programming experience in Python, modern C++, TCL/TK, preferably in Linux environment desired Desired Skills and Abilities Experience in CAD, FEA, and simulation is a plus Experience with CI, code reviews, and Git Experience using LINUX/UNIX Demonstrated experience in the development and deployment of software applications using Python, modern C++, TCL/TK and Linux scripting. Experience with client-server application development, Java, and Rich Client Platform (RCP) in Eclipse is a plus Knowledge of one or both of the following technologies like VTK, and Qt would be nice to have. Knowledge of High-Performance Computing is an asset Excellent debugging and troubleshooting skills. #LI-RB2 Goodyear is an Equal Employment Opportunity and Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to that individual's race, color, religion or creed, national origin or ancestry, sex (including pregnancy), sexual orientation, gender identity, age, physical or mental disability, ethnicity, citizenship, or any other characteristic protected by law. Goodyear is one of the world’s largest tire companies. It employs about 74,000 people and manufactures its products in 57 facilities in 23 countries around the world. Its two Innovation Centers in Akron, Ohio and Colmar-Berg, Luxembourg strive to develop state-of-the-art products and services that set the technology and performance standard for the industry. For more information about Goodyear and its products, go to www.goodyear.com/corporate Job Segment: Test Engineer, Testing, Software Engineer, Linux, Recruiting, Engineering, Technology, Human Resources

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and detail-oriented engineer with a drive to deliver high-quality, innovative hardware solutions. You thrive in collaborative, cross-functional environments and are energized by working on world-class microprocessor IP that powers some of the most advanced embedded systems on the planet. With a strong foundation in electronics engineering or computer science, you bring at least five years of hands-on experience in ASIC physical design, particularly in physical verification and IR analysis. Your expertise enables you to navigate complex design flows, and you are keen to expand your knowledge by engaging with the latest industry tools and methodologies. You are comfortable scripting in Unix, Perl, and TCL, and you have a working knowledge of hardware description languages like Verilog or VHDL. You possess excellent written and verbal communication skills, allowing you to work effectively with international teams and assist in customer engagements. Your methodical and analytical mindset helps you troubleshoot and optimize designs for performance, power, and area. Eager to learn, you look forward to being involved in both in-house test chip projects and customer-facing design-ins, gaining exposure to a wide range of applications for Synopsys’ ARC processor IP. You are committed to continuous personal and professional growth, and you value the opportunity to contribute to a team that is shaping the future of microprocessor technology. What You’ll Be Doing: Developing and optimizing physical design implementation flows for ARC family microprocessor IPs, ensuring best-in-class performance and power efficiency. Performing comprehensive physical verification, including LVS, DRC, and IR drop analysis, to ensure first-pass silicon success. Collaborating with cross-functional teams, including logic design, verification, and library development, to drive seamless integration and qualification of IP. Supporting benchmarking, test chip implementation, and qualification activities for new microprocessor IP families. Assisting with customer support, design-ins, and technical sales engagements, providing insights into implementation best practices. Automating and enhancing existing design flows using scripting languages such as Perl and TCL to improve efficiency and reproducibility. Participating in internal knowledge-sharing initiatives and contributing to the continuous improvement of team processes and methodologies. The Impact You Will Have: Enable Synopsys customers to achieve rapid, successful integration of advanced ARC processor IP into their SoC designs. Drive the delivery of highly optimized, silicon-proven IP, reducing time-to-market for embedded and high-performance applications. Enhance the robustness and scalability of Synopsys’ implementation flows, setting industry benchmarks for physical design quality. Support the development and qualification of next-generation microprocessor IP, fueling innovation in diverse application domains. Strengthen customer relationships by providing expert technical guidance and support during pre- and post-sales engagements. Contribute to the continuous improvement of Synopsys’ engineering excellence, maintaining our leadership in silicon design. What You’ll Need: Bachelor’s degree in electronics engineering or computer science (Master’s preferred). Minimum 5 years of hands-on experience in ASIC physical design, with a focus on physical verification and IR analysis. Proficiency in scripting languages such as Unix shell, Perl, and TCL to automate design tasks. Exposure to hardware description languages such as Verilog or VHDL. Strong analytical and troubleshooting skills, with attention to detail in solving complex design challenges. Who You Are: A collaborative team player who communicates effectively with colleagues across the globe. Methodical and analytical, with a passion for continuous learning and improvement. Adaptable and open to new ideas, technologies, and design methodologies. Self-motivated and proactive in identifying and resolving technical issues. Customer-focused, with the ability to translate technical concepts into actionable solutions. The Team You’ll Be A Part Of: You’ll join a diverse, international team of experts dedicated to developing and delivering industry-leading microprocessor IP for the ARC family. The team works at the intersection of hardware design, implementation, and customer enablement, supporting a full suite of Synopsys memory compilers and standard cell libraries. You will collaborate closely with colleagues across logic design, verification, and applications engineering, learning from and contributing to a vibrant culture of innovation, knowledge sharing, and technical excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Job Title: Field Application Engineer (VLSI) Experience : 2 – 3 Years Education: B.E (E &C) /M.Tech in VLSI and Embedded design/Digital Communication/ DSP/ Micro Electronic. Roles and Responsibilities: 1. Working on EDA tools and presenting latest technology to customer 2. Working with Sales team on technical requirement of customers 3. Provide technical support for the customer of company about the product selling. 4. After the designers are done with their job, the next step is to give support for the product sold by the marketing and sales department. 5. Travelling is part of the job 40 % to 50% you'll have to do a bit of travelling. 6. Responsibilities like preparing "technical proposal" documents. 7. Should have Strong Knowledge in any Scripting and Linux commands 8. Good to have knowledge on Job scheduling products and complete FPGA design flow 9. Should be good in communication skills 10. Should help Technical Support Team for resolving issues related to software integration 11. Complete assigned modules/support issues in timely manner 12. Knowledge of Safety standards like DO-254 is a PLUS Desired skills : Knowledge of HDL(Verilog/ VHDL) language. Good understanding of digital large Fare knowledge of Analog circuit. Good knowledge of CMOS. Knowledge on FPGA. OS Knowledge : Linux, Windows Script Knowledge: TCL/TK, Perl, Python Job Types: Full-time, Permanent Pay: ₹30,000.00 - ₹40,000.00 per month Benefits: Cell phone reimbursement Health insurance Provident Fund Education: Bachelor's (Preferred) Experience: Application development: 1 year (Preferred) total work: 1 year (Preferred) Java: 1 year (Preferred) Work Location: In person

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description: Job Description Ø Define and develop verification environments Ø Write verification plans, and documentation Ø Generate test bench and automatic regression plans Ø Be responsible for verification architecture, simulations, verifications, and debugging of circuit and logic designs Ø Complete block-level verification and chip level verification Ø Bring a self-motivated and enthusiastic approach that will achieve any new Ø requirements and overcome all challenges Ø Able to work mostly independently and handle complex SoC Verification platform. Able to debug the RTL for design intent and Interface with cross-functional teams and collaboration in all verification related activities Requirements/Qualifications: Qualifications/Requirements Ø Minimum of 8 years related proven silicon design or verification work experience Ø Hands on project experience with leading edge verification methodologies like OVM/UVM Ø One of the Protocol knowledges AXI/AHB/DDR/PCIe is must Ø Hands on project experience in coverage/assertion driven verification Ø Knowledge of IC chip design, development flow, process, and methodology Ø Knowledge of CMOS logic design, circuit design, and circuit analysis Ø Proficient in HDL languages System Verilog, Verilog and VHDL Ø Good knowledge of UNIX shell scripting, Perl and TCL scripting. Ø Good knowledge and understanding of CMOS device operation and characteristics Ø Proven experience in writing verification plans and test bench development, simulation, and debugging Ø Proficient with UNIX environment, and CAE/CAD tools such as schematic capture, simulation, design verification Ø Must be able to learn new technology Ø Good analytical and problem-solving skills Ø Excellent written and verbal communication in English. Ø Experience dealing with and communicating at different levels of the organization Travel Time: 0% - 25% To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

Company: Eteros Technologies India Private Limited Eteros Technologies, Inc. is a Semiconductor Engineering services startup, head quartered in the heart of the Silicon Valley, San Jose, CA, USA. Eteros Technologies India Pvt Ltd is a wholly owned subsidiary offices in Bangalore, Noida, Hyderabad and Ahmedabad • Our world-wide customers are amongst The Who's who in the semiconductor industry. Eteros works not only with some of the top 20 semiconductor startups in the world but boasts of customers who are among the most respected publicly traded semiconductor companies. • Eteros engineers work on cutting edge technology nodes while working on the state-of-the art designs in the AI/ML, Datacenter, Automotive and 5G domains. Eteros engineers work with some of the brightest, innovative and successful engineers and leaders around the world. A one-of-a-kind opportunity where young Eteros engineers showcase their ability and experience world-wide from day 1 while learning from some of the world's most well-respected companies. • We are not your traditional design services company offering staff augmentation. Eteros engineers are treated as an integral part of the customer team and routinely are responsible for turnkey, end-to-end ownership and delivery, whether it is Implementation, Digital and Mixed Signal Verification, DFT or Analog Design and Layout. Eteros and our engineers work closely with our customers to define and set methodologies and design flows. • Eteros invests in our engineers. Our engineers are continuously learning, on and off the job. They are able to grow the breadth and depth of knowledge. We believe in preparing our employees for the fast-track in career development as well as longevity ----------------------------------------------------------------------------- Job Title/Role: Synthesis and Static Timing Analysis - Staff Design Engineer/Design Manager Location : Bangalore/Hyderabad/Ahmedabad/Noida Experience Level : 6+ Years Industry : Semiconductors Employment Type : Full-time Job Functions : Engineering ----------------------------------------------------------------------------- Summary Join a development team and lead the synthesis, static timing and DFT efforts for an advanced mixed signal chip for a high-profile Silicon Valley startup. In this highly visible role, as part of a highly talented team you will be at the heart of the Soc design effort interfacing with all disciplines with critical impact in getting functional products to of customers quickly. As a Sr, ASIC STA Engineer, you will be a part of the SOC digital design team responsible for providing integrated solutions into a growth industry Key Qualifications The position requires thorough knowledge of the ASIC design timing closure flow and methodology. • BTech/MTech/PhD with at least 6+ years hands-on experience in ASIC timing constraints generation and timing closure. • Expertise in STA tools (Tempus and Primetime) and methodologies for timing closure with a good understanding of OCV, noise and crosstalk effects on timing. • Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced finFET technology nodes, preferably 7nm. • Knowledge of timing corners/modes and process variations. • Knowledge of low-power techniques including clock gating, power gating and millivoltage designs. Proficient in scripting languages (Tcl and Perl). • ECO timing flow • Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups (e.g. digital design, verification, DFT, physical design, etc.). • Familiarity with RTL, synthesis, logic equivalence, DFT, floor-planning, and backend related methodology and tools. • Must be able to solve complex problems and independently drive tasks to completion in a timely manner. • Be able to work under limited supervision and take complete accountability. Responsibilities Include • Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation). • Develop and maintain methodology and flows related to timing verification and closure. • Generation of block and full chip timing constraints. • Analyze timing reports and utilize scripting techniques to develop insights and drive rapid Eteros Technologies, Inc. Confidential Sep 2020 timing closure. • Support digital chip integration work and flows What's in it for you • Work on leading edge technologies • An opportunity for career development and growth • Competitive compensation • Medical Benefits and more

Job Description Location: NOIDA Exp-7-15Y We are seeking a highly skilled & experienced Synthesis & Static Timing Analysis (STA) expert to join our Flows & Methodologies Team. This role requires strong analytical skills, attention to detail, and the ability to work collaboratively with cross-functional teams. Proficiency in relevant EDA tools and a solid understanding of digital design principles are essential for success in these positions Scope of Responsibilities: As part of the Design Enablement team of the organization, you need to work closely with SoC cross functional teams to develop and define Synthesis & STA flow & methodology to meet SoC & IP level objectives on low geometry nodes (3/5/16nm) Your scope of work will cover tools and flows definition, requirement management for SoC designs You will work with EDA Vendors to proactively review latest tools and flows offerings in Synthesis & STA domains. Evaluate latest offerings and benchmark with organization used tools, flows, and methodologies. You will be an actor of change for deploying new tools & methodologies across the organization Qualifications Bachelor or Master or Ph.D. in Electronics Engineering and specialization in VLSI domain Good understanding of RTL, Synthesis, LEC, VCLP, Timing Constraints, UPF, Timing Closure & Signoff Experience with EDA tools like Genus, Fusion Compiler, Primetime, Tempus, Conformal Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Can – do attitude, openness to new environment, people and culture Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus Ability to work independently and as part of a team Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement . Job title Staff Engineer, Physical Design Department Engineering Location Noida Remote No Requisition ID 20019218_2025-03-01

Job description: Physical design Lead 7+ Years Bangalore/ Pune/ Hyderabad/ Kochi Must Have Skills Floor Planning/Innovus/Fusion Compiler Good to have Experience on programming in Tcl/Tk/Perl. Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Mandatory Skills: VLSI Physical Place and Route . Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: General Summary: Join Qualcomm’s cutting-edge hardware engineering team to drive the design verification of next-generation SoCs, with a focus on wireless technologies including WLAN (IEEE 802.11). You will work on IP and subsystem-level verification, collaborating with cross-functional teams to deliver high-performance, low-power silicon solutions. A strong understanding of on-chip buses and bridges is essential to ensure seamless integration and performance across subsystems. Key Responsibilities: Develop and execute verification plans for complex SoC designs and IP blocks. Architect and implement testbenches using SystemVerilog and UVM/OVM methodologies. Perform RTL verification, simulation, and debugging. Collaborate with design, architecture, and software teams to ensure functional correctness. Contribute to IP design reviews and sign-off processes. Support post-silicon validation and bring-up activities. Analyze and verify interconnects, buses (e.g., AMBA AXI/AHB/APB), and bridges for performance and protocol compliance. Conduct CPU subsystem verification including coherency, cache behavior, and interrupt handling. Perform power-aware verification using UPF/CPF and validate low-power design intent. Execute performance verification to ensure bandwidth, latency, and throughput targets are met. Preferred Skills & Experience: 2–15 years of experience in digital design and verification. Deep understanding of bus protocols and bridge logic, including hands-on experience with AXI, AHB, and APB. Experience with CPU subsystem verification and performance modeling. Familiarity with wireless protocols (IEEE 802.11 a/b/g/n/ac/ax/be) is a plus. Proficiency in SystemVerilog, UVM/OVM, Verilog, and scripting languages (Perl, Tcl, Python). Experience with power-aware verification methodologies and tools (e.g., UPF, CPF). Familiarity with performance verification techniques and metrics. Exposure to tools like Clearcase/Perforce and simulation/debug environments. Strong analytical, debugging, and communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications: Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Science, or related field. Relevant experience in hardware design and verification. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Job Description Qualcomm Chennai is looking for a STA and Synthesis Engineer who is passionate in to work with cross-functional engineering teams. In this position, the engineer will be involved in all stages of the design and development cycles Synthesis, Static Timing Analysis and LEC of SoC/Cores Full chip and block level timing closure, IO budgeting for blocks Logical equivalence check between RTL to Netlist and Netlist to Netlist Knowledge of low-power techniques including clock gating, power gating and MV designs ECO timing flow Proficient in scripting languages (TCL and Perl). Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. 4+ yrs of experience Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.