1079 Timing Closure Jobs

As an Implementation Engineer in Arm's Solutions Engineering group we like to think we are not just crafting sophisticated CPUs, GPUs and SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC, CPU and GPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies. Responsibilities Work w...

We're hiring an ASIC Design Engineer who can take full ownership of complex SoC and subsystem RTL from concept to silicon. You'll define micro-architecture, craft clean Verilog RTL, drive synthesis, timing closure, and work hand-in-hand with integration and backend teams to land a production-ready design. Expect deep involvement across reviews, debug cycles, emulation, and bring-up. You should bring 815 years of solid ASIC RTL experience, strong micro-architecture thinking, and hands-on skills across synthesis, timing, and SoC integration. Expertise with high-speed protocols (PCIe, DDR/LPDDR, USB, Ethernet, SPI/I3C/I2C, etc.), RTL assertions/coverage, and cross-team collaboration is key. Com...

As an ASIC Physical Design Lead, you will be responsible for leading the design of IP/SoC in advanced process technologies for global Semiconductor product MNC clients. Key Responsibilities: - Lead the physical design of complex ASIC projects from Netlist to GDSII. - Perform timing closure tasks including synthesis, place and route, and static timing analysis. - Oversee full-chip physical design processes, including floor planning, power grid design, clock tree synthesis, and signal integrity analysis. - Collaborate with the packaging team to ensure seamless integration of the chip design with the package, including pads log management, bump placement, and RDL routing. - Mentor junior engine...

As an ASIC Physical Design Engineer, your primary role will be to oversee the physical implementation of ASIC designs while working closely with design and verification teams to ensure optimal performance. Your daily tasks will involve logic synthesis, floor planning, clock tree synthesis, physical verification, and timing closure. Additionally, you will be responsible for supporting RTL-to-GDSII flow development and optimization to meet PPA (Performance, Power, Area) goals. Key Responsibilities: - Execute the complete Physical Design Flow (RTL to GDSII) for high-speed, complex digital blocks or full-chip integration. - Perform Floorplanning and Power Grid (PDN) Synthesis to optimize for pow...

As an experienced Physical Design Engineer in Hyderabad and Guntur, your role will involve: - Executing block level Place and Route (P&R) and Timing closure activities. - Owning up block level P&R and performing Netlist2GDS on blocks. - Implementing multimillion gate SoC designs in cutting-edge process technologies such as 28nm, 16nm, 14nm, and below. - Demonstrating strong hands-on expertise in various aspects of physical design, including Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning, Clock Tree Synthesis, analog IP integration, Parasitic Extraction, Timing Closure, Power/IR Drop (Static and Dynamic), Signal Integrity Analys...

Roles and Responsibility Develop and implement effective staffing strategies to meet business needs. Manage and oversee the entire recruitment process, from job posting to onboarding. Build and maintain relationships with clients and vendors to ensure successful placements. Lead and motivate a team of recruiters and staff to achieve high performance levels. Analyze market trends and competitor activity to stay ahead in the industry. Ensure compliance with all relevant laws and regulations related to employment. Job Requirements Proven experience in staffing and recruitment, with a minimum of 8 years of experience. Strong knowledge of recruitment principles, practices, and technologies. Excel...

Responsibilities: Block level or Top Level implementation experts from Netlist to GDSII. * Optimize physical design using STA, PNR, ICC, Primetime & TCL. * Manage floor planning, timing closure & LVS compliance. Provident fund Health insurance Food allowance Annual bonus

Role : Execellent Customer Interfacing and Pre-Sale skills. Proposal Writting, presentation and tuning as per requirement. Must have excellent skills/ Hands On experience in areas including RTL logic design, design verification, team work, customer focus, and communication Will have demonstrated experience as a senior technical contributor, planning and leading RTL logic design development projects Should have good hands on Knowledge on Test Bench creation , configuration and UVM methodologies . Will have demonstrated experience in developing verification environments and performing complete verification on design blocks, sub-systems and full SoCs Must possess proven experience with customer...

As a member of the physical design team at AMD, you will play a crucial role in delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power, and other design requirements for AMD's next-generation processors. Your work will be in a fast-paced environment on cutting-edge technology, collaborating with experienced professionals to shape the future of AI and beyond. Your attitude, analytical skills, and commitment to excellence will be key to driving innovation and solving the world's most important challenges. **Key Responsibilities:** - Implement RTL to GDS2 flow - Manage Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Rout...

Job Overview As a part of Arm's Solutions Engineering group we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is the development of comprehensive implementation and analysis methodologies. Responsibilities Synthesis, Physical implementation, Timi...

General Summary: Responsibilities will include To be strong designer who is able to work independent on one of the peripheral IPs come up with design and microarchitecture solutions guide/mentor juniors engage with external teams to drive/resolve cross team dependencies. Take complete responsibility of one or more project and drive that independently. Being able to make schedule estimates is a plus. People management experience is a plus Skills & Requirements needed 8 to 10 years of work experience in ASIC IP cores design Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering Knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture ...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engine...

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements Minimum Qualifications: Bachelor's degree in Computer Sci...

You will be joining Marvell, a company known for providing semiconductor solutions that are crucial for the data infrastructure connecting various industries. At Marvell, you will have the opportunity to contribute to innovative technology and shape the future possibilities in enterprise, cloud, AI, automotive, and carrier architectures. **Role Overview:** In this unique role as a senior leader in the central physical design team, you will be responsible for shaping the long-term vision for physical design capabilities and infrastructure. Your key responsibilities will include leading RTL-to-GDSII implementation, providing strategic leadership to physical design teams, mentoring engineering ...

Collaborate with leading customers to develop and implement advanced AI-driven RTL-to-GDS methodologies using Synopsys EDA tools, IPs, and libraries. Create and optimize design flows and solutions to meet aggressive PPA targets for high-frequency cores, automotive, and high-capacity AI/compute designs. Enable and deploy flows/solutions leveraging Synopsys offerings such as Fusion Compiler, RTL Architect, and AI-based Design Space Optimization engines. Utilize Tcl/Python scripting for automation and lead a team of junior application engineers, providing technical guidance, coaching, and project management support. Deliver technical presentations, application notes, and best practices to both ...

We are looking for a skilled Staff R&D Engineer with 5 to 10 years of experience to join our team in Bengaluru, responsible for developing and enhancing PPA methodologies for complex interface IPs at advanced technology nodes. The ideal candidate will have expertise in synthesis, timing closure, power optimization, constraints management, LEC, and STA flows. Roles and Responsibility Develop and enhance PPA methodologies for complex interface IPs at advanced technology nodes. Implement high-performance CPUs, GPUs, and interface IPs using industry-leading Synopsys tools such as RTLA, Fusion Compiler, DSO, and Fusion AI. Drive flow development and optimization to improve design quality and pred...

Role Overview: You will be responsible for the complex SOC Top Physical Implementation of next generation SOCs, including mobile application processors, modem sub-systems, and connectivity chips. Your role will involve tasks such as Synthesis, Place and Route, STA, timing and physical signoffs. Additionally, you will work on physical design and timing closure of complex blocks and full-chip designs. Key Responsibilities: - Perform top level floor planning, including partition shaping and sizing, pin placement, channel planning, high-speed signal and clock planning, and feed-through planning. - Understand timing, power, and area trade-offs for optimization of PPA. - Utilize industry standard ...

As a Principal Engineer specializing in Hardware and VLSI, your role will involve acting as a technical authority and strategic advisor in the design, development, and industrialization of hardware systems and VLSI solutions. Your deep expertise in semiconductor design, hardware architecture, and system integration will be crucial in ensuring that products meet performance, reliability, and manufacturability standards. Collaborating with cross-functional teams including design, verification, manufacturing, and supply chain will be essential to drive end-to-end product realization. Key Responsibilities: - Define and review hardware system architecture for complex electronic products. - Ensure...

As an experienced SoC design engineer at Qualcomm India Private Limited, your role will involve working on complex System-on-Chip (SoC) designs with a focus on AMBA protocols such as AXI, AHB, APB, as well as SoC clocking, reset, debug architecture, and peripherals like USB, PCIE, and SDCC. Your understanding of memory controller designs and microprocessors will be highly beneficial, along with hands-on experience in constraint development and timing closure. You will collaborate closely with SoC verification and validation teams for pre/post Silicon debug, requiring expertise in Low power SoC design, multi-clock designs, and asynchronous interfaces. Additionally, your proficiency in Synthes...

Hello Folks, we at LTTS are looking for Physical design Lead role with 8+ years of experience. Deatiled JD is below as mentioned... Candidates with PnR 8+ experience IP/Block level PnR activities from Netlist to GDS-II. Good knowledge of all PnR activities like Floor-planning, Placement, CTS, Routing, Timing closure(STA), signoff checks like FEV, VCLP, EMIR and PV. Knowledge of industry stanrd E tools (Synops, Cadence, Mentor) Worked on DSM technologies, tsmc 5nm and below experience preferred. Knowledge of scripting skills. Minimum Experience : 8+

L&T Technology is looking to hire for Physical Design Engineers Experience : 5-8 Years JD is mentioned below :: Good knowledge of timing closure knowledge for high frequency timing, congestion, and area sensitive designs. Can work closely with FE team for constraints development and constraints cleanup. Work with partitions/block owner to give timing ECO for timing closure. Knowledge of advanced timing closure techniques and methodology Knowledge of industry stanrd tools from Synops or Cadence. Worked on DSM technologies, tsmc 5nm and below experience preferred. Minimum 5+ of relevant experience Good scripting and communication skills

Role : Application Specific Integrated Circuit Design Engineer Industry : Semiconductor Required Technical Skill Set : RTL design skills using verilog, SV, Exposure to complex designs and protocols like PCIe, CXL, ARM subsystem, SATA, DDRx etc. Should have good experience in synthesis and timing closure and low power design flow, partition and upf creation. Should have good experience in unit level testing and DFT concepts Good to have : Low power design and FPGA design and floor plan Desired Experience Range : 12-20 years Location of Requirement : PAN India

Location: Bengaluru, India Type: Full-Time Industry: Semiconductors / VLSI / ASIC Design Job Summary We are seeking an experienced Physical Design Technical Manager to join our chip development team. In this leadership role, you will drive the implementation and optimization of complex ASIC designs from RTL to GDSII . You will collaborate closely with RTL, Verification, and DFT teams to ensure successful tape-outs of high-performance, low-power silicon designs, while mentoring team members, driving execution, and contributing to methodology and flow improvements. Key Responsibilities Technical Manager Responsibilities (Added Pointers) Own project planning, resource allocation, and delivery f...

You have the opportunity to work as an Analog / Mixed Signal Layout Designer with 2-8 years of hands-on experience in advanced FinFET processes such as 16nm, 12nm, 10nm, 7nm, 5nm, 3nm. Your responsibilities will include: - Expertise in complete PNR flow including CTS, routing, and Timing Closure. - Hands-on experience in critical blocks like SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier, etc. - Understanding of CMOS / Bi-CMOS / SOI / FinFET process and AMS IP integration according to Full Chip needs. - Problem-solving skills in Routing Congestion, Physical Verification in Custom Layout, and verification checks...

Role Overview: As an FPGA Architect, you will play a pivotal role in leading the design and development efforts across various projects in a dynamic and collaborative work environment. Your primary responsibility will involve defining and developing intricate FPGA designs for Test products. Working closely with cross-functional teams including R&D Project Manager, Product Architects, Solution Teams, FPGA developers, and Software Engineers, you will contribute to the enhancement of existing products and the creation of new product offerings. Collaboration with design teams based in the US and Europe will be a key aspect of this role. Key Responsibilities: - Lead the design and development of ...