461 Pnr Jobs

International voice experience to handle reservations, ticketing, queries & refunds. Minimum 2 years’ experience in airline reservation/ticketing ,Amadeus knowledge is mandatory. Interested can share you resumes to Aparna 9172726408

Call or WhatsApp ASAP MONICA 9650531029 Clients Hiring for :- BRITISH AIRWAYS International Airline (Captive Unit) hiring Minimum 1year Travel Voice process Experience Role & responsibilities Inbound Voice, Airline Internal Service Process Handling Airline Customer Queries PNR & Ticket & Itinerary Cancelation, Creation, Amendment Preferred candidate profile Excellent Communication* 1 Year Voice or Blended Travel Voice process Experience Mandate Any Education Any Age Any Location within Delhi NCR Immediate Joiner preferred (Notice period can be given) Perks and benefits Monthly salary 30-40% hike on your last withdrawn salary or as per below mentioned one whichever is lesser will be given Experienced = 44000 (INCLUDED VARIABLE) Work From Office Both Way Cab Any 5 Days Working Rotational Shifts & Offs Call or WhatsApp ASAP MONICA 9650531029

International voice experience to handle reservations, ticketing, queries & refunds. Minimum 2 years’ experience in airline reservation/ticketing ,Amadeus knowledge is mandatory. Interested can share you resumes to LAVANYA(9361645614)

Dear Candidate We have immediate job openings for Analog layout and design openings Exp : 3-10 years Location : Bangalore NP : less than 45 days Job details : Analog layout exp Skills Required: Analog Layout design and IO design Good to Have: Exposure to Analog layout, EDA tools Thanks Gayathri

Dear Candidate We have immediate job openings for Analog layout and design openings Exp : 3-10 years Location : Bangalore NP : less than 45 days Job details : Analog layout exp Skills Required: Analog Layout design and IO design Good to Have: Exposure to Analog layout, EDA tools Thanks Gayathri

Job Specs : Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements for the design. Set up and configure STA tools ( PrimeTime, StarRC, Tempus, Innovus and QRC ) for the analysis, including library characterization, delay models, and clock definitions Perform static timing analysis to evaluate setup and hold times, clock-to-q delays, and other timing metrics. Ensure that the design meets timing requirements for various corners and operating conditions (e.g., process, voltage, temperature variations). Identify and analyze asynchronous signals crossing between different clock domains to ensure proper synchronization and to avoid metastability issues. Define and analyze multicycle paths and false paths to accurately capture the designs timing constraints. Collaborate with RTL and physical design teams to achieve timing closure by optimizing the design or constraints. Perform incremental and formal ECO (Engineering Change Order) analysis to address timing issues. Work with CTS engineers to ensure that the clock tree meets timing requirements and minimizes clock skew and jitter. Perform post-layout STA to account for parasitic capacitance and resistance effects introduced during the physical design phase. Identify and resolve timing violations and sign-off on the final timing closure. Analyze timing margins to account for variability and manufacturing process variations, ensuring robust operation. Prepare detailed timing analysis reports, including timing paths, violations, and suggestions for timing optimization. Collaborate closely with RTL designers, physical designers, DFT (Design for Test) engineers, and verification teams to resolve timing-related issues. Contribute to the development and improvement of STA methodologies and flows to enhance efficiency and accuracy.Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Vietnam are the preferred work locations Preferred resources with valid regional work permit.

He/She should be able to do block level / top-level floor planning, PG Planning, partitioning (for hierarchical designs) , placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks and be able to fix the violations . S hould have worked on 4 5nm , 28nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design eng inee rs. Interface with front-end ASIC teams to resolve issues. Excellent communication skills. Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools. Expertise in scripting languages such as PERL, TCL. Strong Physical Verification skill set. Static Timing Analysis in Primetime or Primetime-SI. Good written and oral communication skills. Ability to clearly document plans. Ability to interface with different teams and prioritize work based on project needs.

Excellent Communication Proficiency in collaboration and delegation of duties Hands on - Google sheet, forms & drives Flexible with work timings & Male candidate is preferred Follow ups on tasks and activity.

Key Responsibilities Expertise in PDK enablement and library validation/automation. Hands-on experience with LVS/Parasitic extraction/standard cell characterization flows and methodologies Design/System level experience with DTCO and PPA analysis Hands-on expertise in TCL, Python, make and shell scripting Broad understanding of system design (product architecture, packaging, SRAM, DRAM, etc.) is a plus Strong understanding of the RTL2GDS concepts and methodology and experience with Synopsys/Cadence physical design tools (Fusion Compiler/Innovus) Knowledge of standard cell architecture and design tradeoffs with respect to PPA Proactively identify and act on new trends or developments in future technology nodes Ability to implement solutions and troubleshoot complex problems with limited or no supervision in area of expertise Creative thinking and ability to look ahead and anticipating future technology innovations/issues Ability to collaborate with internal stakeholders, customers and vendors Collaborate/participate in discussions to solve interdisciplinary technical issues in a cross-functional team environment Mandatory - PDK, DRC, LVS, Python, Physical Design Functional Knowledge Demonstrates depth and/or breadth of expertise in own specialized discipline or field Business Expertise Interprets internal/external business challenges and recommends best practices to improve products, processes or services Leadership May lead functional teams or projects with moderate resource requirements, risk, and/or complexity Problem Solving Leads others to solve complex problems; uses sophisticated analytical thought to exercise judgment and identify innovative solutions Impact Impacts the achievement of customer, operational, project or service objectives; work is guided by functional policies interpersonal Skills Communicates difficult concepts and negotiates with others to adopt a different point of view Additional Information Time Type: Full time Employee Type: Assignee / Regular Travel: Yes, 10% of the Time Relocation Eligible: Yes

For sub system in high performance microprocessor design, you are responsible for Timing constraintmodelling given timing specification, generation, validation. Design timing data generation, validation, timing data analysis. Driving timing convergence across different timing corners , by working with logic, circuit, integration designers. Ensuring quality and efficiency in timing convergence. Engaging in automation of flow, data analysis. Required education Bachelor's Degree Required technical and professional expertise 5+ years of industry experience Hands on experience in static timing analysis, modelling timing constraints, setting up timing environment and timing runs, data analysis, timing fix implementation, timing ECO generation. Knowledgeable in physical design flow, logic. Experience with timing fixes (slack, electrical, noise). Preferred technical and professional experience Require programming skills with any language PYTHON, PERL , and/or TCL .

Physical Deisgn Lead Location: Bangalore / Hyderabad / Pune Experience - 8+ YoE In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl. Must have hands-on experience on Synopsys/Cadence tools. (Innovus, ICC2, Primetime, PT-PX, Calibre). Well versed with timing constraints, STA and timing closure. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl Well versed with timing constraints, STA and timing closure. Mandatory Skills: VLSI Physical Place and Route. Experience: 5-8 Years.

Company Name: Kesari Tour Position: Air Ticketing Executive Qualification: IATA, Diploma in Travel and Tourism Experience: 1-4 years Location: Mumbai Responsibilities: Issue domestic and international bookings through Amadeus/Sabre Issue FIT and GIT Booking Processing re-issuance / cancellation / refund of air tickets. Maintain daily tour closing. Candidates who has handled group ticketing would preferred. Eligibility: 2 - 5 years of experience in Domestic/ international air ticketing. Graduate preferably in travel studies and/or Diploma/equivalent in travel and tourism. IATA / UFTAA or any other authorized airline course. Interested candidate can share there resume on akshatas@kesari.in or 8657549866

Assist in managing end-to-end recruitment, onboarding, and induction processes. Support employee engagement activities and performance appraisal cycles. Maintain and update employee records, HRIS systems, and payroll inputs.

Role Description: This is a full-time on-site role for a Senior Lead Physical Design Engineer based in Hyderabad. The Senior Physical Design Engineer will be responsible for tasks related to physical design, physical verification, logic design, circuit design, and RTL design in the development of silicon products. Qualifications: He/She should be able to do block level PNR including PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Minimum of 7-15 years of experience in physical design. He/She should have worked on 7nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design engineers. Lead a team of Physical design engineers and be responsible for their blocks closure Interface with front-end ASIC teams to resolve issues. Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques. Expertise in Timing closure on high speed interfaces is a plus Excellent communication skills. Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. Extensive experience and detailed knowledge in Cadence or Synopsys. Expertise in scripting languages such as PERL, TCL. Strong Physical Verification skill set. Static Timing Analysis in Primetime or Primetime-SI. Good written and oral communication skills. Ability to clearly document plans. Ability to interface with different teams and prioritize work based on project needs.

As a Hardware Engineer at Qualcomm India Private Limited, you will play a vital role in planning, designing, optimizing, verifying, and testing electronic systems that contribute to the launch of cutting-edge, world-class products. Your responsibilities will encompass working on a variety of systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, FPGA, and/or DSP systems. You will collaborate with cross-functional teams to develop solutions that meet performance requirements. **Key Responsibilities:** - Complete ownership of PNR implementation including Floorplanning, Placement, Clock Tree Synthesis (CTS), post_route, etc. on latest nodes. - Mandatory signoff knowledge required in areas such as STA, Power analysis, low power verification, formal verification, etc. - Ability to quickly grasp new concepts with strong analytical and problem-solving skills. **Qualifications:** - Minimum of 20 years of Hardware Engineering experience or related work experience. - At least 17 years of experience with PNR flow in the latest tech nodes (e.g., 4nm/5nm/7nm). If you are an individual with a disability and require accommodations during the application/hiring process, Qualcomm is dedicated to providing accessible support. You may contact disability-accommodations@qualcomm.com or call Qualcomm's toll-free number for assistance. Qualcomm values diversity and is an equal opportunity employer. Note: Qualcomm expects all employees to adhere to applicable policies and procedures, including security measures for protecting company confidential information. Qualcomm's Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies are not authorized to use this site for submissions. For more information about this role, please reach out to Qualcomm Careers directly.,

Required skills: Job Description: Experience into STA and timing closure/signoff experience with PD domain skill-set/knowledge. Candidate should be able to understand the timing constraints, analyze design details, analyze timing reports from prepcts to postcts stages, in-depth concepts of 14nm technode STA analysis, DCD knowledge. Candidate is preferably expert in PT and Tempus tools. Education Requirements B. Tech / M. Tech (ECE) Shift General Work Week Monday to Friday Joining time Immediate to 90 Days

Perform Sub system level floor planning, placement, and routing for high-performance microprocessor design. Collaborate with cross-functional teams to achieve design goals. Close the design to meet timing, power, and area requirements. Implement engineering change orders (ECOs) to rectify functional bugs and timing issues. Ensure the quality and efficiency of the RTL to GDS2 implementation process. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8+ years of industry experience Good knowledge and hands on experience in physical design , timing and methodology which include logic synthesis, placement, clock tree synthesis, routing , post route closure. Should be knowledgeable in physical verification ( LVS,DRC. etc) ,Noise analysis, Power analysis and electro migration . Good knowledge and hands on experience in static timing analysis (closing timing at chip level) good understanding of timing constraints . Should have experience in handling asynchronous timing, multiple corner timing closure.

About The Role : To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, and layout verification. Perform LVS (Layout vs. Schematic) and DRC (Design Rule Check) debugging for advanced FinFET technology nodes (5nm, 7nm, 10nm, 14nm and below). Ensure layout quality by applying principles of matching, electromigration (EM), electrostatic discharge (ESD), latch-up prevention, shielding, parasitic management, and short channel effects. Utilize industry-standard EDA tools such as Cadence Virtuoso Editor and Calibre RVE for layout and verification tasks. Primary Skills : Analog Layout Design(Block/IP level) LVS/DRC Debugging FinFET Technology Node Experience(5nm, 7nm, 10nm, 14nm and below) EDA Tools Cadence Virtuoso Editor Calibre RVE Layout Optimization Area estimation Floorplanning Routing Secondary Skills : These support the primary responsibilities and enhance performance: Understanding of Physical Design Concepts: Matching Electromigration (EM) Electrostatic Discharge (ESD) Latch-Up Shielding Parasitics Short Channel Effects Critical Thinking & Problem Solving Interpersonal and Communication Skills Team Collaboration Educational Qualification: Bachelor"s or Master"s Degree.

Are you looking for a unique opportunity to be a part of something great Want to join a 17,000-member team that works on the technology that powers the world around us Looking for an atmosphere of trust, empowerment, respect, diversity, and communication How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization We offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our we affectionately refer to it as the and it's won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo we did not achieve record revenue and over without a great team dedicated to empowering innovation. People like you. Visit our page to see what exciting opportunities and company await! Job Description: As a member of Microchip's FPGA design engineering team, you will be responsible for the definition, design and integration of interfaces between the global buses and the different blocks in the FPGA such as fabric, I/Os, NOCs, memories, etc. Collaborate with cross-functional teams to establish requirements and specifications for interface logic between global buses and FPGA components such as fabric, I/Os, Network-on-Chip (NoC), and memory blocks. Develop efficient, high-performance digital designs for these interfaces, ensuring compatibility and seamless communication between the FPGA's internal components. Translate design and timing requirements provided by the architects into Verilog code ,and implement and test the RTL code. Partner with architects and lead designers to identify and implement improvements to enhance the efficiency, speed, and reliability of the interfaces. Provide support for post-silicon integration, bring-up, and validation. Effectively present technical information to small engineering teams. Maintain regular communication with the architecture, design and verification team across multiple locations to resolve issues, update status and address technical challenges. Stay updated with the latest industry trends and technologies to continuously improve design processes. Requirements/Qualifications: Bachelor's or Master's in Electrical Engineering or Computer Science, with 12+ years of experience including several product cycles of successful ASIC and SoC development. Expertise in areas such as AMBA bus protocols, CPU and memory architecture. Familiarity with chip bus controllers and flash controllers, PCI-e, DDRx is a plus. Proficiency in Verilog, System Verilog, and testbench generation and simulation. Hands-on experience in synthesis and PnR. Proven skills in scripting, managing simulation queues, and data capture with ability to present findings using Microsoft Office tools, including Excel. Capability to support layout, verification, timing characterization, and software model developers. Strong analytical, oral and written communication skills Able to create clean, readable presentations. Self-motivated and proactive team player. Ability to meet schedule requirements effectively.

Job Area :Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3 to 5 years hands-on experience of different PnR steps including Floorplanning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation and DRC closure Well versed with high frequency design & advanced tech node implementations In depth understanding of PG-Grid optimization, including identification of high vs low current density paths & layer/via optimization, Adaptive PDN experience In depth knowledge of custom clock tree including H-tree, SPINE, Multi-point CTS, Clock metrics optimization through tuning of CTS implementation. Well versed with tackling high placement density/congestion bottlenecks In depth knowledge of PnR tool knobs/recipes for PPA optimization Experience in automation using Perl/Python and tcl Good communication skills and ability & desire to work in a cross-site cross-functional team environment.

Job Area :Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Responsibilities: STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Work on automation scripts within STA/PD tools for methodology development. Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment Experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus Familiar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo. Education : B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI. Preferred Qualification/Skills 5 - 10 years of experience in STA/Timing Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling Hands-on experience with STA tools - Prime-time, Tempus Have experience in driving timing convergence at Chip-level and Hard-Macro level In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling, Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus) Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation. Proficient is scripting languages TCL, Perl, Awk Basic knowledge of device physic

Job Area :Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 7-14 yrs experience in Physical Design and timing signoff for high speed cores. Should have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology. Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design. Experience in leading block level or chip level Physical Design, STA and PDN activities. Work independently in the areas of RTL to GDSII implementation. Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.) Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.) Tcl/Perl scripting Willing to handle technical deliveries with a small team of engineers. Strong problem-solving skills.

Job Area :Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Masters degree in Electrical/Electronic Engineering from reputed institution 8+ years of experience in Physical Design/Implementation Minimum Requirements: Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills.

Job Area :Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum of 5+ years experience in the area of ASIC/DFT -In depth knowledge of DFT concepts -In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors -Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TK, TetraMax) -Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem solving skills -Excellent communication and team work skills and good English is required

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 4+ years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, And should be familliar to PNR tools like Innovus/FC Solid grip on STA fixing aspects to solve extreme critical timing and clock path analysis Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs and manual ECOs as well. Experience in deep submicron process technology nodes is strongly preferred - Below 10nm Knowledge of high performance and low power interface timing is added benefit. Strong fundamentals on basic VLSI design concepts, synchronous design timing checks, understanding of constraints Good experience with in Unix, TCL, PT-TCL, Tempus-TCL scripting Familiarity with Python background is added bonus