696 Vlsi Jobs

The role at Recrivio is strictly on-site and seeks a Senior / Lead Technical Recruiting Staff for their team in Bangalore. Recrivio is known for redefining recruitment by providing agile, scalable, and people-first hiring solutions for leading semiconductor, product, and technology companies. The ideal candidate will have a passion for solving hiring challenges, excel in a high-energy environment, and possess a proven ability to build strong talent pipelines in deep-tech domains. Responsibilities include driving end-to-end technical recruitment in semiconductor, embedded, and product engineering roles, collaborating with hiring managers to understand talent needs, leading sourcing efforts using advanced tools and techniques, managing candidate engagement and negotiations, mentoring junior recruiters, and contributing to strategic hiring programs. The perfect candidate will have at least 5 years of technical recruiting experience, particularly in semiconductor, embedded, VLSI, or product tech fields. Strong sourcing skills and stakeholder management abilities are essential, along with the capacity to thrive in a fast-paced, high-growth environment. Prior experience in leading or mentoring a team is advantageous. Joining Recrivio offers the opportunity to work with cutting-edge clients in various tech fields, be part of a founder-led HRTech firm, experience a growth-focused environment with leadership opportunities, receive competitive compensation and performance-based rewards, and be part of a people-first culture that values collaboration, innovation, and impact.,

Job Description: Role and Responsibilities: Develops and prepares stdcells layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by design engineering. Work may be completed through use of CAD or other computerized equipment. Checks dimensions, writes specifications, and verifies completed drawings, artwork or digitized plots. Check design layouts and detailed drawings. 3-5 years of experience. Qualification/Requirements: Must have 3-5 of experience in standard cell layout, analog, mixed-signal and custom digital block designs in advanced CMOS process. Should have expertise in multiple standard cell layout library developments. Should be able to perform standard cell layout development and physical verification activities for complex designs as per provided specifications. Should have expertise in layout area and routing optimization, design rules, yield and reliability issues. Good understanding of layout fundamentals i.e., Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc. Should have adequate knowledge of schematics, interface with circuit designer and CAD team. Understanding layout effects on the circuit such as speed, capacitance, power, and area etc., Excellent in problem-solving skills in solving area, power, performance, and physical verification of custom layout. Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Caliber- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques. Should have leadership qualities and able to do multi-tasking as required. Should be able to work in a team environment and able to guide and provide technical support to the fellow team members. Self-motivated, hardworking, goal-oriented and excellent verbal and written communication skills. Knowledge of Skill coding and layout automation is a plus. mandatory skillset: stdcells layout || cadence virtuoso || physical verifications checks

Good working experience in Python, C/C++, Shell/Bash and other scripting languages Experience in developing CI/CD using Jenkins, Git or other SCM tools Work experience in Selenium Web automation, django, dashboards, database management and related web development platforms Working experience in integrating Jira and Confluence Automation of ASIC Development Flows & Pre-Silicon Platforms development for productivity improvement & quick delivery to FW, ASIC Validation & ASIC Verification/DFT Customers. Knowledge in Devops and work experience interacting with IT team for developing, integrating and deploying test automation infrastructure Experience in Jenkins job parallelization, manage virtual machines and efficiently utilize test nodes and optimize build resources Experience in working/integrating microcontroller / microprocessor / FPGA boards, Hardware tools, oscilloscopes, UART/SPI/I2C devices, USB bridges Ideal candidate possess a strong foundation in digital design, FPGA hardware, and software development, with experience in automation tools and infrastructure management Candidate with knowledge in Firmware/Embedded/VLSI development environment or experience in building automation framework for similar background will be given more preference. Knowledge in Protocol Analyzers and Measurement equipment is added plus Develop and maintain Build and Test Automation framework for Pre-Silicon and Post-Silicon development environment as part of ASIC Development Engineering Work with ASIC Flows in Pre-Silicon Phase & Integrate Automation & AI Capabilities for improving Productivity. Integrate tools and monitors Provide support for DevOps methodology and tools, such as Jenkins, Git, bit-bucket, etc. Work with development team to build CI/CD pipelines, enable self-service build tools and reusable deployment jobs Qualifications BS in Electrical Engineering or Computer Engineering with 12-15 years of experience in Test Automation Framework Development 12-15 years of experience in Test Automation Framework Development, Continuous Integration/Continuous Delivery Process preferably in VLSI/Firmware/Embedded environments Experience working on VLSI/Firmware/Embedded environments 7-10 Years working experience on Python, C/C++, Shell/Bash and other scripting languages. Knowledge on ASIC Flows/Pre-Silicon Platforms Development Flows Knowledge on ASIC Tools, Pre-Silicon Platform Tools is added plus

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI HVL Verification. Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI HVL Verification. Experience3-5 Years.

About The Role Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client ? Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project ? Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt ? ? Mandatory Skills: VLSI Board Design. Experience3-5 Years. Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

We are seeking a highly qualified and technically accomplished Principal Engineer / Engineering Manager with a consistent record in leading ASIC front-end methodologies across IP and SoC design and verification domains. The ideal candidate will bring VLSI experience, having successfully handled and scaled engineering teams, deployed sophisticated automation flows, and collaborated multi-functionally to deliver innovative solutions in the semiconductor domain. The role includes working with global design teams, vendors, and internal collaborators to develop, implement, and maintain IP/SoC design integration and verification methodologies. Responsibilities: Lead the development and deployment of sophisticated front-end methodologies for ASIC design, including Verification, SoC Integration, LEC, and Implementation processes. Drive and deliver customer-centric automation and tool development initiatives in collaboration with IT and software teams. Lead all aspects of migration strategies for major EDA tool transitions (e.g., CDC 0in to SpyGlass, RealIntent RDC to VC RDC). Collaborate closely with worldwide vendor R&D and AE teams to evaluate and deploy AI and automation solutions for ASIC workflows. Orchestrate RTL quality improvement initiatives including CDC SVA-based verification, Lint optimization, and formal verification improvements. Own vendor management responsibilities, including SOWs, important metric tracking, license management, tool evaluation, and documentation. Represent the company in technical conferences, working groups, and internal award forums. Required Skills and Experience : 15+ years of experience in VLSI ASIC design, verification, and methodology development. Confirmed leadership in setting up and handling high-performance teams and engineering charters. Expertise in EDA tools such as SpyGlass, VC RDC, LEC, Design Compiler, VCFSM, and formal verification tools. Proficiency in scripting and automation using Python, Perl, TCL. Strong understanding of Verilog/SystemVerilog and front-end design verification techniques (CDC, Lint, FV). Experience with tool migrations and performance benchmarking. Solid background in multi-functional collaboration with software, IT, and program management teams. Exceptional communication, collaborator management, and technical program leadership. "Nice to Have" Skills and Experience : Experience with AI flow optimization and automation in EDA environments. Familiarity with automotive and compute SoC programs and compliance processes. Awards or accolades demonstrating innovation, execution excellence, and peer recognition.

Staff R&D Engineer - Static Timing Methodology Development for Gate Level Timing Sign off We are seeking highly motivated individuals with a BS, MS, or PhD degree in Computer Science, Computer Engineering & Electronics & Communication Engineering ready to handle the challenging problems in future technologies and designs. We are also looking for candidates with Machine Learning/AI and/or Data Science background to lead our leading-edge algorithms and AI technology within our EDA solutions to increase our design teams productivity and chip quality and performance. Our dynamic global team is looking to enlist enthusiastic professionals to join world-class hardware design teams responsible for developing the most challenging and complex systems in the world. We are seeking energetic, highly motivated individuals willing to go the extra mile with the aim of helping the overall IBM development team. Strong interpersonal skills are needed to coordinate deliverables and requirements from several areas within and outside of the organization.There are many opportunities to gain and utilize a deep understanding of future issues and provide input towards decisions affecting system development, logical and physical design as well as sophisticated methodology directions. Individuals who are chosen to become a part of our world class development teams will be helping advance IBMs leadership in developing the highest performing computers and changing hardware solutions. Do you want to be an IBMerCome THINK with us! Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Individual contributor for Gate Leve Sign off Timing team to work on ASICs or Server Timing Methodology. 4+ years of Semiconductor/VLSI experience Proven problem-solving skills and the ability to work in a team environment are a must EDA Tool/Methodology development experience Thorough understanding of Static Timing Analysis. Knowledge of other VLSI domains is a plus Excellent scripting skills - TCL/Python/Shell Preferred technical and professional experience Cadence tools, Synopsys tools, VLSI knowledge, VHDL/Verilog, computer architecture, Machine Learning/AI

Understand the design specification , TB architecture Learn in IBM Fusion and Trek verification languages and tools, apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8+ years of work experience in IP, Sub-system & SOC level - Exp in creating multiple UVM/SV based env from scratch, Strong in Block Level verification Exp in developing checkers, Scoreboards, Monitors, Test plan development, Code coverage, Functional coverage, FSM based design, System Verilog Assertions. Protocols SPI (Serial Peripheral Interface), AXI, AHB, APB, ETHERNET, I2C, JTAG, UART Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Preferred technical and professional experience Worked on Power Management blocks , Low Power, Boot & Reset sequences Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

As Logic Lead, you will be responsible for design and development of Compression, Security, and sustainability features for high performance Processors chips. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature Guide and mentor junior engineers. Represent as Design Lead in various forums. Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in silicon bring-up and validation of the hardware Estimate the overall effort to develop the feature and close design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 10 to 15 years of work experience in one or more areas: Processor Architecture/ microarchitecture/ Logic design – Deep technical understanding of dynamic power saving, power capping, droop mitigation techniques. Experience in working with research, architecture/ FW/ OS teams Experience in low power logic design Experience in working with verification, validation for design closure including test plan reviews, verification coverage Good understanding of Physical Design, and able to collaborate with physical design team for floor-planning, placement of blocks for achieving high-performance design and timing closure of high frequency designs Experience in silicon bring-up

We are seeking highly motivated, energetic, and team-oriented individual contributors who can work on synthesis, LEC, and constraints for NXPs digital IPs, working in close collaboration with the RTL team. Key Responsibilities Work closely with the architects and RTL team on synthesis, LEC, and constraints of NXP digital IPs Carry out floor planning, and physically aware synthesis on high-performance IPs Perform timing and power analysis on the design database (db), improve the recipe, and provide timing feedback to the RTL team Leads or solo owners are expected to work with minimal micro-management needs. They should be able to communicate with other project members to manage task divisions and deliveries Responsible for delivering the weekly status with desired metrics information Key Technical Skills Self-starter with 312 years of relevant experience in synthesis, LEC, and constraints at the IP level. Candidate should be able to set up the synthesis and LEC flows from scratch Strong fundamentals of synthesis and place & route (P&R) Good scripting knowledge (TCL, Perl, Python) Knowledge of Fusion Compiler, Genus/Innovus, and Primetime Mandatory Key Skills TCL,Perl,Python,micro-management,Design Engineering,RTL.

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills. Mandatory Key Skills VHDL,RTL coding,Mentor DfT tools,Cadence tools,scan insertion,JTAG,ATPG,DRC,coverage analysis,simulation debug,timing,SDF,LBIST,Mixed Signal Radar IC,proactive,collaborative,detail-oriented,independent judgment,debug,root cause analysis,Verilog*

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable todays needs and tomorrows next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world were living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Good working experience in Python, C/C++, Shell/Bash and other scripting languages Experience in developing CI/CD using Jenkins, Git or other SCM tools Work experience in Selenium Web automation, django, dashboards, database management and related web development platforms Working experience in integrating Jira and Confluence Automation of ASIC Development Flows & Pre-Silicon Platforms development for productivity improvement & quick delivery to FW, ASIC Validation & ASIC Verification/DFT Customers. Knowledge in Devops and work experience interacting with IT team for developing, integrating and deploying test automation infrastructure Experience in Jenkins job parallelization, manage virtual machines and efficiently utilize test nodes and optimize build resources Experience in working/integrating microcontroller/microprocessor/FPGA boards, Hardware tools, oscilloscopes, UART/SPI/I2C devices, USB bridges Ideal candidate possess a strong foundation in digital design, FPGA hardware, and software development, with experience in automation tools and infrastructure management Candidate with knowledge in Firmware/Embedded/VLSI development environment or experience in building automation framework for similar background will be given more preference. Knowledge in Protocol Analyzers and Measurement equipment is added plus Develop and maintain Build and Test Automation framework for Pre-Silicon and Post-Silicon development environment as part of ASIC Development Engineering Work with ASIC Flows in Pre-Silicon Phase & Integrate Automation & AI Capabilities for improving Productivity. Integrate tools and monitors Provide support for DevOps methodology and tools, such as Jenkins, Git, bit-bucket, etc. Work with development team to build CI/CD pipelines, enable self-service build tools and reusable deployment jobs Qualifications BS in Electrical Engineering or Computer Engineering with 12-15 years of experience in Test Automation Framework Development 12-15 years of experience in Test Automation Framework Development, Continuous Integration/Continuous Delivery Process preferably in VLSI/Firmware/Embedded environments Experience working on VLSI/Firmware/Embedded environments 7-10 Years working experience on Python, C/C++, Shell/Bash and other scripting languages. Knowledge on ASIC Flows/Pre-Silicon Platforms Development Flows Knowledge on ASIC Tools, Pre-Silicon Platform Tools is added plus Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [HIDDEN TEXT] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Show more Show less

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills. Mandatory Key Skills JTAG,ATPG DRC,LBIST,RTL coding,VHDL,DFT

Responsibilities & Achievements: Reduced post-silicon bug escapes through early software-driven validation in emulation environments. (Accelerated Verification) Cut SoC bring-up time by 50% by architecting a unified simulation-to-emulation testbench with reusable transactors. Spearheaded the Accelerated verification plan for a next-gen ADAS SoC including use cases like Start Up, BOOTROM, Complex data path, Negative tests Enabled 80% reuse of verification components across simulation, emulation, and prototype platforms through modular UVM design. Successfully led a AV verification team of engineers across DV, emulation *Mandatory Key Skills ADAS SoC,BOOTROM,simulation,team leadership,Synopsys ZeBu,Siemens Veloce,UVM,System Verilog,Accelerated Design Verification*,Post-Silicon Validation*,emulation*

We are looking for a highly skilled and experienced Lead Engineer to join our team and contribute to the verification of mixes Signal. The ideal candidate should have a deep understanding of the Cadence, AMS along with expertise in system-level development and debugging What You Will Do Proficient in Verilog-AMS, System Verilog, and UVM methodologies Experience with Cadence Spectre or similar AMS simulation tools Strong understanding of analog circuit design principles (op-amps, transistors, etc.) What You Need to Be Successful Proficient in Verilog-AMS, System Verilog, and UVM methodologies Bonus Points if You Have Experience with Cadence Spectre or similar AMS simulation tools Strong understanding of analog circuit design principles (op-amps, transistors, etc.) What Makes You Eligible An accomplished leader with a minimum of 8+ years of experience in software design & development and a Bachelor's Masters degree Excellent communication skills (written/verbal) & Team spirit Risk taker with passion for innovation Autonomous working to explore new technologies *Mandatory Key Skills analog circuit design,software design,software development,Cadence Spectre,mixed signal verification*,Cadence*,AMS*,Verilog*,System Verilog*

Cadence is looking for Principal Design Engineer to join our dynamic team and embark on a rewarding career journey Health and Safety Compliance: Ensure that construction projects comply with health and safety regulations, guidelines, and industry standards Risk Assessment: Identify and assess potential health and safety risks associated with the project's design, construction methods, and materials Design Coordination: Collaborate with architects, engineers, project managers, and other stakeholders to integrate health and safety principles into the project's design and planning Hazard Identification: Identify and document potential hazards related to the project, including those arising from design choices, materials, and construction methods Safety Recommendations: Make recommendations for risk reduction, such as design changes, material substitutions, or safety procedures, to minimize or eliminate identified hazards Health and Safety Documentation: Maintain comprehensive health and safety documentation and records throughout the project's design and planning phases Client Communication: Communicate health and safety information, reports, and recommendations to clients, project teams, and contractors Pre-construction Information: Provide relevant health and safety information to contractors to assist them in developing their construction phase health and safety plans Coordination Meetings: Conduct coordination meetings and collaborate with various stakeholders to ensure a holistic approach to health and safety during the project

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Board Design. Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: Mechanical Part design. Experience: 3-5 Years.

Job Description: SOC Verification engineers with 3+ years of experience Knowledge of ARM architecture, CPU fundamentals & Cache coherency Experience with C/C++, assembly, and scripting languages. Familiarity with low-power design and verification Develop CDV UVM verification environments at system level Verify CPU connectivity to IP blocks Develop SoC test plans and test cases and track metrics including code and functional covera Job Requirement: Bachelors or Masters in EE/CS or related field 3+ years of SoC in ASIC/FPGA verification experience Proficiency in SV and UVM Experience with simulation, emulation, and formal verification Strong debugging and problem-solving skills Experience (years) : 3+ Year Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

What You'll Do Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. Responsibilities Looking for a Front-end Design ASIC Engineer. Architectural work: in-depth understanding of the architecture, and identification of problems and solutions. All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for low power and area; highlighting issues and standard methodologies for power and area optimization. Document and improve standard methodologies to make product successful. Who You Are Worked in architecture and definition of high-scale, high-performance ASICs. Validated experience in implementation: specification, RTL design, lint, cdc, timing analysis, formal verification, system testing. Validated experience in flow automation (scripting, Makefiles, etc), and establishing guidelines for the team. Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion. BS/MS and 5+/3+ years respectively of hands-on experience in large-scale, high-performance ASIC BS/MS should be in EE/CS. Minimum Qualifications RTL development (Verilog, SystemVerilog, VCS, Spyglass, CDC, Formal verification) Experienced in system debug and SW/HW bringup, system validation of silicon towards FCS. Gate-level understanding of RTL and Synthesis Programming/scripting skills (C, C++, Perl) Hardware Emulation Platforms and tools (such as EVE, Veloce) Good written/verbal interpersonal skills and leadership skills. Who You'll Work With Come join us and be part of the Cisco SiliconOne team and take part in crafting Cisco's groundbreaking Enterprise and Service Provider solutions by crafting some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a rare combination of a startup culture with the benefits of working for the top tier networking company in the world!

Fundamental Knowledge of VHDL: Understanding of VHDL programming basics and digital design principles. Familiarity with Design Tools: Basic exposure to tools such as AMD Vivado and SDK, with some knowledge of Petalinux, Verilog, and Intel Quartus. Introductory Experience in Interface Design: Understanding of high-speed interface concepts, cross-clock domain interactions, and the creation of simple test benches. Synthesis and Debugging Awareness: Basic understanding of synthesis processes and an introduction to debugging tools like ILA and Signal Tap for high-speed designs. Knowledge of Embedded Systems: Familiarity with embedded processor architectures and programmable logic. Hands-On Experience in Debugging: Basic skills in on-board debugging, troubleshooting mixed-signal designs, and understanding interface protocols like SPI and I2C. Interface Protocols Understanding: Introductory knowledge of Ethernet, PCIe, and LVDS interfaces. Programming Skills: Basic command of programming languages such as C and C++. Measurement Equipment Familiarity: Introductory experience with oscilloscopes and logic analyzers. Interest in Advanced Topics: Enthusiasm for learning about radar module design and high-speed memory interfaces

What You'll Do Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. Responsibilities Looking for a Front-end Design ASIC Engineer. Architectural work: in-depth understanding of the architecture, and identification of problems and solutions. All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for low power and area; highlighting issues and standard methodologies for power and area optimization. Document and improve standard methodologies to make product successful. Who You Are Worked in architecture and definition of high-scale, high-performance ASICs. Validated experience in implementation: specification, RTL design, lint, cdc, timing analysis, formal verification, system testing. Validated experience in flow automation (scripting, Makefiles, etc), and establishing guidelines for the team. Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion. BS/MS and 8+/6+ years respectively of hands-on experience in large-scale, high-performance ASIC BS/MS should be in EE/CS. Minimum Qualifications RTL development (Verilog, SystemVerilog, VCS, Spyglass, CDC, Formal verification) Experienced in system debug and SW/HW bringup, system validation of silicon towards FCS. Gate-level understanding of RTL and Synthesis Programming/scripting skills (C, C++, Perl) Hardware Emulation Platforms and tools (such as EVE, Veloce) Good written/verbal interpersonal skills and leadership skills.

We are looking for a skilled RTL Design Engineer with 3 to 7 years of experience to join our team at Capgemini Technology Services India Limited. The ideal candidate will have a strong background in IT Services & Consulting and be proficient in RTL design. Roles and Responsibility Design and develop high-quality RTL code for various projects. Collaborate with cross-functional teams to identify and prioritize project requirements. Develop and maintain technical documentation for RTL designs. Troubleshoot and debug issues related to RTL code. Participate in code reviews and ensure adherence to coding standards. Stay updated with industry trends and emerging technologies in RTL design. Job Requirements Strong understanding of digital logic design principles and methodologies. Proficiency in programming languages such as Verilog or VHDL. Experience with RTL design tools and software. Excellent problem-solving skills and attention to detail. Ability to work effectively in a team environment. Strong communication and interpersonal skills.

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -4+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.