534 Vlsi Jobs

Job description About The Role This position is for an experienced, motivated, and passionate circuit design engineer with expertise in the area of custom circuits memories, SSARF SRAM, Register File, ROM design for GHI CCG SAI Circuits Team. In this position you will be working in a team responsible for delivering high quality designs for graphics projects. You would also be involved in key decisions finalizing the memory architecture that best meets the design requirements of the program, technical readiness involving circuit simulations and responsibility for implementation as well as convergence of the design while meeting high circuit quality. The key responsibilities include ownership of tools, flows, methodologies as well as coming up with innovative design implementations with focus on power and area reduction. The role would require deep understanding of transistor and circuit behavior, strong communication, problem solving skills, time management and multitasking skills. The team members have also an opportunity to diversify their skills into other custom circuits as well as working with the client in integration of the custom circuits. Qualifications Minimum QualificationsMinimum 4-7 years of experience in designing and delivering of SRAM's/RF's/ROM's. Understanding of semiconductor device physics; VLSI Technology and VLSI circuits (analog/digital), Familiarity with spice simulations and Verilog and other tools for design and development of memory IP's like ESPCV, Nanotime, Nova, Totem etc. Knowledge of scripting (PERL/TCL/Python) is desirable, Preferred Educational QualificationsME/Mtech/MS in Microelectronics/VLSI Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Job description Work in a VLSI wireless team. Major subject VLSI, digital circuit, analog circuit. Project done on related topics preferably using CAD tools and familiar to ASIC design flow. Qualifications Degree:ME/M.TECH VLSI design, signal processing and machine learning, communication engineeringSchools: NIT/VIT Role: Physical Design / Layout Engineer Industry Type: Electronic Components / Semiconductors Department: Engineering - Hardware & Networks Employment Type: Full Time, Permanent Role Category: Hardware Education UG: Any Graduate PG: M.Tech in Any Specialization

Job description Seize the opportunity to work with the team responsible for RTL logic design and microarchitecture of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team, CLIPS is responsible for developing soft IPs, subsystems and gaskets for client and server chipsets.Candidate will be responsible for logic design and development, responsibilities including but not limited to: Develops the logic design, register transfer level (RTL) coding, and simulation for an IP design. Participates in the definition of microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for meet the design specification requirements. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Supports SOC to integrate and validate the IP on need basis. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Qualifications : BE/ME/Btech/ Mtech in computer science eng or electronics and Communications. The candidate must possess a minimum of Bachelor Degree in Electronics Engineering, Computer Engineering, Computer Science or equivalent. The candidate should have successful track record of hardware development experience and demonstrated technical leadership skills. The candidate must have demonstrated the ability to solve highly complex technical problems with excellent communication skills. The candidate must also have demonstrated strong ethical standards. Must also be able to perform in a highly ambiguous and dynamic business environment. Skills : Relevant experience with skills in ASIC IP design flows, RTL coding and Globals (Clocking, Boot/ Reset/Fabrics, DfD, Fuse, etc) with experience in CDC, linting, spyglass, micro-architecture. Experience in subsystem design and IO protocols such as AMBA, USB, PCIe, UCIe, UFS, SATA, UART, SPI, I2C, I3C etc is a plus. Other technical requirements: 3 to 8 years of relevant pre-silicon logic design experience in ASIC domain. Experienced with various tools and methodologies including but not limited to: System Verilog, Python/Perl/ Shell scripting, Synopsys tools, RTL model build, design-for-test, design-for-verification. Experienced in EDA tools & flows such as Spyglass VCLINT, VCLP, VC-CDC, SG-DFT, Design Complier, Calibre, Fishtail, FEV, ATPG etc. Experienced in developing micro-architecture based on High Level Architecture specifications. Experienced in VLSI or Structural and Physical design flow and methodology. Experienced in Power-aware design and reviewing validation flows. Strong Chipset or CPU level understanding required on power consumption, power estimation and low power design methods.

Job description Role & responsibilities Performs functional logic verification of a block, subsystem, and SoC related to DCAI flagship AI products to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, micro architects, full chip architects, RTL developers, post silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from post silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products. Preferred candidate profile Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 5+ years of technical experience. Related technical experience should be in/with: Silicon Design and/or Validation/Verification. Design/Verification with developing, maintaining, and executing complex IPs and/or SOCs. Design/Verification exposure for Ethernet or PCIe Subsystem involving full protocol stack - Transaction layer, Data Link Layer and PHY Layer Design/verification exposure for Industry standard BUS topologies such as AMBA AXI/AHB/APB , I2C, SPI, JTAG, CoreSight Debug and Trace OVM, UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation.

Job description Candidate will be working on runset/ruledeck development across Intel technologies.Coding SVRF/ICV/PEGASUS runest, performing L0QA qualification, managing and analyzing regression.. Candidate will also require to write and execute automation and productivity enhancement scripts in Python/SKILL Qualifications Pursuing Masters degree in Electrical/Electronics/Computer ScienceCandidate must have sound knowledge of VLSI Semiconductor device and electronic circuit fundamentals Designing Implementing circuits and performing the QA for circuit performance Scripting Automation exposure is preferred skillset Candidate must have Good oral and written communication Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel's offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements. Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Job description Responsibilities may be quite diverse of a technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually for the summer or for short periods during breaks from school. Qualifications Mtech graduate with below skillsHardware : VLSI Design, Custom Layout, ESD verification Software : Python, perl Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Job description ISSP FPGA prototyping delivers Intel's core products, therefore you will have a unique opportunity to take part in major activities that affect the entire organization and the high-tech world.Our FPGA design verification team is in charge of validating infrastructure designs used to prototype cutting edge Intel client, devices and data centers chips.We are looking for great, highly motivated problem-solvers seeking to make significant contributions and impact on the projects they work on.In your role you will plan, design and execute scalable and robust verification environments, learn complex digital computers flows and simulate the behavior of the RTL design in purpose of debug and development using advanced verification methodologies. Qualifications Studying towards a B.Sc. or MSc in Computer Science / Electrical Engineering / Computers Engineeringsome experience with OOP (C++, Java...)some understanding of chip design frontend flow (design/validation/synthesis)any relevant chip design / verification experience is a big advantage

Job description Job Description Responsibilities may be quite diverse of a technical nature US experience and education requirements will vary significantly depending on the unique needs of the job Job assignments are usually for the summer or for short periods during breaks from school Qualifications Mtech graduate with VLSI skill Role: Research & Development - Other Industry Type: Electronic Components / Semiconductors Department: Research & Development Employment Type: Full Time, Permanent Role Category: Research & Development - Other Education UG: B.Tech/B.E. in Any Specialization PG: M.Tech in Any Specialization

Job description Responsibilities may be quite diverse of a technical nature US experience and education requirements will vary significantly depending on the unique needs of the job Job assignments are usually for the summer or for short periods during breaks from school. Qualifications Mtech graduate with VLSI skills.

You will be an integral part of the success of the institute by contributing to a diverse, inclusive, fair, and transparent work environment at IIIT-H. We value the uniqueness of each individual and strive to recognize and respect their differences, fostering a culture that embraces diverse ideas and expertise. Our primary focus is on attracting and retaining top talent and providing them with an environment where they can thrive and excel. Currently, we are looking to fill faculty positions in specific domains such as ECE and CSE, but we are also open to recruiting individuals from other interdisciplinary areas throughout the year. We are seeking highly motivated faculty members of any nationality at the levels of Professor, Associate Professor, and Assistant Professor who are passionate about making a difference through research and teaching. Applicants should hold a Ph.D. with a strong research track record and a commitment to teaching. The core areas of expertise we are particularly interested in include embedded systems, VLSI, digital signal processing, robotics, wireless communications networks, digital electronic circuits for ECE; and computer architecture, systems and networking, algorithms and computational geometry, programming languages and compilers, AI, robotics, software engineering, and information security for CSE. As per MHRD 7th CPC guidelines, we offer competitive remuneration and a range of benefits along with research and student support. To apply, please submit your resume, teaching and research statements, and a cover letter in Word (.doc) or PDF format. Kindly note that scanned resumes and other formats will not be processed by our system.,

Come build community, explore your passions, and do your best work at Microsoft with thousands of University interns from every corner of the world. This opportunity will allow you to bring your aspirations, talent, potential, and excitement for the journey ahead. As a Silicon Engineering Intern, you will design, develop, modify, and evaluate electronic parts, components, or integrated circuitry for digital electronic devices and other digital electronic systems. You will define design architecture and operating parameters for circuitry and microelectronic components, as well as select components and equipment based on analysis of specifications and reliability. Analyzing designs and components to establish operating parameters and performance requirements to define complete pre-silicon verification test cases will be part of your responsibilities. Additionally, you will develop test plans, direct support personnel or other engineers in the preparation and execution of design verification testing, and analyze data generated from test results to perform pre-silicon verification of operating parameters and performance requirements. At Microsoft, Interns work on real-world projects in collaboration with teams across the world while having fun along the way. You'll be empowered to build community, explore your passions, and achieve your goals. This is your chance to bring your solutions and ideas to life while working on cutting-edge technology. Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees, we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond. Responsibilities include contributing to and improving the hardware solutions developed, using performance instrumentation and presenting results to the team and architects, thinking strategically, creatively, and innovating ways to communicate and visualize user experiences, implementing or recommending technical solutions to common quality and design challenges with guidance from others, writing complete design verification test cases, test benches, or automation using standard practices, and assisting in writing tests for formal pre-silicon verification of subsystems within a single block. **Qualifications:** **Required Qualification:** - Currently pursuing a bachelor's degree in Electronics Engineering, Electrical & Electronics, or Computer Science Engineering. **Preferred Qualifications (PQs):** - Experience or classes in Microelectronics/VLSI courses, Digital Logic Design and Simulation, Object-Oriented Programming and Data Structures, Embedded Systems and Firmware. - Knowledge of verification principles, testbenches, UVM, C/C++ and scripting languages, digital timing analysis, synthesis, place-n-route, circuit design including VLSI design and solid-state devices.,

We are looking for experienced subject matter experts to create high-quality educational video lectures for our online learning platform. The candidate should have expertise in their respective domain & ability to deliver informative video content. Required Candidate profile Have industrial experience in subjects: VLSI contact shashank@visualpath.in

We are seeking skilled engineers to join our semiconductor verification and simulation team. This role focuses on functional, gate-level, DFT, and timing simulations, along with validating SoC and IP blocks. Ideal candidates will have hands-on experience with Synopsys EDA tools, and domain-level knowledge of IC packaging and analog layout design will be a strong plus. Roles & Responsibilities: Develop and execute RTL test benches using VCS/SystemVerilog/UVM Perform functional and gate-level simulation, debug with Verdi Run DFT pattern simulations, scan insertion validations Conduct Static Timing Analysis (STA) with PrimeTime Execute power-aware and multi-mode multi-corner (MMMC) simulations Validate interfaces considering IC package parasitic (SiP/2.5D/3D-IC understanding is a plus) Collaborate with teams to correlate package- and board-level effects with chip-level behavior Analyze analog layout impact on mixed-signal simulation accuracy (awareness of layout parasitic) Requirements Strong hands-on experience with Synopsys tools: VCS (RTL simulation), Verdi (debug), PrimeTime (timing), TetraMAX/TestMAX (DFT), HSPICE/FineSim (analog simulation exposure is a plus) Familiarity with IC packaging technologies, chip-package co-simulation, and signal/power integrity considerations Understanding of analog layout practices and their influence on simulation/verification Strong scripting skills (TCL, Perl, Python) for automation Excellent debugging, documentation, and communication skills Preferred Qualifications: Bacheloror Masterin Electronics, VLSI, or Electrical Engineering & 5-8 Years of Relevant Experience is mandatory Awareness of multi-die, chip let, or 3D IC architectures Basic understanding of EM/IR effects, package substrate modeling, or layout vs schematic (LVS) Strong analytical and collaborative mindset Master in VLSI / Microelectronics Benefits -Challenging job within a young and dynamic team. -Performance-driven, Career Progression Opportunities. -Attractive remuneration package: On par with Industry Standards. -Opportunity to join an organization experiencing year on year growth.

This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; - Grade Specific Focus on Electrical, Electronics and Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers.

•BE/B.Tech in ECE /M.Tech in VLSI with 6 to 9 years experience in Analog Mixed Signal Verification •Very Good experience in Verilog AMS, Verilog-A, WREAL, modeling of Analog blocks •Very Good experience in Analog Mixed Signal verification simulation tools •Good experience in System Verilog, UVM methodologies •Able to train the team members and guide them to the solutions for problems •Good experience in creating the AMS Verification environment and able to create AMS Verification environment from scratch. •Good experience in Gate level netlist simulation •Experience in Python, Perl, Shell scripting is added advantage. •Good communication and documentation skills

This position offers a great opportunity for you to pursue a Ph.D. at SRM University. The ideal candidate should hold an M.Tech degree in VLSI. For further details, please contact 9790667033.,

Alternate Job Titles: Senior R&D Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a passionate and driven engineering professional with a strong foundation in VLSI concepts, CMOS circuit design, and EDA tools With2-3 years of hands-on experience in the semiconductor industry, you thrive in dynamic environments where innovation, collaboration, and continuous learning are valued Your curiosity drives you to explore emerging technologies such as AI/ML, and you have developed proficiency in scripting languages like TCL and Python to solve complex engineering challenges You have a keen eye for detail and a solid grasp of timing, power, and noise analysis, enabling you to deliver robust and reliable design solutions Your exposure to industry-standard tools such as VCS, Design Compiler, Primetime, and HSPICE/Primesim has honed your technical expertise, and you are comfortable navigating various stages of the design flow, from synthesis to signoff As a team player, you communicate effectively, share knowledge openly, and support your peers in achieving shared goals You value diversity, equity, and inclusion, and are eager to contribute to a culture that fosters creativity and personal growth If you are ready to challenge yourself, make an impact, and be part of a world-class engineering team, Synopsys is the place for you, What Youll Be Doing: Developing and maintaining scripts and automation flows using TCL, Python, and Make to streamline EDA tool operations and design processes, Performing advanced timing, power, and noise analysis on CMOS circuits, leveraging your understanding of setup/hold constraints and leakage concepts, Contributing to the characterization of standard cell libraries, including NLDM/CCSN and LVF methodologies, and ensuring accurate modeling for signoff, Collaborating with design, verification, and methodology teams to optimize PPA (Power, Performance, Area) and address STA (Static Timing Analysis) challenges, Utilizing tools such as VCS, Design Compiler, Primetime, and HSPICE/Primesim to support verification, synthesis, and signoff activities, Participating in root cause analysis of timing and power issues, implementing innovative solutions, and documenting best practices for future projects, Staying abreast of the latest trends in AI/ML and exploring their application in EDA tool flows and design optimization, The Impact You Will Have: Accelerate the delivery and quality of Synopsys' IP and design solutions through automation and process innovation, Enhance product reliability by ensuring precise timing and power characterization, directly influencing customer satisfaction, Drive cross-functional collaboration, sharing insights and solutions that elevate team performance and project outcomes, Contribute to the adoption of cutting-edge AI/ML techniques, positioning Synopsys as a leader in intelligent EDA workflows, Reduce design cycle times and resource bottlenecks through effective scripting and workflow optimization, Mentor and support junior engineers, fostering a culture of knowledge sharing and continuous improvement, What Youll Need: 2-3 years of experience in VLSI design, EDA tool flows, or related semiconductor engineering roles, Proficiency in TCL, Python, and Make for scripting and automation, Strong understanding of CMOS circuit fundamentals, including timing (setup/hold), power (leakage/dynamic), and noise analysis, Experience with cell library characterization methodologies (NLDM/CCSN, LVF) and familiarity with library constructs and syntax, Working knowledge of STA analysis, PPA trends, and basic understanding of PNR (Place & Route), Hands-on experience with EDA tools: VCS, Design Compiler, Primetime, HSPICE/Primesim, Who You Are: Analytical thinker with strong problem-solving skills and a passion for innovation, Effective communicator, able to collaborate across disciplines and share complex ideas clearly, Self-motivated and adaptable, eager to learn new technologies and methods, Detail-oriented with a commitment to delivering high-quality results under tight deadlines, Team player who values diversity, equity, and inclusion in the workplace, The Team Youll Be A Part Of: You will join a vibrant team of R&D engineers focused on advancing the state of the art in chip characterization, timing, and power analysis Our team collaborates closely with cross-functional partners in design, verification, and methodology to deliver next-generation semiconductor solutions We foster a culture of innovation, mentorship, and continuous improvement, ensuring every member has an opportunity to grow and make a meaningful impact, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process, Show

Job Summary: Seeking an experienced FPGA developer to join our team and work on the design and development of complex FPGA-based systems. The ideal candidate will have a strong background in FPGA design, verification, and implementation, as well as experience working with hardware and software engineers to integrate FPGA designs into larger systems.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. About The Role As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Additional About The Role Additional About The Role Job Role * Work with multiple SOC Design teams to rollout robust Logic Synthesis, UPF synthesis, QoR optimization and netlist Signoff flows* Provide implementation flows support and issue debugging services to SOC design teams across various site* Develop and maintain 3rd party tool integration and product enhancement routines * Should lead implementation flow development effort independently by working closely with design team and EDA vendors * Should drive new tool evaluation, methodology refinement for PPA optimization Skill Set * Proficiency in Python/Tcl * Familiar with Synthesis tools (Fusion Compiler/Genus), * Fair knowledge in LEC, LP signoff tools* Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking* Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus* Should be sincere, dedicated and willing to take up new challenges Experience 13+ years of experience in RTL,UPF & Physical aware Synthesis for cutting edge technology nodes, logic equivalence checking, Scripting and Netlist Timing Signoff Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience 3+ years of experience in RTL,UPF & Physical aware Synthesis for cutting edge technology nodes, logic equivalence checking, Scripting and Netlist Timing Signoff Proficiency in Python/Tcl * Familiar with Synthesis tools (Fusion Compiler/Genus), * Fair knowledge in LEC, LP signoff tools * Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking * Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus * Should be sincere, dedicated and willing to take up new challenges Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Where IP Design Technical Lead/ Staff ASIC RTL Design Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12276 Remote Eligible No Date Posted 24/07/2025 Job Title: IP Design Technical Lead/ Staff ASIC RTL Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and forward-thinking digital design expert with a strong foundation in ASIC RTL design and a proven track record of delivering complex, high-performance IP cores. With a Bachelor s or Master s degree in EE, EC, or VLSI and over four years of relevant industry experience, you thrive in dynamic, multi-site environments and excel at translating functional specifications into robust, scalable architectures. You re adept at working with advanced protocols such as Ethernet, DDR, PCIe, and USB, and have hands-on experience in data path and control path design, including Reed Solomon FEC, BCH codes, and MAC SEC engines. Your expertise extends to synthesizable Verilog/SystemVerilog coding, timing closure, CDC analysis, and P&R-aware synthesis, complemented by a keen understanding of design trade-offs in area, latency, and throughput. You are comfortable leveraging version control systems like Perforce and scripting languages such as Perl or Shell to automate and streamline workflows. As a natural leader, you are ready to mentor and technically guide a team of designers, fostering a collaborative and inclusive culture. Communication comes easily to you, and you re known for your proactive problem-solving skills, attention to detail, and unwavering commitment to design quality. You re seeking an opportunity to take ownership of challenging projects, contribute to cutting-edge innovation, and grow alongside a team of world-class engineering professionals. What You ll Be Doing: Architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications. Translating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features. Leading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks. Collaborating with global teams and engaging directly with customers to understand and refine specification requirements. Driving technical excellence in design processes, including linting, static timing analysis, formal checking, and P&R-aware synthesis using tools such as Fusion Compiler. Mentoring and technically leading a team of designers, providing guidance on best practices and innovative design methodologies. Utilizing version control systems and scripting to manage design flows and automate repetitive tasks for improved efficiency. The Impact You Will Have: Enable Synopsys to deliver industry-leading, high-performance IP cores that power next-generation technologies. Contribute to the successful execution of complex, global projects that set new standards in chip design and verification. Accelerate time-to-market for customers in commercial, enterprise, and automotive sectors by delivering robust, reliable IP solutions. Elevate the technical capabilities of your team through mentorship and leadership, cultivating a culture of continuous learning and innovation. Drive improvements in design quality, efficiency, and scalability through process optimization and automation. Directly influence product architecture and feature enhancements, ensuring alignment with customer needs and emerging industry trends. What You ll Need: Bachelor s or Master s degree in Electrical Engineering, Electronics, VLSI, or related field. 4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects. Deep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines. Proficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis. Familiarity with high-speed design (>600MHz), P&R-aware synthesis, and EDA tools such as Fusion Compiler. Experience with version control systems (e.g., Perforce) and scripting languages (Perl, Shell) for design automation. Knowledge of industry protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA (AMBA2, AXI). Exposure to quality processes in IP design and verification is an advantage. Prior experience as a technical lead or mentor is highly desirable. Who You Are: Innovative thinker with a solutions-oriented mindset and a passion for technology. Excellent communicator who thrives in collaborative, multicultural, and multi-site environments. Natural leader with mentoring abilities, fostering inclusion and diversity within the team. Detail-oriented professional with strong analytical and problem-solving skills. Self-motivated, adaptable, and eager to drive technical excellence and process improvements. Committed to continuous learning and staying ahead of industry trends. The Team You ll Be A Part Of: You will join the R&D Solutions Group at our Bangalore Design Center, as part of the DesignWare IP Design team. This diverse and innovative group is dedicated to architecting, developing, and delivering cutting-edge IP cores that enable Synopsys global customers to achieve their design goals. The team thrives on collaboration, technical excellence, and shared success, working in a supportive environment that values creativity, knowledge sharing, and continuous growth. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Required Qualifications Bachelor's degree /masters degree in Electronics & Tele Engineering, Microelectronics, Computer Science, or related field. 9+ years RTL Design/Hardware Engineering experience or related work experience. Skills/Experience Required Strong Domain Knowledge on RTL Design , implementation, and integration. Experience with RTL coding using Verilog/VHDL/System Verilog. Experience in micro-architecture & designing cores and ASICs. Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc. Exposure in scripting (Pearl/Python/TCL). Strong debugging capabilities at simulation, emulation, and Silicon environments. Collaborate closely with cross-function team located in different time zone to research, design and implement performance and power management strategy for product roadmap. Good team player. Need to interact with the other teams/verification engineers proactively. Responsibilities Design and lead all Front-end design activities for Display Sub-system that deliver cutting edge solution for various Qualcomm business unit like VR, AR, Compute, IOT, Mobile. Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check, and formal verification for IP blocks. Work closely with technology/circuit design team to close IP block specification/requirement. Work closely with verification/physical design team to complete the IP design implementation. Support SoC team to integrate Display Sub-system IP solution into various SoC chips and front-end design flows. Work closely with system/software/test team to enable the low power feature in wireless SoC product. Evaluate new low-power technologies and analyze their applications to address requirements. Understand and perform block & chip-level performance analysis & identify performance bottleneck and provide required solution. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

You are a highly motivated and experienced professional with a deep understanding of VLSI design and a strong background in high-speed protocols Analog Circuit Design CMOS circuit design and layout methodology & flow Familiarity with ASIC design flow Knowledge of JEDEC requirements for DDR interfaces & standards, DDR Timing, ODT and SDRAM functionality would be a plus What Youll Be Doing: DDR/HBM Memory Interface I/O Circuit and layout design including GPIO and Special IOs Work with DDR/HBM PHY team, package engineers and system engineers to meet design specifications What Youll Need: Bachelor's and/or Master's Degree in Electrical Engineering or similar with a focus on VLSI design Who You Are: Creative and results-oriented, capable of managing multiple tasks concurrently Strong verbal and written communication skills in English Ability to work collaboratively across teams to deliver solutions to customers Strong analytical, reasoning, and problem-solving skills Willingness to travel occasionally to support customer engagements The Team Youll Be A Part Of: The team focuses on enabling our Interface IP customers to integrate the IP into their SoC and assist them through their design flows, debugging critical issues, and supporting silicon bring-up This collaborative team works closely with customers to ensure the successful deployment of Synopsys' leading Interface IP products in various market segments

Overview: The role is for an Active Directory Engineer in Core Infra IAM operations within Identity & Access Technology Services, responsible for the operation of the Active Directory environment and related technologies. Responsible for the delivery of tiered admin solution and other global solutions for both on premise and cloud identity solutions. The successful candidate must possess relevant experience of operating enterprise scale identity platforms. Role / Principal Accountabilities: The Core Infra IAM function is responsible for operating of all aspects of core infrastructure components relating to Identity and Access Management. The candidate must be highly self-motivated team player with good oral and written skills and confidence to present to management. The candidate should also have a good sense of discipline for change control procedures. A flexible work ethic is required with the ability to form part of a multi-platform global function Skills & Experience Required: Demonstrate an ability to work well as part of a global team, and on their own when required. Strong oral and written communication Enthusiastic, eager and personable. Ability to cope well under pressure. Essential: Subject-matter expert knowledge of Active Directory related technologies (i.e., Group Policy, DHCP, DNS, Active Directory enterprise design principles etc.) Subject-matter expert knowledge of Active Directory OU structures and delegation models and understanding of impact when moving objects within OU structures. Subject-matter expert knowledge of Windows Server technologies Experience in using and developing automation and scripting (PowerShell) to drive efficiencies. Desirable: Enterprise-scale technical experience designing and deploying tiered administrative / Enterprise Access Models.

You will be responsible for working with the VisualSim architect software package to develop a complete test bed for an application in the fields of VLSI, aerospace, or automotive. Your role will involve researching and proving assertions on existing technology challenges, analyzing models, and comparing results with similar papers published online. Additionally, you will be required to write an industry paper based on your findings and publish it. To be successful in this position, you must have completed coursework in computer architecture, VLSI design, processor internals, and related studies. It is also essential to have prior experience in evaluating semiconductor or embedded system architecture through school projects or internship work.,