1181 Floor Planning Jobs

As an ASIC Physical Design Lead, you will be responsible for leading the design of IP/SoC in advanced process technologies for global Semiconductor product MNC clients. Key Responsibilities: - Lead the physical design of complex ASIC projects from Netlist to GDSII. - Perform timing closure tasks including synthesis, place and route, and static timing analysis. - Oversee full-chip physical design processes, including floor planning, power grid design, clock tree synthesis, and signal integrity analysis. - Collaborate with the packaging team to ensure seamless integration of the chip design with the package, including pads log management, bump placement, and RDL routing. - Mentor junior engine...

As an Analog Mixed Signal (A&MS) Layout Engineer at Synopsys, you will be a part of the Analog Mixed Signal IP Team working with cutting-edge technologies in chip design and software security. Your role involves working on custom layout Analog IPs such as High Speed IOs, PLL, DLL, Bandgap, and High-Speed macros for PHY and Clock trees. You will be responsible for floor planning, power design, signal routing strategy, EMIR awareness, parasitic optimization, and layout verification for various parameters. Additionally, you will collaborate with global teams, participate in design reviews, and may lead a layout team or mentor junior engineers. Key Responsibilities: - Work on custom layout Analo...

As an ASIC Physical Design Engineer, your primary role will be to oversee the physical implementation of ASIC designs while working closely with design and verification teams to ensure optimal performance. Your daily tasks will involve logic synthesis, floor planning, clock tree synthesis, physical verification, and timing closure. Additionally, you will be responsible for supporting RTL-to-GDSII flow development and optimization to meet PPA (Performance, Power, Area) goals. Key Responsibilities: - Execute the complete Physical Design Flow (RTL to GDSII) for high-speed, complex digital blocks or full-chip integration. - Perform Floorplanning and Power Grid (PDN) Synthesis to optimize for pow...

Mirafra Technologies Hiring Physical Design - CAD Engineers Experience - 3 to 5 years Notice Period - 0 to 30 days Location - Bangalore Job Description: Job involves PDCAD Jira support and HM PDCAD flow flush for all Bangalore projects. Candidate needs to be working closely with CAD team and provide feedback pertaining to Flow/Design issues. Candidate should have good knowledge on floor planning, place and route, timing and power analysis required for establishing flows and methodology for physical design flow (low power methodology) Minimum Qualifications: Support ASIC physical design tools from Synopsys Fusion Compiler Provide tool support and issue debugging services to design teams. Inte...

As an experienced Physical Design Engineer in Hyderabad and Guntur, your role will involve: - Executing block level Place and Route (P&R) and Timing closure activities. - Owning up block level P&R and performing Netlist2GDS on blocks. - Implementing multimillion gate SoC designs in cutting-edge process technologies such as 28nm, 16nm, 14nm, and below. - Demonstrating strong hands-on expertise in various aspects of physical design, including Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning, Clock Tree Synthesis, analog IP integration, Parasitic Extraction, Timing Closure, Power/IR Drop (Static and Dynamic), Signal Integrity Analys...

Principle/Staff STA Engineer Job Summary We are seeking a highly skilled and experienced Principle/Staff STA Engineer to join our dynamic team in Noida. This role involves leading and executing Static Timing Analysis (STA) for complex SoC designs, ensuring timing closure, and contributing to the development of next-generation semiconductor products. --- Job Responsibilities Lead and perform comprehensive Static Timing Analysis (STA) at the block, sub-system, and SoC levels for cutting-edge semiconductor designs. Develop, integrate, and maintain timing constraints (SDC) for various design hierarchies, ensuring accuracy and coverage. Identify, debug, and resolve complex timing violations, incl...

Roles and Responsibility Develop and implement effective staffing strategies to meet business needs. Manage and oversee the entire recruitment process, from job posting to onboarding. Build and maintain relationships with clients and vendors to ensure successful placements. Lead and motivate a team of recruiters and staff to achieve high performance levels. Analyze market trends and competitor activity to stay ahead in the industry. Ensure compliance with all relevant laws and regulations related to employment. Job Requirements Proven experience in staffing and recruitment, with a minimum of 8 years of experience. Strong knowledge of recruitment principles, practices, and technologies. Excel...

Skill set required : Should have a very good understanding of semiconductor and analog basics. Good hands-on experience in toplevel integration and block level analog layouts like ADC/DAC/PLL/high speed Serdes, Power Management blocks Hands-on experience in 7nm, 5nm. N3E or lower node experience is a plus. Good Experience with floor planning, matching, EM/IR and DFM issues and other analog layout related concepts and hands on implementation from scratch. Experience of LVS, Density, lower node DRCs, Parasitic reduction and other lower node challenges. Good experience in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Good problem solving and logical reaso...

Responsibilities: Block level or Top Level implementation experts from Netlist to GDSII. * Optimize physical design using STA, PNR, ICC, Primetime & TCL. * Manage floor planning, timing closure & LVS compliance. Provident fund Health insurance Food allowance Annual bonus

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you ll discover the real differentiator is our culture. We push the limits of innovation to solve the world s most important challenges striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. To...

As a Project Manager in the Interior Fit-out Industry, your role will involve project management and execution, client interactions, and measurement of work. You will be responsible for preparing the Bill of Material for interior work, coordinating with the purchase team, and managing vendors and their teams at project sites. Ensuring work execution with proper safety measures will be a key part of your responsibilities. Additionally, you should have knowledge of construction technology, safety standards, building codes, and the ability to interpret blueprints, drawings, and specifications. Familiarity with CAD software and project management software would be advantageous. Role & responsibi...

Job Description Actively contribute to provide Custom Datapath solutions for next generation Memory in advanced CMOS technology nodes. Designing Datapath (custom and/or RTL) Blocks, Full chip Timing Finesim Design closure to meet the specifications and product requirements Work closely with team and actively participate in technical discussions and reviews. Pro-actively get design issues/problems solved. Contribute to or propose innovative design solutions and design methodologies. Qualifications Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering (VLSI Design) Hands-on design knowledge on both Digital custom, Analog & mixed signal design environment. 4+ years ...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engine...

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements Minimum Qualifications: Bachelor's degree in Computer Sci...

. Roles and Responsibility PD The candidate will be responsible for implementing the place and route of design blocks including floorplanning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc . The candidate will also be responsible for block level physical design closure in terms of timing, power, DRC/LVS etc. Full Chip Floorplan: Bus planning Pin assignments Tile area allocations Repeater planning and Feedthrough push Full chip Tile PnR 7-10 yrs of experience, preferably with AMD experience

Job Description The company is looking for several FPGA developers for their operations within product development and IT in Pune. Qualifications Must have : Minimum of 7 years working experience of FPGA code development in VHDL, Verilog and/or System Verilog programming languages Experience of FPGA domain crossing designs Experience of FPGA timing analyses Experience of FPGA floorplanning Worked with either AMD/Xilinx or Intel/Altera FPGA:s and tools such as Vivado, ISE, Quartus etc. Competency in software scripting languages such as Python and Tcl Excellent communication skills in English both orally and in writing. Bachelors or Master s degree in computer science, Electronics Engineering,...

Looking for: *STA Engineer *DFT Engineer * Design Verification Engineer * Develop RTL designs using ASIC methodology. * Implement STA and DFT techniques during physical design phase. Mail: chaitanya.vasamsetti@gigaopsglobal.com Office cab/shuttle Food allowance Health insurance Annual bonus Provident fund

Role Overview: You will be responsible for the complex SOC Top Physical Implementation of next generation SOCs, including mobile application processors, modem sub-systems, and connectivity chips. Your role will involve tasks such as Synthesis, Place and Route, STA, timing and physical signoffs. Additionally, you will work on physical design and timing closure of complex blocks and full-chip designs. Key Responsibilities: - Perform top level floor planning, including partition shaping and sizing, pin placement, channel planning, high-speed signal and clock planning, and feed-through planning. - Understand timing, power, and area trade-offs for optimization of PPA. - Utilize industry standard ...

You are a Physical Design Engineer who will be responsible for delivering high-performance design flows for high-performance SoCs in sub-10nm process for the mobile space. Your role will involve the following key responsibilities: - Hands-on experience of different PnR steps including Floor planning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post-route optimization, ECO implementation, and DRC closure. - Well-versed with high-frequency design & advanced tech node implementation. - In-depth understanding of PG-Grid optimization, including the identification of high vs low current density paths & layer/via optimization, Adaptive PDN experience. - In-depth ...

Role Overview: You will be responsible for designing a hospital building spanning 50,000 square feet across 5 floors. Key Responsibilities: - Design the hospital building layout considering space utilization and functionality - Ensure compliance with building codes and regulations - Collaborate with architects, engineers, and contractors to ensure successful project completion Qualifications Required: - Proven experience in designing commercial or healthcare buildings - Proficiency in architectural design software - Strong knowledge of building codes and regulations Please note that this is a contractual/temporary position for a duration of 1 month, and the work location is on-site.,

Location: Bengaluru, India Type: Full-Time Industry: Semiconductors / VLSI / ASIC Design Job Summary We are seeking an experienced Physical Design Technical Manager to join our chip development team. In this leadership role, you will drive the implementation and optimization of complex ASIC designs from RTL to GDSII . You will collaborate closely with RTL, Verification, and DFT teams to ensure successful tape-outs of high-performance, low-power silicon designs, while mentoring team members, driving execution, and contributing to methodology and flow improvements. Key Responsibilities Technical Manager Responsibilities (Added Pointers) Own project planning, resource allocation, and delivery f...

We are seeking an experienced Physical Design Tech Lead to join our chip development team. In this leadership role, you will drive the implementation and optimization of complex ASIC designs from RTL to GDSII . You will collaborate closely with RTL, Verification, and DFT teams to ensure successful tape-outs of high-performance and low-power silicon designs while mentoring team members and contributing to flow and methodology improvements. Key Responsibilities Leadership Responsibilities Lead and mentor the Physical Design engineering team while also contributing as an individual contributor. Drive execution, quality, and schedule for block-level and full-chip physical design activities. Revi...

As an IC Layout Manager at Micron Technology, you will have the opportunity to lead a team in designing IC layout for intensive applications such as artificial intelligence and high-performance computing solutions like High Bandwidth Memory. Your role will involve collaborating with peer teams across Micron's global footprint to ensure the successful completion of multiple projects. **Responsibilities:** - Provide leadership in building and growing a Custom layout team to support Micron's global DRAM layout requirement. - Develop Analog and custom layout to meet schedule and milestone. - Train the team in technical skills and cultural healthiness. - Communicate effectively with engineering t...

Required skills: He/She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design engrs. Interface with front-end ASIC teams to resolve issues. Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques. Timing...