160 Eda Tools Jobs

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable todays needs and tomorrows next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world were living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. SanDisk, a leader in data storage solutions, is seeking talented and experienced ASIC RTL Design Engineers to join our cutting-edge team. Our mission is to revolutionize the data storage industry through relentless innovation and technology breakthroughs. Job Description Join SanDisk India as a Technical ASIC Project Leader and take charge of developing the cutting-edge ASICs that power the next generation of the USB storage solutions. This is a high-impact leadership role where your technical expertise and strategic vision will drive projects from concept to mass production. Key Responsibilities Lead Full-Cycle SoC Development: Own the end-to-end development of high-performance ASIC controllers, from architecture definition to production ramp-up. Translate Product Vision into Technical Execution: Collaborate with product, firmware, and system teams to define ASIC requirements aligned with SanDisks storage solutions. Drive Cross-Functional Collaboration: Partner with SoC Design, Verification, Validation, DFT, Physical Design, Mixed-Signal IP, Foundry, Hardware, Firmware, and Test Engineering teams to deliver industry-leading SoC solutions. Ensure Technical Excellence: Conduct in-depth technical reviews, identify risks early, and implement mitigation strategies to ensure project success. Mentor and Inspire: Provide technical leadership and mentorship to engineering teams, fostering a culture of innovation, accountability, and continuous improvement. Communicate with Impact: Deliver clear, concise, and transparent project updates to stakeholders, ensuring alignment and enthusiasm across all levels. Qualifications Masters degree in electrical engineering, Computer Engineering, or a related field. Proven experience leading complex ASIC or SoC development projects. Strong technical background in digital design, verification, and silicon validation with good understanding of the USB, PCIe, ONFI standards and peripherals. Excellent cross-functional leadership and communication skills. Ability to manage technical risks and drive execution in a fast-paced environment. Passion for innovation and delivering high-quality, scalable solutions. Preferred Qualifications Proficiency with EDA tools and methodologies for ASIC development. Familiarity with industry standards and best practices in semiconductor design. Expertise in low-power design techniques and high-speed interfaces. Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [HIDDEN TEXT] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Show more Show less

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable todays needs and tomorrows next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world were living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Join SanDisk India as a Technical ASIC Project Leader and take charge of developing cutting-edge ASICs that power the next generation of SD cards for imaging, gaming, mobile, and data storage. This is a high-impact leadership role where your technical expertise and strategic vision will drive projects from concept to mass production. Key Responsibilities Lead Full-Cycle SoC Development: Own the end-to-end development of high-performance ASIC controllers, from architecture definition to production ramp-up. Translate Product Vision into Technical Execution: Collaborate with product, firmware, and system teams to define ASIC requirements aligned with SanDisks storage solutions. Drive Cross-Functional Collaboration: Partner with SoC Design, Verification, Validation, DFT, Physical Design, Mixed-Signal IP, Foundry, Hardware, Firmware, and Test Engineering teams to deliver industry-leading SoC solutions. Ensure Technical Excellence: Conduct in-depth technical reviews, identify risks early, and implement mitigation strategies to ensure project success. Mentor and Inspire: Provide technical leadership and mentorship to engineering teams, fostering a culture of innovation, accountability, and continuous improvement. Communicate with Impact: Deliver clear, concise, and transparent project updates to stakeholders, ensuring alignment and enthusiasm across all levels. Qualifications Masters degree in electrical engineering, Computer Engineering, or a related field. Proven experience leading complex ASIC or SoC development projects. Strong technical background in digital design, verification, and silicon validation with understanding of the SD, UHS and SD-Express standards. Excellent cross-functional leadership and communication skills. Ability to manage technical risks and drive execution in a fast-paced environment. Passion for innovation and delivering high-quality, scalable solutions. Preferred Qualifications Proficiency with EDA tools and methodologies for ASIC development. Familiarity with industry standards and best practices in semiconductor design. Expertise in low-power design techniques and high-speed interfaces. Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [HIDDEN TEXT] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Show more Show less

Job description Responsibilities may be quite diverse of a technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually for the summer or for short periods during breaks from school. Qualifications Mtech graduate with below skillsHardware : VLSI Design, Custom Layout, ESD verification Software : Python, perl Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Job description Job Description Responsibilities may be quite diverse of a technical nature US experience and education requirements will vary significantly depending on the unique needs of the job Job assignments are usually for the summer or for short periods during breaks from school Qualifications Mtech graduate with VLSI skill Role: Research & Development - Other Industry Type: Electronic Components / Semiconductors Department: Research & Development Employment Type: Full Time, Permanent Role Category: Research & Development - Other Education UG: B.Tech/B.E. in Any Specialization PG: M.Tech in Any Specialization

Job description Responsibilities may be quite diverse of a technical nature US experience and education requirements will vary significantly depending on the unique needs of the job Job assignments are usually for the summer or for short periods during breaks from school. Qualifications Mtech graduate with VLSI skills.

We are seeking a highly experienced Hardware Verification Engineer with extensive hands-on experience in block-level, IP-level, and SoC-level verification. You will leverage your proficiency in Verilog, SystemVerilog, and UVM-based testbenches, along with knowledge of industry-standard EDA tools, to ensure the robustness and functionality of complex hardware designs. This role requires strong problem-solving and communication skills, and an in-depth understanding of ARM AMBA protocols. Hardware Verification Engineer Roles & Responsibilities: Develop and execute comprehensive verification test plans for block-level, IP-level, and SoC-level designs. Create and maintain efficient UVM-based testbenches . Utilize Verilog and SystemVerilog for testbench development and assertion-based verification. Employ industry-standard EDA tools for simulation and debug to identify and resolve hardware design issues. Verify the functionality and performance of IPs for caches, cache coherency, memory subsystems, interconnects, and NoCs (Networks-on-Chip). Collaborate closely with design teams to understand architectural specifications and ensure verification coverage. Debug complex hardware and software interactions, contributing to root cause analysis. Potentially explore and apply formal verification techniques and emulation platforms . Ensure the quality and reliability of hardware designs prior to tape-out. Qualifications and Preferred Skills: Strong hands-on experience in block-level/IP-level/SOC-level verification . Proficiency in Verilog, SystemVerilog . Familiarity with industry-standard EDA tools for simulation and debug . Deep experience with UVM-based testbenches . Experience with modern programming languages like Python . Knowledge of ARM AMBA protocols such as AXI, APB, and AHB. Understanding of ARM CHI protocol is a plus. Experience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NOCs. Experience with formal verification techniques, emulation platforms is a plus. Excellent problem-solving skills and attention to detail. Strong communication and collaboration skills. QUALIFICATION: BS, MS in Electrical Engineering, Computer Engineering or Computer Science.

As a senior leader in the central physical design team at Marvell, you will shape the long-term vision for physical design capabilities and infrastructure in alignment with the company-wide technology strategy. You will lead RTL-to-GDSII implementation for multiple SoC programs, overseeing synthesis, floorplanning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, and physical verification (DRC/LVS). Your role will involve providing strategic leadership and technical direction to physical design teams, ensuring successful and timely tapeouts of complex, high-performance SoCs. Mentoring and developing engineering talent will be a key aspect of your responsibilities, fostering a culture of innovation, collaboration, and continuous improvement within the team. You will oversee team structure, hiring, performance management, and career development to build and retain a high-performing physical design organization. Driving cross-functional collaboration with design teams to influence design decisions and ensure successful project execution will also be part of your role. You will navigate and resolve cross-functional conflicts effectively, fostering alignment and maintaining momentum across diverse teams. It will be your responsibility to drive the development and adoption of next-generation physical design methodologies, flows, and automation to improve productivity and design quality. Managing project schedules, resources, and risks to ensure alignment with business goals and customer requirements will also fall under your purview. Representing the physical design function in cross-org and executive-level discussions, contributing to long-term technology and product strategy will be expected. Collaborating with EDA vendors and internal CAD teams to evaluate and deploy new tools and technologies is also a crucial aspect of the role. We are looking for candidates with a Bachelors, Masters, or PhD degree in Electrical Engineering, Computer Engineering, or a related field, along with 18+ years of progressive experience in back-end physical design and verification, including significant leadership roles. A proven track record in leading and scaling physical design teams, managing complex SoC projects, and delivering high-quality tapeouts under aggressive schedules is essential. Deep expertise in hierarchical physical design strategies, methodologies, and advanced process node challenges is required. Additionally, familiarity with AI/ML-driven optimization in physical design tools is considered a plus. Strong communication and collaboration skills, along with the ability to influence cross-functional teams and executive stakeholders, are also important qualities for this role. Proficiency in automation and scripting using Makefile, Tcl, Python, or Perl to enhance design efficiency and flow robustness is expected. Marvell offers competitive compensation, great benefits, and a workstyle that promotes shared collaboration, transparency, and inclusivity. The company is dedicated to providing its employees with the tools and resources they need to succeed in meaningful work, grow, and develop within the organization. For more information on working at Marvell, visit our Careers page.,

Allegion is seeking a highly motivated Senior Hardware Engineer to join our dynamic team and play a pivotal role in designing and developing high-quality hardware and product solutions. You will work collaboratively within a cross-functional environment, utilizing your strong technical skills in hardware design and comprehensive understanding of the product design and development cycle. As an organized self-starter, you will thrive in a fast-paced design culture. You will be responsible for playing a key role in the design and development of hardware solutions, collaborating within a larger team to ensure successful project outcomes. Your tasks will include developing and refining hardware architectures, designing embedded electronics with a focus on wireless communications, and evaluating system performance for optimization. Additionally, you will provide PCB design support, enhance product development processes through design tools automation and simulation, and ensure adherence to product development processes and life cycle management. The ideal candidate for this position is a Senior Hardware Engineer with at least five years of experience in hardware design and development. You should have a proven track record of contributing to complex projects, possess strong problem-solving skills, and expertise in embedded hardware and low power wireless designs. Excellent organizational skills, attention to detail, and the ability to collaborate effectively with cross-functional teams and external partners are essential. Strong communication and leadership abilities are crucial for fostering a collaborative team environment. Required skills include expertise in designing embedded systems based on Microcontroller/Microprocessor, experience in communication protocols, designing multi-layer PCBs, proficiency in EDA tools like Altium and LTSpice, knowledge of short-range wireless technologies, understanding of RF performance criteria, and familiarity with design for EMI/EMC. Additionally, experience in product compliance and reliability testing, manufacturing engineering, quality engineering, and reliability engineering is preferred. The successful candidate should be seasoned in electronic product development processes and life cycle management, as well as possess excellent communication, collaboration, and networking skills. Emotional resilience, negotiation abilities, and effectiveness in working within a team environment and cross-functionally are also important attributes. Education: B.E/B Tech or higher in EEE or ECE,

You are a highly experienced ASIC RTL Design Architect responsible for leading the design and verification of cutting-edge SoCs and high-speed digital IPs. With over 10 years of experience in ASIC/FPGA design, your expertise lies in RTL using Verilog/SystemVerilog, Lint, CDC, and Spyglass-based design verification methodologies. Your main responsibilities include leading RTL design and micro-architecture for high-performance ASIC SoCs, ensuring compliance with Lint, CDC, and SDC constraints using Spyglass or equivalent tools, driving design optimization and timing closure, as well as collaborating with cross-functional teams such as Design Verification, DFT, Physical Design, and Software teams. You will also be involved in developing and reviewing architecture specifications, coding guidelines, and best practices, as well as performing synthesis, timing analysis, and static verification using tools like STA, LEC, and Formal Verification. Key requirements for this role include a minimum of 10 years of experience in ASIC RTL design and architecture, expertise in Verilog/SystemVerilog for RTL design, strong knowledge of Spyglass Lint/CDC and static verification methodologies, experience in SoC micro-architecture, high-speed interfaces, and power optimization. Additionally, you should have a solid understanding of synthesis, STA, timing closure, backend constraints, experience with EDA tools like Synopsys, Cadence, Mentor Graphics, and familiarity with UVM-based verification and scripting languages such as TCL, Python, or Perl. Preferred qualifications include an M.Tech/MS/PhD in Electrical Engineering, Computer Engineering, or related field, experience in chip tape-out and production silicon, and an understanding of hardware security, reliability, and safety standards. If you are looking to be part of a team that is shaping the future of high-performance computing, apply now and join us in building innovative solutions together.,

You have experience in Mixed-Signal layout design and hold a bachelor's degree. Your responsibilities will include working independently on block levels analog layout design from schematic, estimating the Area, optimizing Floorplan, Routing, and Verifications. You should have firsthand experience in Critical Analog Layout design of blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier, etc. It is essential to have good LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below. You must possess a good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic, and short channel concepts. Familiarity with EDA tools like Cadence VLE/VXL, PVS, Assura, and Calibre DRC/LVS is a must. Understanding layout effects on the circuit such as speed, capacitance, power, and area is crucial. You should be able to understand design constraints and implement high-quality layouts. Multiple Tape out support experience will be an added advantage. Good people skills and critical thinking abilities to resolve issues technically and professionally are required. Excellent communication is essential, along with being responsible for timely execution with a high quality of layout design. Primary Skills: - Analog Layout - Process or technology experience: TSMC 7nm, 5nm, 10nm, 28nm, 45nm, 40nm - EDA Tools: - Layout Editor: Cadence Virtuoso L, XL - Physical verification: DRC, LVS, Calibre Secondary Skills: - IO layout,

As an IR Drop Engineer, you will be responsible for analyzing and optimizing the power distribution network in integrated circuits (ICs) to ensure minimal voltage drops and reliable performance. Your role involves collaborating with design and verification teams to identify potential issues related to voltage drop, electromigration, and power integrity, with the primary goal of enhancing the overall power delivery system within the IC to meet performance, reliability, and power efficiency requirements. Key Responsibilities: Power Delivery Network Analysis: Conduct detailed analysis of the power delivery network in IC designs to identify and mitigate potential IR drop issues. Utilize industry-standard tools and methodologies to simulate and analyze power distribution, ensuring optimal power integrity. Collaboration with Design Teams: Work closely with IC design teams to understand the circuit architecture and power consumption characteristics. Provide recommendations for layout and design changes to enhance power distribution and minimize IR drop. Voltage Drop Analysis: Perform voltage drop analysis to ensure that power is distributed uniformly across the IC, avoiding excessive voltage drops that may impact functionality. Electromigration Analysis: Evaluate the risk of electromigration in the power distribution network and propose design enhancements to mitigate potential issues. Tool Development and Automation: Develop and implement scripts or automation tools to streamline the IR drop analysis process, improving efficiency and accuracy using tools like Redhawk and Voltus. Qualifications: - Bachelors/Masters/Ph.D in Electrical Engineering or a related field. - Strong understanding of semiconductor devices, integrated circuit design, and power delivery systems. - Proficiency in using industry-standard EDA tools for power analysis. - Experience with scripting languages (e.g., Python, TCL) for automation. - Familiarity with electromagnetic simulation tools and methodologies. - Excellent communication skills and the ability to collaborate effectively with cross-functional teams. Job Type: Full-time Schedule: Day shift Experience: - Redhawk: 7 years (Preferred) - Power distribution network: 7 years (Preferred) - Voltage Drop Analysis: 7 years (Preferred) - Power Delivery Network Analysis: 7 years (Preferred) Work Location: In person Application Deadline: 01/10/2024,

Challenging and Interesting work on building and enhancing Indias only completely open-source RISC-V based SHAKTI processors. Learn everything about the entire flow from spec to silicon. Work on state-of-the-art research topics and engineering efforts. Exposure to engage with foreign universities and support in preparation to pursue higher studies in India/Abroad. Exposure to engage with leading industry partners thereby improving your career trajectory and exposure. International Publications can also be achieved as part of tenure, boosting your research potential for higher studies. Required Skill Set Must have basic expertise in at least one of: verilog, vhdl, bluespec system verilog and/or chisel. Must have knowledge: digital design, pipelining Basic computer architecture knowledge, include one or more of : in-order cores, out-of-order cores, processors, caches, SoC development, memory architecture, etc. Good to have experience with FPGAs , performance modelling, workload analysis/benchmarking, python scripting, knowledge of peripheral and communication IPs

Job Titles: Senior Staff ASIC RTL Design Engineer Bangalore location We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a passionate and highly skilled digital design engineer with a strong background in ASIC RTL design You thrive on technical challenges, enjoy collaborating with global teams, and are motivated by seeing your designs come to life in real-world products With over8 years of hands-on experience in architecting, implementing, and verifying complex digital systems, you are adept at translating functional specifications into efficient, robust RTL Your experience spans data path and control path designs, and you are comfortable working with industry-standard protocols such as Ethernet, DDR, PCIe, USB, and AMBA You possess deep expertise in synthesizable Verilog/SystemVerilog, design flows, and EDA tools You are equally at home mentoring junior engineers as you are diving deep into code or debugging complex issues Your ability to balance area, latency, and throughput trade-offs sets you apart, and your attention to detail ensures high-quality, reliable IP cores You communicate effectively with both technical and non-technical stakeholders and are comfortable engaging with customers to clarify requirements and ensure successful delivery You value diversity, inclusion, and continuous learning, and you bring a collaborative spirit to every project If youre ready to lead, innovate, and make a tangible impact in the world of high-performance silicon design, Synopsys is the place for you, What Youll Be Doing: Architecting, designing, and implementing state-of-the-art RTL for high-performance synthesizable IP cores within the DesignWare family, Translating complex functional and standard specifications into detailed architecture and micro-architecture documents for medium to high complexity blocks, Owning the entire digital design lifecycle, including RTL coding, synthesis, CDC analysis, debugging, and test development, Collaborating with global, multi-site teams of expert engineers to drive technical excellence and innovation, Interacting with customers to understand and refine specification requirements and providing technical guidance as needed, Mentoring and technically leading junior designers, fostering growth and sharing best practices within the team, Participating in design reviews, quality process improvements, and ensuring adherence to industry-leading verification and design methodologies, The Impact You Will Have: Delivering robust, high-quality IP cores that power next-generation commercial, enterprise, and automotive applications worldwide, Driving innovation in digital ASIC design, enabling faster, more efficient, and reliable silicon solutions for Synopsys customers, Contributing to the advancement of industry standards and protocols through technical leadership and deep domain expertise, Enhancing team performance through mentorship, knowledge sharing, and technical guidance, Strengthening Synopsysreputation as a leader in chip design by consistently delivering on complex customer requirements, Accelerating product development cycles by streamlining design processes and championing best-in-class methodologies, What Youll Need: Bachelors or Masters degree in EE, EC, or VLSI with8+ years of relevant industry experience in digital ASIC RTL design, Expertise in data path and algorithmic block design ( e-g , Reed Solomon FEC, BCH codes, MAC SEC engines) and architecture trade-offs, Proficiency in synthesizable Verilog/SystemVerilog RTL coding, simulation, and EDA tools, Hands-on experience with design flows including Lint, CDC, synthesis, static timing analysis, and formal checking, Strong knowledge of industry-standard protocols (Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA AXI/AMBA2), Experience with high-speed design (>600MHz), P&R aware synthesis, and tools like Fusion Compiler is a significant plus, Familiarity with revision control systems ( e-g , Perforce) and scripting languages (Perl/Shell), Prior experience as a technical lead or mentor within a design team is highly desirable, Who You Are: A collaborative team player who thrives in a global, distributed environment, An effective communicator, adept at conveying complex technical ideas to diverse stakeholders, A proactive problem-solver with strong analytical skills and high initiative, Detail-oriented, quality-focused, and committed to delivering excellence, Passionate about mentoring and enabling the growth of others, Dedicated to diversity, inclusion, and fostering an open, respectful workplace, The Team Youll Be A Part Of: Youll be an integral member of the DesignWare IP Design R&D team at Synopsys Bangalore, collaborating with some of the brightest minds in the industry The team is focused on developing cutting-edge synthesizable IP cores that are deployed in a wide range of commercial, enterprise, and automotive applications Working in a multi-site, global environment, youll have opportunities to engage with cross-functional teams, contribute to technical excellence, and drive innovation in digital design, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process, Show

You should have good experience in PCB design, verification, and assembly. Additionally, you should possess expertise in schematic design, verification, and modification. It is preferable to have design and development experience in an industrial-related product. Experience in EMI/EMC compliance and intrinsically safe design is also essential. You must excel in designing complex high-density multi-layer PCBs utilizing different types of high-density and SMD packages. Furthermore, proficiency in standard analog and mixed-signal design is required. Knowledge of creating, checking, and editing Gerber and plot files is important. Exposure to all relevant IPC standards and MIL Standard design is crucial. Experience in at least one EDA tool like Cadence Allegro, Orcad, Mentor Graphics, Altium, or CAD-Star is expected. Understanding of PCB fabrication and assembly, passive components, transistors (BJTs and FETs), troubleshooting, and documentation is necessary. Ability to work independently and as a team member to meet product delivery goals is vital. You should be capable of defining and communicating problems clearly to others while collaborating across multiple groups. Expertise in high-speed design is preferred, and knowledge in SI and PI simulation is required. Familiarity with Flex PCB will be appreciated. Responsibilities: - Perform product characterization and develop specifications. - Design schematics. - PCB design and PCB layout. - Gerber generation. - Prototype board bring-up, testing, and debugging. - Resolve any design issues during the development phase. - Documentation.,

You are an experienced Hardware Board PCB design engineer with over 3 years of experience, based in Vadodara, India. You possess a strong systems knowledge and have the ability to grasp high-level concepts quickly to achieve results effectively. Your skills include: - Working experience across various stages of hardware product development cycles - Expertise in High-speed board design - Proficiency in working with protocols such as PCIe, USB3.0, MIPI CSI/DSI, LVDS, HDMI, DDR3/4, SD/eMMC, NAND, SPI/I2C - Experience with peripherals like Image sensors, LCD displays, Flash memory, etc. - Strong knowledge of Timing, Pre and Post Signal Integrity Analysis, and simulation tools - Solid experience in board power supply design, Switching and linear regulators, and power supply filtering - Good understanding of board design guidelines, implementation, and EMI/EMC aspects - Skills in board bring-up, functional testing, DVT measurements, and validation - Proficiency in using EDA tools like Cadence Orcad, Allegro, Visio, Altium - Hands-on experience with board level testing and lab instruments such as Function generator, Oscilloscope, Multimeter - Awareness of board mechanical fitment - Excellent analytical and problem-solving skills - Strong team player with effective communication skills for cross-functional collaboration About A&W Engineering Works: A&W Engineering Works is focused on developing and deploying innovative solutions to real-world problems. The team at A&W Engineering Works is skilled in hardware, software, mechanical, and system development, and aims to address challenging problems by leveraging unique innovative development techniques for fast prototyping and delivering quick proof of concepts while preparing for production. To apply, please send your resume and cover letter to [email protected] with the job title in the subject line.,

IT Specialist (Semiconductor Domain) Role Summary: Supports and maintains IT infrastructure critical to semiconductor design, manufacturing, and testing environments. Key Responsibilities: Manage servers, networks, and storage systems used in EDA and manufacturing tools. Ensure cybersecurity compliance and data integrity. Support CAD tools, simulation software, and license management. Collaborate with engineering teams to optimize IT workflows. Troubleshoot hardware/software issues in cleanroom and lab environments. Qualifications: Bachelors in Computer Science , IT, or related field. Experience with Linux/Unix systems and semiconductor design tools. Knowledge of scripting (Python, Shell) and virtualization.

Job Details Job Description: Altera is looking for a talented and driven Silicon Design Engineering Manager to lead and inspire a multidisciplinary silicon design team. In this critical role, you will manage design engineers across multiple functional domainsincluding logic design, verification, circuit design, and physical implementationfor cutting-edge IP, subsystems, SoCs, and discrete chips. Youll be at the forefront of Alteras product innovation, driving high-quality silicon solutions that meet power, performance, area, and cost objectives. Key Responsibilities Lead and manage a team of silicon design engineers across multiple disciplines and development phases. Drive end-to-end development of IP blocks, subsystems, and full-chip SoC designs, ensuring on-time delivery with high quality. Oversee design reviews, ensuring power, performance, area (PPA), and cost targets are met. Collaborate with architecture, IP, and SoC development teams to ensure cohesive design and execution. Monitor verification results, conduct design debug, analyze data, and drive resolution of design issues. Implement and maintain rigorous silicon quality and continuous improvement standards. Optimize and evolve silicon development methodologies, tools, and processes. Set clear team goals, manage priorities, provide coaching, and foster a culture of accountability and high performance. Role model Altera and Intel values while creating an inclusive, productive, and innovative work environment. Minimum Requirements Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. 10+ years of experience in silicon design, including at least 3 years in a management or technical leadership role. Proven track record managing full lifecycle silicon design projects from architecture through tape-out. Strong technical background in logic design, verification, and physical design. Deep understanding of PPA trade-offs and experience driving metrics-based decision making. Experience working across functional teams and global development environments. Preferred Qualifications Experience in SoC or FPGA-based design projects. Familiarity with industry-standard EDA tools and design methodologies. Demonstrated leadership in team building, performance management, and talent development. Strong communication and organizational skills. Qualifications Job Type: Regular Shift Shift 1 (India) Primary Location: Bengaluru, Karnataka, India Additional Locations: Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Show more Show less

Senior Specialist Software Engineering (Semiconductor) Role Summary: Develops software tools and systems that support semiconductor design, simulation, and manufacturing. Key Responsibilities: Design and implement software for EDA, automation, or data analysis. Optimize algorithms for performance and scalability. Collaborate with hardware and process teams to integrate software solutions. Maintain code quality and documentation. Lead software architecture decisions and mentor developers. Qualifications: Bachelors/Masters in Computer Science or Software Engineering. Experience with C++, Python, and semiconductor workflows. Knowledge of EDA APIs and data formats (e.g., GDSII, LEF/DEF).

KEY RESPONSIBILITIES: Work closely with CAD implementation members to deliver high quality tools and flows that meet all the key metrics of QoR: Manufacturability, Reliability, Timing, Area, and Performance. Regress methodology and develop capabilities to improve quality. Develop the strategy and key initiatives to ensure the CAD flows meet the future design needs and the most advances technologies. PREFERRED EXPERIENCE: 3-5 years experience in Silicon design or CAD/EDA development Understanding of EDA tools from Synopsys and Cadence Synopsys 3DIC Compiler experience is a plus Proficient in programming with Python and Linux Familiar in automating workflows in a distributed compute environment. Excellent communication skills (both written and oral). ACADEMIC CREDENTIALS: Bachelors or Masters degree in Computer Engineering/Electrical Engineering

Key Responsibilities: Critical Issue Resolution: Identify and resolve complex physical design problems during dry runs and execution. Provide independent analysis and solutions to critical issues impacting design integrity and performance, including challenges specific to CPU core physical design such as timing closure, optimization, and signal integrity Securing Execution Excellence: Ensure high standards of execution excellence by providing strategic guidance and support to the PD execution team. Monitor and evaluate the effectiveness of physical design processes and methodologies, ensuring optimal performance and power efficiency for CPU cores Bridging Methodology and Execution: Act as a liaison between the PD methodology team and PD execution team to ensure seamless integration of methodologies into practical execution. Facilitate communication and collaboration between teams to address challenges and optimize design processes for CPU core designs Data Analytics Generate and analyze data points to identify potential design failures and areas for improvement. Use advanced tools and techniques to predict and mitigate risks, focusing on CPU core-specific issues like floorplanning, placement, and routing Independent Review and Opinions: Conduct thorough and independent reviews of design methodologies and flows. Offer unbiased opinions and recommendations based on extensive experience and expertise in CPU core physical design strategies Mentorship and Guidance: Mentor and guide design teams on best practices and innovative solutions and share insights and knowledge to enhance team capabilities. Communication: Communicate findings and recommendations effectively to stakeholders and higher management, emphasizing CPU core design considerations Qualifications Education: Ph.D. or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Experience: Minimum of 20 years of experience in physical design, EDA tools, or related areas. Proven track record of driving PD methodology innovations and strategies in a leading semiconductor company. Technical Expertise: Deep understanding of physical design, EDA tools, and design optimization techniques. Proficiency in relevant tools and technologies. Publications and Patents: Demonstrated history of publications in reputable journals and conferences. Experience with filing and securing patents related to physical design and EDA tools. Leadership Skills: Strong leadership and team management skills. Ability to lead cross-functional teams and drive complex projects to successful completion. Communication: Excellent verbal and written communication skills. Ability to articulate complex technical concepts to diverse audiences. Industry Knowledge: In-depth knowledge of industry trends, standards, and best practices in physical design for semiconductors. Why Join Us Innovative Environment: Be part of a team that is at the forefront of physical design methodology innovations. Impactful Work: Contribute to the development of cutting-edge technologies that shape the future of semiconductor design. Collaborative Culture: Work with a diverse and talented team of professionals who are passionate about technology and innovation. Career Growth: Opportunities for professional development and career advancement in a dynamic and growing company.

IIT Bombay is hiring one experienced administrator on a full-time contractual basis to manage EDA tools, IPs, and cloud-based infrastructure for semiconductor design projects. Bachelors/Master’s degree in Electrical Engineering, Computer Science. Health insurance

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive design optimizations to improve QoR. Block/Partition signoff closure for STA, PV, LEC, IR/EM, CLP very efficiently. Provide technical leadership and guidance to the physical design team, mentoring junior engineers and fostering a culture of excellence. Work closely with RTL design and DFT teams to understand design requirements and constraints, and drive successful tapout of designs. Support and Development of advanced physical design methodologies and flows for complex semiconductor designs. Requirements Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. 4+ years of experience in physical design of ASICs Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics for Synthesis, PnR, Signoff Closure. Extensive experience with timing closure techniques, power optimization. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Expertise in Synthesis that includes details understanding of RTL, Early PnR timing issues, Constraint issue, design issues. Experience in handling Partitions and blocks for size estimation, pin assignment, CTS. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration. Detailed Knowledge on Clocking methodology and various techniques to improve skew, latency, timing, power. Familiarity with low-power design techniques and methodologies, such as multi-voltage domains and power gating using UPF. Expertise in physical verification, including DRC, Antenna, LVS, PERC, and ERC checks. Expertise in Timing Closure including setup, hold, DRV, SI, Interface issues. Experience with formal verification for RTL to Netlist and Netlist to Netlist. Knowledge of emerging technologies such as machine learning and AI for design automation and optimization.

NVIDIA is continuously reinventing itself, with a rich history that includes inventing the GPU, which sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. The current global boom in artificial intelligence research demands highly scalable and massively parallel computation horsepower, a challenge where NVIDIA GPUs excel. As a part of NVIDIA, you will be joining a dynamic team focused on tackling difficult global challenges and amplifying human creativity and intelligence. The diverse and supportive environment at NVIDIA encourages everyone to strive for excellence and make a lasting impact on the world. NVIDIA is seeking a talented ASIC STA Engineer to join the Networking Silicon engineering team. In this role, you will contribute to the development of high-speed communication devices, ensuring the highest throughput and lowest latency for AI platforms. You will work on designing innovative large-scale chips and collaborate in a professional environment where your contributions matter. Key Responsibilities: - Lead full chip and/or chiplet level STA convergence from initial stages to signoff. - Contribute to top-level floor plan and clock planning. - Optimize CAD signoff flows and methodologies. - Integrate digital partitions and analog IPs timing, provide feedback to PD/RTL, and drive convergence. - Collaborate closely with logic design and DFT engineers to define and implement constraints for various work modes efficiently. Requirements: - B.Sc./M.Sc. in Electrical Engineering/Computer Engineering. - 3-8 years of experience in physical design and STA. - Proven expertise in RTL2GDS and STA design and convergence. - Familiarity with physical design EDA tools (e.g., Synopsys, Cadence). - Hands-on experience with STA using Synopsis Primetime. - Strong understanding of timing concepts and a collaborative team player. At NVIDIA, we have a team of forward-thinking individuals who are passionate about pushing boundaries. If you are a creative engineer who enjoys challenges and is ready to grow professionally, come be a part of our industry-leading physical design team. JR1995153,

The Common Hardware Group (CHG) at Cisco is responsible for delivering silicon, optics, and hardware platforms for core Switching, Routing, and Wireless products. As a part of this team, you will contribute to designing networking hardware for Enterprises, Service Providers, the Public Sector, and Non-Profit Organizations globally. Cisco Silicon One is a groundbreaking silicon architecture that allows customers to utilize top-of-the-line silicon in various network environments. Join us in shaping innovative solutions by working on the design, development, and testing of complex ASICs. In this role, you will collaborate with the team on Verilog RTL and scripted flow implementation of Hardware Design-for-Test (DFT) features to support ATE, in-system test, debug, and diagnostics requirements. You will also be involved in Verilog testbench implementation for verification tests and automation scripts to enhance implementation quality and efficiency. **Minimum Qualifications:** - Bachelor's or Master's Degree in Electrical or Computer Engineering with a minimum of 2 years of experience. - Proficiency in DFT, test, and silicon engineering trends. - Familiarity with JTAG protocols, Scan and BIST architectures, ATPG, and EDA tools. - Verification skills in System Verilog Logic Equivalency checking and Test-timing validation. **Preferred Qualifications:** - Understanding of VLSI circuit physical behaviors in silicon. - Knowledge of timing concepts and EDA tools usage. - Strong verbal communication skills and adaptability in a dynamic environment. - Proficiency in scripting/coding languages such as Tcl, Python, Perl, or C/C++. Cisco is committed to embracing diversity, fostering innovation, and driving digital transformation. With a focus on inclusive teamwork and a culture of creativity, we encourage individuality and support continuous learning and growth. At Cisco, we value accountability, boldness, and diversity of thought. Join us in our journey to create a future where technology drives positive change and equality for all.,

The Common Hardware Group (CHG) at Cisco is responsible for delivering silicon, optics, and hardware platforms for the core Switching, Routing, and Wireless products. We design networking hardware for Enterprises, Service Providers, the Public Sector, and Non-Profit Organizations worldwide. Cisco Silicon One is a unique silicon architecture that allows customers to utilize top-of-the-line silicon in TOR switches, web-scale data centers, and across various networks with a unified routing and switching portfolio. Join our team and contribute to shaping Cisco's innovative solutions by participating in the design, development, and testing of cutting-edge ASICs. As a member of our team, you will be involved in the Verilog RTL and scripted flow implementation of Hardware Design-for-Test (DFT) features supporting ATE, in-system test, debug, and diagnostics requirements. Additionally, you will collaborate on Verilog testbench implementation for verification tests related to DFT features and use cases. Your role will also include contributing to automation scripts aimed at enhancing implementation quality and efficiency. **Minimum Qualifications:** - Bachelor's or Master's Degree in Electrical or Computer Engineering with a minimum of 2 years of experience - Knowledge of the latest trends in DFT, test, and silicon engineering - Proficiency in JTAG protocols, Scan and BIST architectures, including memory BIST and boundary scan - Familiarity with ATPG and EDA tools such as TestMax, Tetramax, Tessent tool sets, and PrimeTime - Verification skills encompass System Verilog Logic Equivalency checking and validating the Test-timing of designs **Preferred Qualifications:** - Understanding of VLSI circuit physical behaviors in silicon, including electrical migration and temperature/voltage effects - Knowledge of basic timing concepts like setup and hold, metastability - Experience with EDA tools - Strong verbal communication skills and ability to excel in a dynamic environment - Proficiency in scripting/coding languages like Tcl, Python, Perl, or C/C++ Cisco is a diverse and inclusive environment where individuality is celebrated, and collaborative teamwork drives meaningful change for an inclusive future. Embracing digital transformation, we assist our customers in implementing digital changes in their businesses, showcasing our expertise as both a hardware and software company. Our innovative network solutions adapt, predict, learn, and protect, setting us apart as a company that defies traditional categorization. At Cisco, we value accountability, boldness, and diversity of thought. We foster a culture of innovation, creativity, and learning from failures, all while promoting equality for all individuals. Our inclusive environment encourages employees to be themselves, whether it's through unique personal styles or a passion for technology and positive change. Join us at Cisco, where your individuality and dedication to excellence are celebrated.,