163 Soc Design Jobs

Job description Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 6+ years of technical experience. Related technical experience should be in/with: Silicon Design and/or Validation/Verification. Preferred Qualifications: Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. OVM/UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation.

Job description About The Role Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum (must haves) Bachelor's degree in electrical engineering or computer engineering with 4 to 9 years of experience or a master's degree in electrical engineering or computer engineering. 4+ years of experience in 5 or more of the following: Test Bench bring-up at SoC and strong programming skills in System Verilog, OVM and UVM. Test Plan development experience. Enabling regressions, maintaining QoV (quality of validation) with good functional/code/other coverage metrics. Familiarity with both simulation and emulation environments. Strong CPU/GPU architecture understanding. RTL Debugging module level or soc level system simulation failures. Monitoring and improve existing simulation environments and simulation efficiency. Good to Have: Building emulation models, enabling content Working with Validation Engineers and central CAD teams to support and maintain verification requirements in terms of Automation and tool flow support.

Job description About The Role About The Role As a SoC Micro-Architect, you will be responsible to work on feasibility of feature requests, partitioning them effectively and proposing an effective implementation which meets the desired Power, Performance and Area targets. You will need to work with cross functional teams and will be responsible for defining Micro-architecture specifications. Work with SoC Architecture, Platform, Firmware, Logic, Validation, Physical and DFT teams in defining and guiding SoC design implementationResponsibilities and duties:* Work with SoC Architecture to interpret high level architecture specs* Drive feature analysis and scoping* Define micro-architecture specifications.* Perform feasibility study on different third-party IP and drive integration* Drive RTL Implementation team, work closely with Backend team on floorplan, Constraints definition and timing analysis.* Closely work with Verification team and help define test plan and debug design.* Participate in design reviews.* Participate and drive timing convergence for high-speed designs including micro- architecture optimizations* Collaborate with internal and external team members on architectural decisions, development flows and methodologies* Lead end to end feature implementation and enablement.* Responsible for meeting SoC design quality, performance and power goals Qualifications Required qualifications:Educational requirements for this position are a BSEE/CE minimum, MS preferred.Also required 18 plus years experience in IC/SoC Design and Micro Architecture* Experience in all phases of logic development lifecycle from high-level specification to tape-out and production* Expertise in one or more of the following domains* AI server Micro Architecture* Power Management* Cache Management* Inter die IOs Micro Architecture* HBM IOs Micro ArchitectureBehavioral Traits* Excellent communication and documentation skill.* Must be skilled to influence in heavily matrixed environment.* Capable to operate in ambiguity where roles may not be clearly defined or teams across multiple/functions and IP/SOC must be pulled together.In this role you will be part for the Data center group (XEG - India) design team, working on next-generation Server and AI products. Inside this Business Group Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Job description Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyse power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the pre silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, micro architects, full chip architects, RTL developers, post silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from post silicon on the quality of validation done during pre silicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications Minimum 7 to 10 year of relevant experience in SoC emulation validation i.e. developing verification components integrating IP verification content to SOC preparing and executing test plan for complex clusters, subsystems for emulation platform. Good understanding and working experience in HVL System Verilog HDL, Verilog, C or C++ and scripts Perl shell Knowledge, experience in Industry standard emulation and debugging tools i.e. Zebu and/or palladium etc. . Good understanding of SoC Fabric [CXL mainly, cache coherency), Multimedia (Graphics, Media, Display, IPU), D2D/UCIE and Power Management clusters. Excellent debugging and analytical abilities. Qualifications BE or B Tech or M Tech ECE or Computer Science with 6-10 years emulation model bring-up and emulation verification experience at SoC level.

Job description Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications Minimum Qualifications: Candidate should have done Electrical or Computer Science Engineering or related field in Bachelor's with 8+ Years relevant experience or Master's with 6+ Years relevant experience or PhD with 4+ years relevant experience required. Related technical experience should be in/with: Silicon Design and/or Validation/Verification. Preferred Qualifications: Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. OVM/UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation.

Job description FPGA SoC Prototyping Engineer We are seeking an FPGA SoC Prototyping Engineer to develop and optimize FPGA-based prototypes for SoC validation. You will be responsible for FPGA synthesis, timing closure, partitioning, power flows, and system integration , enabling efficient presilicon verification and early software development. Key responsibilities: Build high-performance FPGA prototypes , addressing synthesis, timing, and system constraints . Debug and resolve synthesis, timing, and functional issues with design and verification teams. Innovate automation flows to improve FPGA usability and validation efficiency . Develop hybrid prototyping solutions (FPGA + virtual platforms) for SoC verification. Drive power-aware FPGA methodologies for accurate modeling and optimization. Support IP and SoC bring-up, testbench debugging, and system integration . This role requires problem-solving, creativity, and persistence to push the limits of FPGA prototyping for next-gen SoCs.

Job description Job Description Supporting development of leading Client SoCs for Intel working across various domains like Logic Design, Verification, Physical Design or DFT based the requirements and matching skillset. Qualifications Pursuing Post Graduate Degree (M.Tech. /ME/..) in Microelecronics/VLSI or similar streamPreferred Skill domains - Logic Design, Pre-Silicon Verification, Physical/Structural Design, Layout DFT, System Validation, Firmware

Job description Supporting development of leading Client SoCs for Intel working across various domains like Logic Design, Verification, Physical Design or DFT based the requirements and matching skillset. Qualifications Pursuing Post Graduate Degree (M.Tech. /ME/..) in Microelecronics/VLSI or similar stream. Preferred Skill domains -Logic Design, Pre-Silicon Verification, Physical/ Structural Design, Layout, DFT, System Validation, Firmware.

We are seeking a highly experienced Senior Field Applications Engineer with a strong background in electrical or computer engineering. You will leverage your expertise to provide customer-facing technical support, from architecture definition to tape-out of complex SoCs, addressing implementation challenges on advanced process nodes. This role requires excellent communication and interpersonal skills, along with an understanding of functional safety standards and RAS/reliability for enterprise markets. Roles & Responsibilities: Provide technical leadership and support in a customer-facing role . Support the design and implementation of complex SoCs (System-on-Chips) , from architecture definition through to tape-out. Address and resolve implementation challenges on advanced process nodes . Effectively engage with customers, colleagues, and partners at all levels to ensure project success and customer satisfaction. Act as a subject matter expert, guiding customers through technical complexities and offering optimal solutions. Skills Required: Experience in designing or supporting complex SoC , from architecture definition to tape-out, addressing implementation challenges on advanced process nodes. Understanding of RAS (Reliability, Availability, Serviceability) and reliability for enterprise and infrastructure markets is a plus. Understanding of functional safety standards and certification . Excellent communication and interpersonal skills , with the ability to effectively engage with customers, colleagues, and partners at all levels. Strong problem-solving and analytical abilities to tackle intricate technical issues. QUALIFICATION: Master's degree in Electrical Engineering, Computer Engineering, or related field.

You play a crucial role at AMD, where the focus is on transforming lives through innovative technology to make a difference in the industry, communities, and the world. The mission at AMD is centered around creating exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. The core of this mission lies in the AMD culture, which thrives on pushing the boundaries of innovation to tackle the world's most pressing challenges. The values of execution excellence, directness, humility, collaboration, and inclusivity of diverse perspectives drive the AMD team towards achieving their goals. As a SoC Design Architect at AMD, you will take on a leadership role in designing high-end networking silicon. Your responsibilities will include overseeing the development of SoCs in collaboration with IP, Subsystem, and Physical design teams. You will be detail-oriented when it comes to managing Power, Performance, and Area, while also ensuring adherence to schedules and cost management. This senior position will challenge you to lead the development of cutting-edge networking IP and silicon, coordinating milestones across various geographical locations. To excel in this role, you must possess exceptional communication and presentation skills, as evidenced by technical publications, presentations, trainings, and executive briefings. Your ability to address SOC design challenges, guide teams towards milestones, and communicate progress effectively to upper management will be crucial for success. Key Responsibilities include defining product features, driving technical specifications for SoC and IP blocks, collaborating with IP/Domain architects to resolve technical issues, and providing technical direction to execution teams. You will also be responsible for system optimization, area and floorplan refinement, verification test plan reviews, bug resolution, and performance/power verification sign-offs. Preferred Experience for this role includes a strong foundation in Systems & SoC architecture, expertise in CPU or Networking, memory sub-systems, power management, and low power design. Excellent communication, management, and collaborative skills are essential, along with the ability to work effectively with diverse teams across different geographies. Academic Credentials preferred for this position include a Bachelor's or Master's degree in a related discipline. Join AMD to be a part of a team that drives innovation and makes a positive impact on the world.,

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. About The Role As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Additional About The Role Additional About The Role Job Role * Work with multiple SOC Design teams to rollout robust Logic Synthesis, UPF synthesis, QoR optimization and netlist Signoff flows* Provide implementation flows support and issue debugging services to SOC design teams across various site* Develop and maintain 3rd party tool integration and product enhancement routines * Should lead implementation flow development effort independently by working closely with design team and EDA vendors * Should drive new tool evaluation, methodology refinement for PPA optimization Skill Set * Proficiency in Python/Tcl * Familiar with Synthesis tools (Fusion Compiler/Genus), * Fair knowledge in LEC, LP signoff tools* Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking* Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus* Should be sincere, dedicated and willing to take up new challenges Experience 13+ years of experience in RTL,UPF & Physical aware Synthesis for cutting edge technology nodes, logic equivalence checking, Scripting and Netlist Timing Signoff Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. As a design verification engineer you will work with a fast paced Integrated Wireless Technology (IEEE 802.11) team, with various wireless technologies embedded into an ARM based SOC infrastructure. You will be responsible for developing HW blocks (IP design), conduct High/Mid/Low level Design review and delivery IP to Subsystem team for making complex SoCs. You will be a critical part of the WLAN subsystem, contribute to IP design, sign-off the core to the SOC design team. Skills/Experience: - 6-15 years experience in Digital Design with a leading chipset company - Decent knowledge in Wireless connectivity technologiesIEEE 802.11 a/b/g/n/ac/ax/be - Knowledge in SoC architecture, including CPUs (preferably ARM), communications peripherals, multi-domain clocking, bus & interconnect structures, and power management - Strong fundamentals in one or few of these domain areas - Wireless and Mobile communications, Information theory, Coding theory, Signal processing - Strong knowledge on fixed-point implementation Truncation/Rounding/Saturation concepts - Strong knowledge on Digital communication engines viz., Demodulator, Deinterleaver, Viterbi/Turbo Decoders, Sigma-Delta modulation, Base band filters, FFT etc. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Bachelors /Masters degree in Engineering Relevant experience of 6+yrs in any of the mentioned domain - Verification/ Emulation/ Validation Verification: Strong knowledge of digital design and SOC architecture. Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C Experience in HDL such as Verilog Knowledge of ARM/DSP CPU architecture, High Speed Peripherals like USB2/3, PCIE or Audio/Multimedia Familiarity with Power-aware Verification, GLS, Test vector generation is a plus Exposure to Version managers like Clearcase/perforce FPGA Emulation : Familiarity with Verilog/Vhdl and General Digital Logic Design concepts Knowledge of system-level architecture including buses like ARM processor bringup, AXI/AHB, bridges, memory controllers such as DDR/Nand. Knowledge of peripheral emulation like PCIE/USB is a plus. Strong working knowledge of UNIX environment and scripting languages such as Perl or shell Working knowledge XILINX Virtex FPGA architecture and experience with ISE tool flow Pre/Post silicon Validation: ARM based System-On-Chip Pre-Silicon emulation and Post-Silicon ASIC Validation experience related to board bring up and debug. Perform system level validation and debug Debug experience with Lauterbach Trace32 environment. Test equipment like Logic analyzer, Oscilloscope and Protocol analyzers. Embedded software development of low level hardware drivers in C language. Working experience related to one or more of the following is required. ARM/DSP Processors/USB/PCIE, Ethernet Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: 3 to 15 years of work experience in ASIC/SoC Design Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Experience creating padring and working with the chip level floorplan team is an added advantage. Excellent oral and written communications skills Proactive, creative, curious, motivated to learn and contribute with good collaboration skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications 2-9 years of experience in SoC design Educational Requirements2+ years of experience with a Bachelors/ Masters degree in Electrical engineering Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail myhr.support@qualcomm.com or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

We are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with aminimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans. Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse controllers, test clocking strategy, chip I/O test strategy and HSIO test strategy. Define JTAG TAP, boundary scan, I/O Test JTAG access, IEEE1687 iJTAG network and instrument design and implementation. Define the Test Interface for each of the P&R IP blocks for Scan, MBIST and other test interfaces. Define hierarchical block isolation, Test clocking and On Chip Clock controllers and reset methodology. Define scan and MBIST timing at the top level and block level timing. Analyse block level RTL or gates to ensure that scalability and coverage is satisfied as per the design goals. Ensure that DFT is provided to fix the DFT violations to ensure that the design goals are meet. Analyse compression requirements for each of the blocks, define Intest and Extest compression requirements and define the requirements for compression engines. Synthesize compression engines for each of the blocks. Create the collaterals for compression for the IPs. Block level scan insertion as well as development of the scan wrappers for the blocks. Do scan insertion on the blocks, analyse scan DRC, implement DFT fixes. Create scan protocol files for designs, create scan inserted netlist, create scan definitions as well as scan definition files for PD. Perform ATPG on the scan inserted netlist, analyse DRC and coverage violations. Deep knowledge of different scan models Stuck-at, transition test, path-delay, bridging, cell aware, small-delay transition, IDDQ test etc. Ability to analyse coverage for each of the model types. Running GLS with or without timing for the scan vectors. Ability to debug the failures and working with timing and PD teams to fix the timing issues. Understanding of pattern delivery to the post-silicon test engineering teams. Delivering to the Test engineering the Test pin muxing and other full chip requirements for the Test Engineering Team. Understanding tester requirements and delivering the patterns in the formats that the tester teams needs. Implement pattern retargeting. Create grey box models for blocks. Coverage analysis of full chip consolidating Intest and Extest patterns. Knowledge of Top level scan architecture and creating flow to create pattern retargeting. Knowledge of Streaming Scan Network and other Top level scan pin sharing and implementing the block to top level pattern generation for this flow. Implementing Memory Testing and MBIST. Knowledge of Memory defect models and test algorithms. Knowledge of memory bit mapping and redundancy analysis. Implementing memory repair and fuse sharing among various memory. Knowledge of LogicBIST with Test point insertion, X-blocking. Full chip DFT delivery for tapeout including but not limited to DFT netlist verification, pattern delivery, Tester requirements. Debug DFT patterns post silicon, ability to analyse chain test patterns for failures, scan pattern failures. Analyse MBIST pattern failures, yield and repair debug. Ability to perform volume diagnostics on the parts to isolate and improve the patterns. Requirements Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. OR masters degree in computer science, Electrical/Electronics Engineering, or related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design for Test. Expertise in DFT tools and flows in scan intertion, ATPG, GLS simulation, diagnosis flows. Prior experience working on IP level and SOC level DFT projects. Proficient in DFT tools from Siemens (Tessent), Synopsys DFTmax, Tetramax, Spyglass DFT advisor, Genius DFT, Modus, VCS, Xcelium etc. Worked in full chip design or complex IP delivery in the area of DFT. Experience in post silicon debug, diagnosis and yield enhancements is a plus.

Job Overview We are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs. Job Description Lead and manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans. Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR and HBM Conduct Gate-level simulations, and power-aware verification using Xprop and UPF.Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams. Analyze and implement System Verilog assertions and coverage (code, toggle, functional). Provide mentorship and technical guidance to junior verification engineers.Manage and lead a dynamic team of verification engineers, fostering a collaborative and innovative work environment. Ensure verification signoff criteria are met and documentation is comprehensive.Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines. Adhere to quality standards, implement good test practices, and contribute to the continuous improvement of verification methodologies. Experience with verification tools from Synopsys and Cadence, including VCS and Xsim. Integration of third-party VIPs (Verification IP) from Synopsys and Cadence. Qualifications Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. ORMasters degree in computer science, Electrical/Electronics Engineering, or related field. ORPhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design Verification. Expertise in UVM (Universal Verification Methodology) and System Verilog. Prior experience working on IP level and SOC level verification projects. Proficient in verification tools such as VCS, Xsim, waveform analyzers, and third-party VIP integration (e.g., Synopsys VIPs and Cadence VIPs). Hands-on experience with UFS (Universal Flash Storage), Ethernet, PCIe, CXL, MIPI protocols.Solid understanding of low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols. Experience in DDR, HBM, Gate-level simulations, and power-aware verification using Xprop and UPF. Proficiency in scripting languages such as shell, Makefile, and Perl. Strong understanding of processor-based SOC verification, including native, Verilog, System Verilog, and UVM mixed environment. C-System Verilog handshake and writing C test cases for bootup verification. Excellent problem-solving, analytical, and debugging skills.

Qualcomm India Private Limited is looking for a Hardware Engineer with over 12 years of experience in SoC design. You should have a strong understanding of AMBA protocols such as AXI, AHB, and APB, as well as SoC clocking, reset, debug architecture, and peripherals like USB, PCIE, and SDCC. Knowledge of memory controller designs and microprocessors would be an added advantage. In this role, you will be responsible for constraint development and timing closure, working closely with SoC verification and validation teams for pre/post Silicon debug. Hands-on experience in Low power SoC design is required, along with expertise in Synthesis and understanding of timing concepts for ASIC. You should also have experience in Multi Clock designs and Asynchronous interface. Familiarity with tools in ASIC development such as Lint, CDC, Design compiler, and Primetime is necessary. Minimum qualifications include a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 6+ years of Hardware Engineering experience, or a Master's degree in the same field with 5+ years of experience, or a PhD with 4+ years of experience. If you are an individual with a disability and need accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. For reasonable accommodations, you may contact disability-accommodations@qualcomm.com. Qualcomm expects all employees to adhere to applicable policies and procedures, including security and confidentiality requirements. Please note that Qualcomm's Careers Site is for individuals seeking jobs at Qualcomm. Staffing agencies and individuals represented by agencies are not authorized to use this site. Unsolicited submissions from agencies will not be accepted. For more information about this role, please contact Qualcomm Careers.,

THE ROLE: The ideal candidate will get to work on Verification of complex Analog Mixed Signal IPs (with significant Digital and Analog content) that are delivered to various AMD SoCs. KEY RESPONSIBILITIES: Verification of IP features : Feature Test plan creation, Verification of the IP in RTL, Gatesim and Analog Mixed Signal simulations. Create methodology-based (UVM) verification testbenches and components from scratch for various IP features. Quality deliverables through regressions Verification coverage:code-coverage, functional coverage, assertions, to achieve 100% verification completeness Reviews, and feedback to design/architecture teams. PREFERRED EXPERIENCE: Expertise in System Verilog, methodology based testbench architectures such as UVM, and System Verilog assertions Expertise in code and functional coverage, Excellent Problem solving and debugging skills. Excellent Communication skills Strong digital design knowledge, SoC design flow Knowledge on AMS designs (SERDES or Memory PHYs such as DDR, GDDR) and Mixed signal verification methodology is an added advantage. UPF based RTL low power verification Prior experience in working on IPs with mixed signal content will be helpful. Prior experience of technical leadership will be an asset. ACADEMIC CREDENTIALS: Bachelor or Masters degree in ECE/EEE desired with 15+ years exp

THE ROLE: We are looking foran adaptive, self-motivative design verification engineer to join our growing team. As a key contributor,you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. TheVerification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Develop/Maintain tests for functional verification and performance verification at the core level Build testbench components to support the next generation IP Maintain or improve current test libraries to support IP level testing Create hardware emulation build to verify the IP functionalperformance Maintain and improve current hardware emulation environment to speed up the runtime performance and improve the debug facility Provide technical support to other teams PREFERRED EXPERIENCE: Minimum 5 year of industry experience in IP/SOC level design verification Have worked upon atleast one full cycle of SoC Verification flow Strong SV/UVM, UVC, Scoreboards, Functional Coverage, SV assertions, C/C++ expertise Must have good communication skills and ability to work in a team environment. Strong debug expertise Experience in data path verification protocol like PCIe/CXL/AXI/SATA at SoC Level ACADEMIC CREDENTIALS: Bachelors orMastersdegree in computer engineering/Electrical Engineering

Key Responsibilities: Ensure issues are solved on time with quality. Lead complex debug efforts for internal Silicon findings to identify root cause and resolution. Manage and track technical issues, risks and priorities. Manage customer and executive communications, including program status, risks and opportunities. Publish debug program indicators to identify major roadblocks and drive changes to improve debug throughput. Evaluate at the end of every program milestone if the open issues are gating to go to the next milestone. Drive improvements to the debug process based on the program learnings. Preferred Skills: 12+?years or more of experience in validation roles involving debugging OS, FW, Silicon, and HW issues. Understanding of PC industry standard busses and their software stack, such as?PCIe, DDR, USB, Ethernet. Strong knowledge of X86 architecture, SoC design, memory, RAS & power management Extensive knowledge of system architecture, technical debug, and validation strategy Good understanding and experience in platform/ system level debug, Operating System, Device Drivers and System BIOS interactions. Excellent communication and coordination skills. Detailed oriented, highly organized, able to prioritize, and juggle multiple work streams to tight deadlines. Experience in Technical program management. A thorough understanding of industry standard technologies and their software stack. ACADEMIC CREDENTIALS: Bachelors orMaster'sdegree in electrical or computer engineering

THE ROLE: Technical leader responsible for System and Silicon Debug of AMD EPYC Server products. The successful candidate willwork as part of the post-silicon validation group; facilitating all aspects of debug and resolution for system level failures working with engineering teams across AMD. Candidate will be immersed in challenging work developing & executing debug strategy for optimal debug throughput on current product to meet project milestones at POR quality. The system debug lead will also help in driving improvements to current product and future debug methodology. The candidate should be able to work in a global environment while maintaining a synergetic culture. The Person: As a key contributor to the success of AMD's product, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry leading technologies to market. AsSystem Debug Lead you willbe responsible for post-Silicon debugin the next generation of AMD's flagship server CPU products. In this role you willfacilitate the debug efforts of a program to ensure the maximum debug throughput is achieved.The System debug lead will also help to drive improvements in the current product and future debug methodology working with?System Validation and Engineering teams and other stakeholders (System Architects, IP design, SoC, FW, SW, manufacturing). Key Responsibilities: Ensure issues are solved on time with quality. Lead complex debug efforts for internal Silicon findings to identify root cause and resolution. Manage and track technical issues, risks and priorities. Manage customer and executive communications, including program status, risks and opportunities. Publish debug program indicators to identify major roadblocks and drive changes to improve debug throughput. Evaluate at the end of every program milestone if the open issues are gating to go to the next milestone. Drive improvements to the debug process based on the program learnings. Preferred Skills: 15+?years or more of experience in validation roles involving debugging OS, FW, Silicon, and HW issues. Understanding of PC industry standard busses and their software stack, such as?PCIe, CXL. Strong knowledge of X86 architecture, SoC design, memory, RAS & power management Extensive knowledge of system architecture, technical debug, and validation strategy Good understanding and experience in platform/ system level debug, Operating System, Device Drivers and System BIOS interactions. Excellent communication and coordination skills. Detailed oriented, highly organized, able to prioritize, and juggle multiple work streams to tight deadlines. Experience in Technical program management. A thorough understanding of datacenter industry technologies and their software stack. Academic Credentials: Bachelors/Masters in Computer Engineering with 15+ years of applicable experience.

Role Responsibilities: Define and drive the implementation of physical design methodologies for advanced SoCs. Take ownership of one or more physical design partitions or top-level designs. Manage the timing and power consumption of designs, ensuring optimal performance and efficiency. Contribute to the development and refinement of design methodologies, libraries, and code review processes. Define physical design-related rule sets for functional design engineers to follow. Job Requirements: Bachelor's degree in Electrical Engineering or equivalent practical experience. 7 years of experience with advanced design techniques, including clock/voltage domain crossing, Design for Testing (DFT), and low-power designs. Experience with System on a Chip (SoC) design cycles. Experience in high-performance, high-frequency, and low-power designs.

Responsibilities: Develop power management architecture for ASICs, ensuring optimal performance under power and thermal constraints. Prototype and validate SoC power management systems across various design phases. Track and analyze power-mode specifications, measurements, and optimizations through different stages of design. Collaborate with software and architecture teams to build comprehensive system-level designs and methods. Job Requirements: Bachelor's degree in Electrical Engineering or equivalent practical experience. Experience in power management or post-silicon measurements and validation. Knowledge of Dynamic Voltage Frequency Scaling (DVFS), idle power management, and system mitigation techniques. Familiarity with the impact of software and architectural decisions on power and thermal behavior, including thermal mitigation and scheduling.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: As a Qualcomm Systems Engineer at Qualcomm India Private Limited, you will be at the forefront of technology innovation. Qualcomm is known for pushing the boundaries of what's achievable to drive digital transformation and create a smarter, more connected future. In this role, you will be responsible for researching, designing, developing, simulating, and validating systems-level software, hardware, architecture, algorithms, and solutions that pave the way for cutting-edge technology. You will collaborate with cross-functional teams on various projects including next-generation System-on-chip (SoC) for smartphones, tablets, automotive, machine-learning accelerators, and other product categories. Minimum Qualifications: To qualify for this position, you should hold a Bachelor's/Master's Degree in Electronics & Communication / Micro Electronics or a related field with at least 5 years of experience in Physical Design or a related field. Alternatively, a PhD in Electronics & Communication / Micro Electronics or a related field with a minimum of 2 years of experience in Physical Design or a related field is also acceptable. Job Overview: As a Systems Engineer at Qualcomm, you will collaborate with the Platform Architecture team to work on next-generation System-on-chip (SoC) for Compute, smartphones, IoT, and other product categories. Your responsibilities will include contributing to the architecture and microarchitecture of various subsystems and interfaces of the SoCs such as reset, boot, power management, security, access control, debug services, and various processing subsystems like CPU, DSP, GPU, and AI Accelerator subsystems. You will work closely with hardware and software teams to understand design requirements, specifications, and interface details, validate architecture/microarchitecture models, integrate models into the SoC platform, validate IP/System Level use cases, perform trade-offs analysis, and develop system-level architecture/micro-architecture. Additionally, you should have experience working with ARM-based SoC architectures and possess a deep understanding of computer architecture fundamentals. Key Responsibilities: - Be part of Qualcomm Platform Architecture Team - Collaborate with Hardware and Software teams - Validate architecture/microarchitecture models - Integrate models into the SoC platform - Perform trade-offs analysis - Develop system level architecture/micro-architecture - Work with cross-functional teams - Analyze power, performance, area trade-offs Desired Skills: - Good understanding of SoC Design & Physical Design Concepts - Proficiency in digital design, VLSI, computer architecture, HDL languages - Strong analytical and problem-solving skills - Experience with ARM architecture and Coresight architecture - Excellent communication and presentation skills - Self-motivated and strong inter-personal skills Areas Of Expertise: Candidates with expertise in Physical Design flow, VLSI flow, ARM and RISC-V Architecture, DSPs, CPUs, DDR, Interconnect, System Cache, QOS, Power, Boot, Debug, Security, and Access Control Architecture are encouraged to apply. Qualcomm is an equal opportunity employer and is committed to providing reasonable accommodations for individuals with disabilities. If you require an accommodation during the application/hiring process, you can reach out to disability-accommodations@qualcomm.com. Qualcomm expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. For more information about this role, please contact Qualcomm Careers.,