Staff Engineer - RTL Design

As an RTL Design Engineer at Alphawave Semi, you will play a crucial role in the advancement of digital technology by contributing to the next generation Chiplet designs. You will be involved in the complete ASIC development cycle, from concept to product, and work on cutting-edge technologies that power innovation in data-demanding industries. Your responsibilities will include microarchitecting and RTL Design of SoC SubSystem/IP blocks, developing UPF and running CLP checks, ensuring RTL quality checks, creating documentation for hardware blocks, and collaborating with various teams to ensure the successful tapeout of high-quality SoCs. To excel in this role, you should possess a Bachelor's or Master's degree in Electrical, Electronics and Communication, or Computer Science Engineering, along with 8+ years of experience in SoC architecture and full-chip design for multi-million gate SoCs. Your expertise should encompass the design convergence cycle, IP dependencies management, project milestone tracking, and experience in CPU, high-speed serial interfaces, or coherence/noncoherent NOC domains. Your skills in communication, collaboration, and leadership will be essential in working effectively in a fast-paced, distributed team environment. You should have a strong understanding of bus protocols, memory controllers, chip IO design, test plans, verification, synthesis, formal verification, timing closure, post-silicon debug, and decision-making under incomplete information. At Alphawave Semi, we offer a hybrid work environment and a comprehensive benefits package that includes competitive compensation, Restricted Stock Units (RSUs), provisions for advanced education, medical insurance, wellness benefits, educational assistance, advance loan assistance, and office lunch & snack facilities. We are committed to equal employment opportunity and welcome applicants from diverse backgrounds, providing accommodations during the recruitment process to ensure a fair and inclusive environment for all candidates.,