91 Upf Jobs

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience 3+ years of experience in RTL,UPF & Physical aware Synthesis for cutting edge technology nodes, logic equivalence checking, Scripting and Netlist Timing Signoff Proficiency in Python/Tcl * Familiar with Synthesis tools (Fusion Compiler/Genus), * Fair knowledge in LEC, LP signoff tools * Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking * Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus * Should be sincere, dedicated and willing to take up new challenges Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools. Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure. Experience in all aspects of timing closure for multi-clock domain designs. Should be familiar with MCMM synthesis and optimization. Should have good understanding of low-power design implementation using UPF. Experience with scripting language such as Perl/ Python, TCL. Experience with different power optimization flows or technique such as clock gating. Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation Should be able to handle ECOs and formal verification and maintain high quality matrix

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Qualifications: Bachelors or Masters degree from a top-tier institute. 6-11 years of experience in physical design from product-based companies. Experience: Proven experience in managing complex subsystems and small teams. Proficiency in synthesis, place and route (PnR), and sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations. Job : Expertise in meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems/System on Chips (SoCs), place and route, and IP integration. Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating. Familiarity with ASIC design flows and physical design methodologies. Strong understanding of circuit design, device physics, and deep sub-micron technology. Experience working on multiple technology nodes in advanced processes. Proficiency in automation to drive improvements in PPA.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Roles and Responsibilities o Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. o Work closely with design/verification teams within CPU to develop comprehensive test plan. o Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. o Verify power intent through use of methodologies like UPF. o Work closely with system architects, software teams and Soc team to validate system use cases. o Work closely with emulation team to enable verification on emulators and FPGA platforms. o Debug and triage failures in simulation, emulation and/or Silicon. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. o BE/BTech degree in CS/EE with 3+ years experience. o Experience in power management verification. o Implementation of assembly and C language embedded firmware. o Experience in C/C++, scripting languages, Verilog/system Verilog. o Strong understanding of power management features in CPUs and CPU based Socs. o Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred : o Good Understanding of CPU architectures and CPU micro-architectures. o In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture o Experience with advanced verification techniques such as formal and assertions is a plus o Knowledge and verification experience in DFT and structural debug concepts and methodologiesJTAG, IEEE1500, MBIST, scan dump, memory dump is a plus

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Job Responsibilities Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 2+ years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Minimum 3+ years of experience in PD Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Summary Position for 3-8 years of experience in design verification of complex Qualcomm propriety DSP/NPU IP DSP team is responsible for delivering high-performance DSP/NPU cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space, AI, Automotive and more. Qualcomm is one of the largest fabless semiconductor design companies in the world, generating over $35 Billion in annual revenues from chipsets and royalties from intellectual property. Job Responsibilities Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, power, post silicon and back-end teams. Implement and improve System Verilog/UVM Testbench Architecture. Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency. Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals. Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails and bugs. Complete all required verification activities at IP level and ensure high quality commercial success of our products. Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a daily basis. Responsible gate level simulation bring-up, gate level verification with timing simulations. Responsible for power aware RTL verification and gate level simulation. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Skillset/Experience 3-8 years experience in processor/ASIC design verification Solid background and understanding of Digital Design, Processor Architecture , Processor Verification and Power aware verification. Expertise in System Verilog Testbench Architecture and implementation. Experience in writing C based and assembly level testcases is preferred. Exposure to power aware implementation and verification using UPF is a plus. Experience with advanced verification techniques such as formal and assertions is a plus. Gate-Level Simulation and Debug "” 0-delay, timing annotated and power aware. Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence . Scripting/Automation Skills "” Perl, Python, Shell, Make file TCI . Solid analytical and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts. Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog is preferred. Experience in verification of Processor subsystems is preferred. Experience in creating validation suite and building automation. Should have excellent inter-personal and communication skills.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: General Summary: Bachelors /Masters degree in Engineering Relevant experience of 2-12 yrs in any of the mentioned domain - Design/Verification/ Implementation Will be working on cutting-edge Wireless Technology (IEEE 802.11) team. Strong fundamentals in core areasMicroarchitecture, Computer Arithmetic, Circuit Design, Process Technology Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Design You will be responsible for developing HW blocks (IP design), conduct High/Mid/Low level Design review and delivery IP to Subsystem team for making complex SoCs. You will be a critical part of the WLAN subsystem, contribute to IP design, sign-off the core to the SOC design team. Strong communication skills to work with design teams worldwide Verification Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C As a design verification engineer you will work on developing IPs catering to upcoming Wifi standards like 802.11bn and beyond. You will have opportunity to contribute to the life cycle of the technology right from IP specification, till productization/customer deployments, leveraging your verification, pre and post silicon debug expertise. Implementation Candidate will be responsible for next generation WLAN hardmacro implementation Extensive experience in Synthesis (DC or Genus), Formal Verification (LEC / Formality), Conformal Low Power, PTPX, Primetime, Conformal ECO Extensive experience in UPF based power intent and synthesis

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Roles and Responsibilities o Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. o Work closely with design/verification teams within CPU to develop comprehensive test plan. o Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. o Verify power intent through use of methodologies like UPF. o Work closely with system architects, software teams and Soc team to validate system use cases. o Work closely with emulation team to enable verification on emulators and FPGA platforms. o Debug and triage failures in simulation, emulation and/or Silicon. BE/BTech degree in CS/EE with 3+ years experience.o Experience in power management verification. o Implementation of assembly and C language embedded firmware. o Experience in C/C++, scripting languages, Verilog/system Verilog. o Strong understanding of power management features in CPUs and CPU based Socs. o Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred : o Good Understanding of CPU architectures and CPU micro-architectures. o In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture o Experience with advanced verification techniques such as formal and assertions is a plus o Knowledge and verification experience in DFT and structural debug concepts and methodologiesJTAG, IEEE1500, MBIST, scan dump, memory dump is a plus

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Responsibilities Defining chip and macro level power domains System Level Power Modeling Mixed signal power analysis Power Island/Power Gating/Power Isolation Structural Low power design of level shifter and isolation cell topology and associated rules Architectural analysis and development of digital power optimization logic/circuits/SW Work with Power Management IC developers for power grid planning Creating detailed architecture and implementation documents Education RequiredBachelor's, Computer Engineering and/or Electrical Engineering PreferredMaster's, Computer Engineering and/or Electrical Engineering Work with cross-functional teams on SoC Power and architecture for mobile SoC ASICs. Skills/Experience At least 4-12 years of experience are required in the following areas Low power intent concepts and languages (UPF or CPF) Power estimation and reduction tools (PowerArtist/PTPX,Calypto) Power dissipation and power savings techniques- Dynamic clock and voltage scaling Power analysis (Leakage and dynamic) and thermal impacts Power Software features for power optimization Voltage regulators including Buck and Low Drop out ASIC Power grids and PCB Power Distribution Networks Additional skills in the following areas are a plus: Mobile Baseband application processors chipset and power grid understanding UPF-based synthesis and implementation using Design Compiler Structural low power verification tools like CLP or MVRC Outstanding written and verbal communication skills Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

In this role, you will develop and direct the engineering organization for development and revision of new and existing products or services and oversees the different R&D engineering dimensions. Act as the interface between the global engineering organization and the local sites. Manage the development of new products and release, leading state-of-the-art development teams (SW, HW, test, information design) within a multi-site R&D environment, with strong dependencies towards external stakeholders like product managers, supply chain, quality and procurement. You have: Typically requires 12+ years extensive relevant experience and/or a graduate / postgraduate equivalent degree. PhD degree would normally be expected in R&D stream. Strategic thinking with experience in business management and leadership of large cross-functional units. Proven track record in delivering strong financial results in key projects Leadership, influencing, and facilitation skills. Highly organized with strong focus on driving results. Must be strong in C/C++ and data structures. Management experience across several functional areas or businesses. It would be nice if you also had: Protocol development preferably, wireless experience, such as development on SMF/UPF, GGSN, PGW/SGW is added advantage. Familiarity with IP network protocols. Familiarity with UNIX based and real-time operating systems. Experience in debugging and maintaining control plane software. Sustain and increase the high-performance of the Packet Core Engineering global software development organization, showing y-o-y improvements in quality, productivity, morale, customer satisfaction. Design and implementation of the functional modules for the Serving and PDN Gateway, 5G SMF and UPF. Unit testing of features developed on mobile gateways, maintenance of software with support and technical assistance. Mentor and train new team members. Anticipate internal and external business challenges and / or regulatory issues and drives process, product or service improvements that create competitive advantage. Combine profound professional expertise with a holistic sense for the business and commercial environment and understands how the job contributes to achieving the objectives of the business. Influence strategic decisions in the professional area through expertise, in turn impacting the performance of the sub-function to create competitive advantage. Solve highly complex problems and develops original and innovative solutions with broad impact on the business.

In this role, you will be responsible for the technical delivery of our Packet Core projects, ensuring seamless execution from start to finish. You will manage all technical aspects of the project, ensuring adherence to quality, risk, and time constraints outlined in the customer contract. Your responsibilities will span from delivery approach preparation through deployment, customer acceptance, and ongoing care. As the primary technical interface and first point of escalation for the customer project, you will be a key player in building strong relationships and ensuring customer satisfaction. We encourage you to apply and join our team of dedicated professionals who are committed to delivering exceptional results. You have: Bachelor's or master's degree in computer science, Software Engineering, or a related field. Around 16+ years of experience in Packet Core Projects Knowledge and Experience of Packet Core EquipmentMME, S/PGW, AMF, SMF, UPF Knowledge and Experience of Nokia Packet Core equipmentcMM, cMG, NRD Capable of understanding Technical Notes, Protocol Specs, Method of Procedure It would be nice if you also had: Linux knowledge is an advantage. Basic understanding ofProject Management skill is an advantage Responsible for Packet Core domain project delivery schedule creations Support to Project Manager in creating Project schedule and Resource Management plan Accountable for Project technical documents initiation, creation and delivery, according to customer and internal procedures, consult Project stakeholders with all technical questions related to CPC, managing of project technical risks Manage Packet Core project technical team on daily basics, including specific tasks assignment and control of their execution, coordinate engineers work according to customer demands and expectation Accountable and responsible for closure and follow up of all Tickets raised towards Salesforce/4LS/R&D Solution Architect is accountable for tickets consolidation, prioritization and escalation, coordination/communication with customer and other stake holders related to technical delivery. Responsible for reporting project weekly updates to management, care handover of Project, contribute to improvement (Delivery Quality) KPI by reviewing the need to raise Care case

Job description Must have skills. Payment Domain Expertise, MUST - Knowledge on MT and MX Message, Basics of SQL, and Java Specific skillset on MTS and UPF knowledge. Payment domain expertise, knowledge on MT and MX messages Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications. 1. Applies scientific methods to analyse and solve software engineering problems. 2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance. 3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers. 4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities. 5. The software engineer collaborates and acts as team player with other software engineers and stakeholders.

In this role, you will manage project technical team, including specific tasks assignment and control of their execution, coordinate engineers work according to customer demands and expectation, Schedule and facilitate regular Project technical meetings. Provides report about the status, existing issues, future plans according to responsibility area, Accountable for quality of all technical process and procedures implemented at the project, e.g. customer network interventionadministrative and technical preparations of such Interventions, including development of all required procedures and their rehearsal testing in labs, instructing intervention engineers, making decision about the results of Intervention execution. You have: Bachelor's or master's degree in computer science, Software Engineering, or a related field. Around 15+ years of experience in Packet Core Projects Knowledge or experience for Packet Core EquipmentMME, S/PGW, AMF, SMF, UPF Knowledge or experience for Nokia Packet Core equipmentcMM, cMG, NRD Capable of understanding Technical Notes, Protocol Specs, Method of Procedure It would be nice if you also had: Linux knowledge is an advantage Basic understanding ofProject Management skill is an advantage ComputerMS Office, Teams Create Packet Core domain project delivery schedule creation, Support to Project Manager in creation of Project schedule and Resource Management plan Project technical documents initiation, creation, and delivery, according to customer and internal procedures, CPC design documents delivery according to customer and project requirements. Technical project scope delivery, including network functions deployment, integration, upgrade, acceptance testing, system performance evaluation. Consult Project stakeholders with all technical questions related to CPC Define Software implementation strategy, including specific SW version for CPC Network Elements (NE), their installation sequence, considering dependency from other NEs of the Nokia solution. Define the requirement for new SW features development, required for project completion. Interworks with R&D and Product Managers to request those features. Define and implement new tools to increase project execution effectiveness, including automation tools, provides feedback toward tools developers.

In this role, you will manage Packet Core project technical team on daily basis, including specific task assignments and control of their execution, coordinate engineers work according to customer demands and expectations, schedule and facilitate regular Project technical meetings. Provides report about the status, existing issues, future plans according to responsibility area, Accountable for the quality of all technical processes and procedures implemented at the project, e.g. customer network interventionadministrative and technical preparations of such Interventions, including development of all required procedures and their rehearsal testing in labs, instructing intervention engineers, making decision about the results of Intervention execution. You have: Bachelor's or master's degree in computer science, Software Engineering, or a related field. Around 15+ years of experience in Packet Core Projects Knowledge and Experience for Packet Core EquipmentMME, S/PGW, AMF, SMF, UPF Knowledge or Experience for Nokia Packet Core equipmentcMM, cMG, NRD Capable of understanding Technical Notes, Protocol Specs, Method of Procedure It would be nice if you also had: Linux knowledge is an advantage Basic understanding ofProject Management skill is an advantage ComputerMS Office, Teams Create Packet Core domain project delivery schedule creation, Support Project Manager in creation of Project schedule and Resource Management plan Project technical documents initiation, creation, and delivery, according to customer and internal procedures, CPC design documents delivery according to customer and project requirements. CPC technical project scope delivery, including network functions deployment, integration, upgrade, acceptance testing, system performance evaluation. Consult Project stakeholders with all technical questions related to CPC Define CPC SW implementation strategy, including specific SW version for CPC Network Elements (NE), their installation sequence, considering dependency from other NEs of the Nokia solution. Define the requirement for new Software features development, required for project completion. Interwork with R&D and Product Managers to request those features. Define and implement new tools to increase project execution effectiveness, including automation tools, provide feedback toward tools developers.

Skill: RTL design skills using verilog, SV, PCIe, CXL, ARM subsystem, SATA, DDRx etc, synthesis and timing closure , low power design flow, partition and upf creation. unit level testing and DFT concepts

Responsibilities: SoC integration/scenario/performance verification including CHI, DDRx/LPDDRx, and AI accelerator blocks in RTL. Develop test plans, SystemVerilog/Verilog testbenches, and C-based embedded tests. Collaborate with cross-functional teams architecture, design, performance, silicon validation, FPGA, and board teams. Plan, track and report verification tasks to management. Skills & Experience Required: Strong knowledge of Verilog/SystemVerilog HDL. Hands-on experience in SoC verification using embedded C/C++/assembly (ARM preferred). Experience in UVM/OVM, emulation, formal verification, UPF/Power-aware verification. Expertise in GLS, DFT/DFD, CDC (Clock Domain Crossing). Familiar with ARM SoC boot flows, cache coherency, SoC verification flow & strategy. Scripting experience in Python, Perl, Tcl, Shell. Excellent debugging and problem-solving skills.

Role & responsibilities Physical Design Engineer (PD/STA/Synthesis) Must-Haves: •Tools: Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime for STA •Flow Experience: •Floorplanning •Power planning •Placement •Clock Tree Synthesis (CTS) •Routing •Physical Verification (DRC/LVS) •Timing Closure •Knowledge of: •Low-power design (UPF/CPF) •ECOs •IR Drop, EM Analysis •STA constraints and timing analysis Nice-to-Haves: •Experience with block-level and/or full-chip PD •Familiarity with scripting (Tcl, Perl, Python)

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a passionate and highly skilled engineer with a deep understanding of digital implementation and logic equivalence checking and a strong desire to lead product validation efforts Your exceptional debugging skills and proficiency in software and scripting languages such as Perl, Tcl, and Python set you apart With a keen eye for detail, you maintain high standards of product quality and excel in communication and leadership roles You thrive in collaborative environments, working closely with cross-functional teams to develop and execute comprehensive validation plans Your analytical mindset allows you to perform in-depth root cause analysis and proactively address potential issues, ensuring the readiness of products for customer deployment You are an experienced professional with a b-tech or m-tech degree and a minimum of 6-8 years of related experience, ready to make a significant impact on our Formality tool, What Youll Be Doing: Execute and lead product validation of Synopsys's Formality tool by understanding requirements specifications, functional specifications, and customer use cases Lead a team of 5 or more product validation engineers Collaborate with cross-functional teams such as R&D, Product Engineering to develop, implement, and execute comprehensive validation plans based on our technical roadmap and specifications Define and manage scope, schedule, and risks associated with the validation objectives Perform in-depth customer incoming root cause analysis to understand the product weak areas and hot spots and execute proactive testing to improving product quality Use product expertise to provide technical recommendations, identify, diagnose and troubleshoot issues, and propose solutions to ensure quality and readiness of the product/solution for customer deployment Analyze product validation data to identify trends, discrepancies, and areas for improvement Prepare detailed validation reports for presenting to multi-functional teams and management The Impact You Will Have: Ensuring the quality and reliability of Synopsys's Formality product to keep standing out as a leading LEC solution in the industry Enabling timely and successful deployment of high-performance designs for our customers Contributing to the innovation and advancement of LEC and product validation technologies Strengthening collaboration and communication across R&D, Product Engineering, and Field teams What Youll Need: Tech or equivalent and a minimum of 5 years of related experience or M Self-motivated individual with deep domain knowledge in Logic Equivalence Checking (LEC) including expertise in debugging and resolving LEC failures using Synopsyss Formality tool Experience and sound knowledge in design implementation including datapath optimization, CTS, UPF and DFT instrumentation Sound knowledge in HDL including SystemVerilog and VHDL Exceptional debugging skills Proficiency in software and scripting skills (Perl, Tcl, Python) Experience in cross-functional teamwork, driving projects and mentoring Who You Are: Details oriented with a focus on maintaining high standards of product quality Excellent communication, organizational, risk assessment/mitigation, and time management skills Ability to abstract up and communicate meaningful conclusions and define next steps Excellent communication and leadership skills The Team Youll Be A Part Of: You will be part of a dedicated product validation team for Formality, working closely with R&D, product engineering and field applications engineering teams Your team focuses on ensuring the high quality of new releases and features of Formality tool, enabling customers to accurately and timely validate their high-performance designs Together, you will tackle complex technical challenges and drive continuous improvement in our product validation processes, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process, Inclusion and Diversity are important to us Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability,

Your exceptional debugging skills and proficiency in software and scripting languages such as Perl, Tcl, and Python set you apart With a keen eye for detail, you maintain high standards of product quality and excel in communication and leadership roles You thrive in collaborative environments, working closely with cross-functional teams to develop and execute comprehensive validation plans Your analytical mindset allows you to perform in-depth root cause analysis and proactively address potential issues, ensuring the readiness of products for customer deployment You are an experienced professional with a b-tech or m-tech degree and a minimum of 6-8 years of related experience, ready to make a significant impact on our Formality tool, What Youll Be Doing: Execute and lead product validation of Synopsys's Formality tool by understanding requirements specifications, functional specifications, and customer use cases Lead a team of 5 or more product validation engineers Collaborate with cross-functional teams such as R&D, Product Engineering to develop, implement, and execute comprehensive validation plans based on our technical roadmap and specifications Define and manage scope, schedule, and risks associated with the validation objectives Perform in-depth customer incoming root cause analysis to understand the product weak areas and hot spots and execute proactive testing to improving product quality Use product expertise to provide technical recommendations, identify, diagnose and troubleshoot issues, and propose solutions to ensure quality and readiness of the product/solution for customer deployment Analyze product validation data to identify trends, discrepancies, and areas for improvement Prepare detailed validation reports for presenting to multi-functional teams and management The Impact You Will Have: Ensuring the quality and reliability of Synopsys's Formality product to keep standing out as a leading LEC solution in the industry Enabling timely and successful deployment of high-performance designs for our customers Contributing to the innovation and advancement of LEC and product validation technologies Strengthening collaboration and communication across R&D, Product Engineering, and Field teams What Youll Need: Tech or equivalent and a minimum of 8 years of related experience or M Self-motivated individual with deep domain knowledge in Logic Equivalence Checking (LEC) including expertise in debugging and resolving LEC failures using Synopsyss Formality tool Experience and sound knowledge in design implementation including datapath optimization, CTS, UPF and DFT instrumentation Sound knowledge in HDL including SystemVerilog and VHDL Exceptional debugging skills Proficiency in software and scripting skills (Perl, Tcl, Python) Experience in cross-functional teamwork, driving projects and mentoring Who You Are: Details oriented with a focus on maintaining high standards of product quality Excellent communication, organizational, risk assessment/mitigation, and time management skills Ability to abstract up and communicate meaningful conclusions and define next steps Excellent communication and leadership skills The Team Youll Be A Part Of: You will be part of a dedicated product validation team for Formality, working closely with R&D, product engineering and field applications engineering teams Your team focuses on ensuring the high quality of new releases and features of Formality tool, enabling customers to accurately and timely validate their high-performance designs Together, you will tackle complex technical challenges and drive continuous improvement in our product validation processes, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process, Inclusion and Diversity are important to us Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability,

What You ll Be Doing: Execute and lead product validation of Synopsyss Formality tool by understanding requirements specifications, functional specifications, and customer use cases Lead a team of 5 or more product validation engineers Collaborate with cross-functional teams such as R&D, Product Engineering to develop, implement, and execute comprehensive validation plans based on our technical roadmap and specifications Define and manage scope, schedule, and risks associated with the validation objectives Perform in-depth customer incoming root cause analysis to understand the product weak areas and hot spots and execute proactive testing to improving product quality Use product expertise to provide technical recommendations, identify, diagnose and troubleshoot issues, and propose solutions to ensure quality and readiness of the product/solution for customer deployment Analyze product validation data to identify trends, discrepancies, and areas for improvement Prepare detailed validation reports for presenting to multi-functional teams and management The Impact You Will Have: Ensuring the quality and reliability of Synopsyss Formality product to keep standing out as a leading LEC solution in the industry Enabling timely and successful deployment of high-performance designs for our customers Contributing to the innovation and advancement of LEC and product validation technologies Strengthening collaboration and communication across R&D, Product Engineering, and Field teams What You ll Need: B.Tech or equivalent and a minimum of 8 yearsof related experience or M.Tech or equivalent and a minimum of 6 years of related experience Self-motivated individual with deep domain knowledge in Logic Equivalence Checking (LEC) including expertise in debugging and resolving LEC failures using Synopsys s Formality tool Experience and sound knowledge in design implementation including datapath optimization, CTS, UPF and DFT instrumentation Sound knowledge in HDL including SystemVerilog and VHDL Exceptional debugging skills Proficiency in software and scripting skills (Perl, Tcl, Python) Experience in cross-functional teamwork, driving projects and mentoring Who You Are: Details oriented with a focus on maintaining high standards of product quality Excellent communication, organizational, risk assessment/mitigation, and time management skills Ability to abstract up and communicate meaningful conclusions and define next steps Excellent communication and leadership skills

Role & responsibilities Key Responsibilities : Lead and manage RTL design activities for complex ASICs, ensuring high performance and low power consumption. Integrating RTL components into System-on-Chip (SoC) designs Integrating RTL components into System-on-Chip (SoC) designs Architect and implement RTL for digital circuits (such as processors, communication systems, or custom IP cores). Mentor and guide junior RTL engineers in best practices for design, coding standards, and optimization techniques. Develop and refine RTL code in Verilog/System Verilog for ASIC development. Collaborate with cross-functional teams (Verification, Physical Design, and Software) to ensure successful integration of the ASIC design. Perform RTL design reviews, debugging, and optimization to meet design targets such as area, speed, and power. Work on creating micro-architectural specifications and ensure the design meets project requirements. Ensure designs are implemented with proper synchronization, timing constraints, and low power techniques. Participate in top-level design, integrating IP blocks, ensuring design consistency across subsystems. Drive the design flow from architecture and specifications through to implementation. Prepare and maintain technical documentation for designs and related processes. CDC, LINT and Integration expertise is expected. Required Skills & Experience : Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or related fields. 3-12 years of experience in RTL design for ASICs, with at least 3 years in a team lead role. Expertise in RTL design using Verilog or System Verilog. Solid understanding of digital design principles, including timing analysis, state machines, and pipelining. In-depth knowledge of ASIC design flow, from RTL to tape-out. Experience with EDA tools for synthesis, simulation, and timing analysis (e.g., Synopsys, Cadence). Strong debugging and problem-solving skills. Good knowledge on scripting (Python, Perl and Shell scripting) Knowledge of power, performance, and area (PPA) optimization techniques. Experience with designing for low-power, high-speed circuits is highly desirable. Excellent communication skills and the ability to work in a team environment. Preferred Skills : Experience with complex subsystems such as memory controllers, interconnects, or high-speed I/O. Prior experience working with large, cross-functional teams and managing design schedules. Experience with software tools for RTL analysis and optimization. Hands-on experience in leading ASIC projects from specification to production.

Summary Established in 2001, EnSilica is a publicly listed company (LON:ENSI), designing industry leading, application specific integrated circuit chips (ASIC), for customers ranging from start-ups to blue chip companies, in industries including: automotive, medical, space and mobile technology companies. With its head office on Milton Park, Oxfordshire, and other offices in Bristol, Sheffield, Brazil (Porto Alegre) and India (Bangalore), EnSilica currently employs more than 160 people. We are looking for a very experienced verification engineer who can not only strengthen the team through their technical expertise but also bring leadership and grow the verification business within EnSilica. You will have a good understanding of different methodologies, but particularly SystemVerilog and UVM. Faced with a new project, you will have the ability to quickly assimilate the verification challenge and help define an effective and pragmatic verification strategy and gain the support of the end-customer for the chosen approach. You will need to understand the importance of monitoring key metrics to assess progress and predict the end-point for the verification process. Responsibilities Verification specialist working on customer and internal projects often as the verification lead. Provide high-class verification support to a wide range of projects using a range of advanced verification techniques including constrained random, coverage driven, assertion-based and formal methods. You would also be responsible for the development of a comprehensive verification strategy and plan, along with the architecting and development of the complete test environment. Active participation in the verification community to drive the introduction of new and effective techniques within our business to help solve the verification challenges faced by our customers. Close working with our customers to build a strong relationship that results in repeat business. Education / Key Skills / Experience BE/ME in Electronics /Computer Science 1 group University. 15+ years experience in industry working on a variety of verification projects. Extensive knowledge of verification methodologies particularly UVM and SystemVerilog. Strong experience in the specification and implementation of verification infrastructures, test benches, models, assertions and functional tests in Verilog and SystemVerilog. Familiarity with constrained random verification methodologies, code coverage analysis and running regression tests. Strong VHDL/Verilog RTL. Very good understanding of modern verification flows and methodologies and able to influence the EnSilica one toward continuous improvement Ideally you will be familiar with both Mentor Questa and Cadence Incisive tool and ideally some exposure to low power verification using UPF based flows A good understanding of functional safety and quality processes, to achieve ISO26262 or similar standards compliances will be considered as a strong plus Personality Excellent communication and interpersonal skills. Strong and effective presentation skills, able to operate at multiple levels including senior management. Self-motivated achiever who gains satisfaction from providing excellent customer service and has a can-do attitude. Happy to take ownership of problems and provide suitable solutions. Creative problem solving. Team player. Ability to work in a dynamic environment.

You will contribute as a skilled Packet Core Specialist expert responsible for one or more key functions like Fault, Configuration, Performance, and Security. You will work independently within global guidelines, solve complex problems, and contribute to process improvements. You will also mentor and advisor, take responsibility for high-risk procedures, and collaborate with internal and external stakeholders to ensure seamless delivery of MS services. You have: 9-12 years with a bachelors degree in Telecommunications, Network Engineering, Computer Science, or a related field. Proven experience in packet core network design and planning for mobile and broadband networks, including EPC and 5G Core technologies. Expertise in packet core network elements such as MME, SGW, PGW, UPF, PCRF, and their interworking in both 4G and 5G environments. Experience with network optimization, traffic modeling, and capacity planning tools. It would be nice if you also had: Good analytical and problem-solving skills, with the ability to diagnose and resolve complex network issues. Knowledge of cloud technologies and virtualization (e.g., NFV, SDN, cloud-native 5G) is a plus. Excellent communication skills and the ability to collaborate effectively with cross-functional teams. You will lead the design and planning of packet core network architectures, including EPC (Evolved Packet Core), 5G Core, and other related technologies, ensuring scalability, security, and performance. You will perform capacity planning for packet core elements (e.g., MME, SGW, PGW, UPF) and ensure efficient resource allocation and utilization. Optimize network design to accommodate traffic growth while meeting quality of service (QoS) requirements. You will Collaborate with the implementation and operations teams to integrate new packet core components and technologies into existing networks. Oversee the testing and validation of network configurations and integrations. You will utilize traffic modeling tools and simulations to forecast future demand on the packet core network and identify potential bottlenecks or performance issues. You will design and implement security measures for packet core networks, including encryption, firewalls, and access control mechanisms, to safeguard data and ensure compliance with industry standards and regulations. You will work with vendors to select appropriate hardware, software, and technologies for packet core network infrastructure. Manage vendor relationships and ensure that vendors meet performance and delivery expectations. You will monitor packet core network performance using network management and monitoring tools. Analyze performance data to troubleshoot issues and propose solutions to optimize the network.

In this role, you will manage a team of one of Solution Area and bring thought leadership in customer engagement. Candidate will also be responsible for quality delivery and delivery project KPI tracking and adhering, manage Nokia's Internal Stake holder engagements with solution capabilities from multiple sources and technologies, build understanding and preference for Nokia products and solutions by influencing regional team decisions and strategic direction, demonstrate significant operational as well as commercial knowledge of clients' business and uses this to build credibility as well as identify sales opportunities, define new & innovative delivery model and package integrated solutions not only limited to Nokia Net's portfolio Leads training, development. You have: Bachelor's or master's degree in computer science, Software Engineering, or a related field. Around 14+ years of experience in Packet Core Projects Knowledge or experience of Packet Core EquipmentMME, S/PGW, AMF, SMF, UPF Knowledge or experience of Nokia Packet Core equipmentcMM, cMG, NRD Understanding of Technical Notes, Protocol Specs, Method of Procedure It would be nice if you also had: Linux knowledge is an advantage Basic understanding ofProject Management skill is an advantage Work in several technology areas with intermediate to advanced skill level or with one technology area at an advanced skill level. Create implementation plan and technical infrastructure documents. Work according to the Systems Integration (SI) delivery process, create test strategy and test cases. Contribute to gather customer requirements, analysis, feature specification and requirement feasibility study, contribute to migration procedures. Contribute to knowledge documentation in various tools like Sharepoint, ShareInside, Yammer, ShareNet, discussion forums. Work autonomously and effectively in a mixed environment and uses best practices and knowledge of internal or external business issues to improve products or services. Use advanced analytical skills to solve complex problems or problems that do not have routine solutions and takes a new perspective. May lead projects with manageable risks and resource requirements or small teams, handles day-to-day staff management issues, including resource management and allocation of work.

General Summary: As a SoC Power & Architecture Engineer, you will collaborate with cross-functional teams to develop and optimize power architecture for mobile SoC ASICs. Your expertise will drive low-power design techniques and power management strategies that enhance chip efficiency and performance. Skills and Experience: Required (412 years): Low power intent concepts and languages (UPF or CPF) Power estimation and reduction tools (PowerArtist, PTPX, Calypto) Power dissipation and savings techniques, including dynamic clock and voltage scaling Power analysis (leakage and dynamic) and thermal impact evaluation Power software features for optimization Voltage regulators (Buck converters, Low Dropout regulators) ASIC power grids and PCB power distribution networks Preferred / Additional Skills: Mobile baseband application processor chipset and power grid knowledge UPF-based synthesis and implementation with Design Compiler Structural low power verification tools (CLP, MVRC) Excellent written and verbal communication skills Responsibilities: Define chip and macro-level power domains Conduct system-level power modeling and mixed-signal power analysis Design power islands, power gating, and power isolation techniques Develop structural low-power design elements such as level shifters and isolation cell topologies with associated design rules Perform architectural analysis and develop digital power optimization logic, circuits, and software Collaborate with Power Management IC developers for power grid planning Create detailed architecture and implementation documentation Education and Minimum Qualifications: Required: Bachelor's degree in Computer Engineering, Electrical Engineering, or related field with 3+ years of hardware engineering experience OR Master's degree with 2+ years of hardware engineering experience OR PhD with 1+ year of hardware engineering experience Preferred: Master's degree in Computer Engineering or Electrical Engineering