234 Formal Verification Jobs

As a Formal Verification Engineer at our company, you will play a crucial role in ensuring the functional correctness of complex IP and SoC designs by developing and executing formal verification strategies. Your responsibilities will include: - Defining and implementing formal verification strategies and plans. - Developing formal properties and assertions for critical design blocks. - Applying formal techniques such as property checking, sequential equivalence checking, and formal coverage. - Analyzing formal results, identifying unreachable or vacuous properties, and refining models. - Collaborating closely with RTL designers, DV engineers, and architects. - Integrating formal into the overall verification methodology and sign-off. - Documenting and presenting formal verification methodologies, assumptions, and results. Qualifications required for this role include: - 4+ years of experience in formal verification using industry tools (e.g., JasperGold, VC Formal, Questa Formal, OneSpin). - Strong knowledge of SystemVerilog Assertions (SVA) and formal property specification. - Solid understanding of digital design concepts and RTL coding in Verilog/SystemVerilog. - Familiarity with formal coverage metrics and convergence techniques. - Experience in debugging complex design bugs using formal tools. - Ability to abstract and model designs or protocols at different levels. Desirable skills that would be a plus for this role include: - Familiarity with safety-critical designs (ISO 26262, DO-254). - Knowledge of common protocols such as AXI, AHB, PCIe, Ethernet, etc. - Exposure to sequential equivalence checking and abstraction modeling. - Understanding of simulation-based verification and integration with formal. - Proficiency in scripting (Python, Perl, or TCL) for automation. If you are interested in this opportunity, please share your CV to sharmila.b@acldigital.com.,

As an experienced Functional Formal Verification Engineer, you will be leading the formal verification efforts for complex digital designs. You will play a critical role in ensuring the quality and reliability of our digital designs. **Key Responsibilities:** - Lead complete formal verification for single or multiple design blocks and IPs, including developing and implementing formal verification strategies and test plans. - Create comprehensive formal verification test plans and specifications to ensure thorough coverage of design functionality. - Prove design properties, identify bugs, and collaborate with design teams to improve micro-architectures and ensure design correctness. - Craft innovative solutions for verifying complex design architectures, including developing re-usable and optimized formal models and verification code bases. - Mentor junior team members and provide technical leadership in formal verification methodologies, including training and guidance on industry-standard tools and techniques. - Collaborate with cross-functional teams, including design and verification, to ensure seamless integration of formal verification into the overall verification flow. **Qualifications:** - Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or a related field. - 10+ years of experience in formal verification of complex IP/SubSystem/SoCs, with a strong understanding of digital logic design and verification techniques. - Expertise in formal verification tools and property specification languages (e.g., SVA, PSL), as well as proficiency in HDLs such as System Verilog, Verilog, or VHDL. - Experience with industry-standard EDA formal tools. - Experience with scripting languages (e.g., Python, Tcl, Perl) and programming languages such as C/C++/SystemC. - Excellent problem-solving and analytical skills, with the ability to debug complex issues and optimize verification performance. - Strong communication and interpersonal abilities, with experience working in a team environment and collaborating with cross-functional teams. - Proven track record in technical leadership and mentoring, with experience guiding junior engineers and contributing to the development of formal verification methodologies. The company is looking for someone with experience in CPU, GPU, or other complex digital architectures, including knowledge of industry-standard protocols (e.g., AXI, CHI, PCIe). Familiarity with UVM methodology and/or other simulation-based verification methodologies is preferred. Additionally, expertise in Jasper or VC Formal products is highly desirable.,

Overview UVM Based verificaton at SOC level Responsibilities As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Requirements Bachelor’s/ Master’s degree or higher in EEE/ECE 5+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platformsUVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with ARM/RISCV Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skills

Required Skills Experience in Logic design / RTL coding is a must. Experience is SoC design and integration for complex SoCs is a must. Experience in Verilog/System-Verilog is a must. Experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint and CDC. Experience in Synthesis / Understanding of timing concepts is a plus. Experience in ECO fixes and formal verification. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture. Excellent oral and written communications skills. Proactive, creative, curious, motivated to learn and contribute with good collaboration skills

We require 1.DV-Formal verification with must Jasper Gold Exp Exp : 5+ Location : BLR/Pune 2. DV- WIFI/ Wireless / BT with Test case Dev/debugging Exp : 5+ Location : BLR/Pune 3. DV- PCIE with Test case Dev/debugging Exp : 5+ Location : BLR/Pune

ASIC Design Verification Engineer - ( SystemVerilog, UVM test bench, C/C++ , Perl/Python scripting, (VCS, DVE, Verdi), TCL/Shell scripting) | 10+ years Meet the Team Join our dynamic front-end design team at Cisco Silicon One, where innovation meets innovative technology! As part of the heart of silicon development at Cisco, you'll engage in every facet of chip design, from architecture to validation, using the latest silicon technologies to create groundbreaking devices. Cisco Silicon One is the only unified silicon architecture that empowers customers to deploy top-tier silicon across diverse applications, from top-of-rack switches to expansive data centres. Be a part of shaping Cisco's progressive solutions by designing and testing advanced ASICs that integrate networking, compute, and storage into a single system. With tightly integrated hardware and software solutions, you'll gain exposure to all aspects of our systems, using the latest technology. We're seeking a dedicated ASIC engineer with a proven track record in high-performance products, ready to make a significant impact in the industry. Join us and push the boundaries of what's possible! Your Impact Develop test plans, cover points, and qualification tests Perform end-to-end verification of design blocks and top-level Build and maintain block, cluster, and top-level DV environment infrastructure Construct testbenches components like scoreboard, agents, sequencers, and monitors Write tests, debug regressions, and drive to module verification closure Collaborate with designers and verification engineers for cross-block verification Upgrade configuration/reset sequences (APIs) Develop environment and tests for emulation Ensure complete verification coverage through code, functional coverage, and gate level simulations Support post-silicon bring-up and optimize integration and performance Minimum Qualifications Bachelors Degree in EE, CE, or other related fields with 6+ years or Masters Degree with 4+ years of ASIC design or verification experience Experience in developing verification environment for complex blocks from design specifications document Proficient in verifying complex blocks and/or clusters for ASIC using UVM/System Verilog. Scripting experience with Perl, Python, TCL, shell scripts. Preferred Qualifications Experience in Data center/ Hyper scaler /AI Networking technologies Proven experience meeting and delivering project milestones and deadlines. Ability to communicate technical concepts to audiences spanning executives to junior engineers to customers. Demonstrated ability in troubleshooting and debugging. Experience with Emulation and Formal Verification tools is a plus.

You will be responsible for understanding and reviewing design specifications to develop verification strategies, test plans, and coverage plans. Your role will involve creating constrained random verification environments, verification components, and writing tests, sequences, functional coverage, and assertions to achieve verification goals. Additionally, you will be developing C-based test cases for SOC verification. To excel in this role, you must have a strong background in functional verification fundamentals, environment planning, test plan generation, and environment development. Experience with System Verilog and UVM-based functional verification environment development is essential. Proficiency in verilog, VHDL, C, C++, Perl, and Python is required. Expertise in AMBA protocols (AXI/AHB/APB) and familiarity with protocols such as USB, PCIE, Ethernet, DDR, LPDDR, as well as version control and load sharing software are necessary. Desirable skills include prior experience with Cadence tools, ARM/CPU architectures familiarity, assembly language programming experience, knowledge of protocols like UART, I2C, SPI, JTAG, embedded C code development and debug, and formal verification experience. Excellent vocabulary, communication, organizational, planning, and presentation skills are essential for this role. You should be able to work independently, deliver high-quality results in a fast-paced environment, and be open to learning new methodologies, languages, and protocols. A self-motivated approach, willingness to take on additional responsibilities, and a commitment to personal development are key traits required to contribute to the team's success.,

You are seeking Senior DV engineers for BLR location with 6+ years of experience in SoC Verification. As a Senior DV engineer, your responsibilities will include developing Detailed Documentation for Verification Strategy and Test Plan for IP, Subsystem, and SoC. You will be involved in Directed and Random Verification at IP, Subsystem, and SoC Level for complex ARM / RISC-V processor based MCU, MPU products, Mixed Signal SoCs, Processors, Memory Subsystems, Connectivity Platforms, Analog, Security Acceleration, General Peripherals. Additionally, you will perform Functional and Code Coverage Analysis. To qualify for this position, you should have 6 to 15 years of experience in SoC Verification and expertise in Verilog, System Verilog, UVM, Constrained Random Verification, Formal Verification, Mixed Signal Verification, Post-Layout Gate Level Simulations, Code Coverage, and Functional Coverage analysis. You must also possess strong expertise in DDR, LPDDR, Pcie, Ethernet, USB Protocols (Any One). Strong debug and analytical capabilities, as well as in-depth understanding of SoC Design Flow, RTL Implementation, and Analog Circuit models, are essential for this role. Soft skills required for this position include strong analytical, problem-solving, and hands-on skills. You should be self-driven and thrive when facing open-ended tasks. A start-up mentality with a fast-paced, flexible, and team-oriented approach is desirable. Good written and verbal communication skills with great documentation skills are crucial. Flexibility to work with varied schedules and tolerance for ambiguity are also necessary attributes. If you meet the requirements and are interested in this opportunity, kindly share your updated profile with anand.arumugam@modernchipsolutions.com.,

Job Details Job Description: Come join Intel&aposs Design Development Group organization as an SOC Verification engineering focused on Design for Debug (DFD). As a member of the product team, you will work firsthand with multi-function teams/sites, implementing and validating state-of-the-art debug solutions appropriate for new and existing technology in the product. In this role you will be working as part of a pre-silicon validation team for future Intel SoCs or IPs, focusing on debug validation. You will be working with pre-silicon and post -silicon validation teams to improve debug features and tools suites. You will also work closely with post-silicon validation SW teams on debug tool validation and silicon enabling. You will be pioneering new debug tools and flows, reviewing and publishing architectural specs and supporting next-generation silicon enabling on system platforms. Your Responsibilities Will Include But Not Be Limited To Verification of Design for Debug features (e.g. low and high-bandwidth signal tracing and event triggering) using simulation, emulation, and/or FPGA. Creating test plans and tests for validating portions of a complex microarchitecture using written specs, RTL code and other tests as a guide. Learning Power Management, Memory and debug architecture and microarchitecture by debugging failures to the root cause. Developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design. Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models. Developing debugging tools and software. Qualifications Minimum Qualifications: Candidate must have either a BE /ME / MTech or MS in Electronics, VLSI, Microelectronics, Computer Science or Electrical Engineering with 4-10 Years of experience. Extensive Pre-silicon Track record of driving debug tools enabling and validation, improvements and getting them adopted by others. Proven record of working across verification teams to solve problems. Expert of HW and SW Interaction and debug to root cause. Experience working across verification, architecture, SW, and design teams to resolve debug issues. Minimum 4 years of experience with writing verification plans and testcases to implement those validation plans. Minimum 4years of SOC Verification or Functional verification. Minimum 2yrs experience with Programming languages/Scripting: C, Perl, Python, Verilog and UNIX or Linux. Minimum 2yrs experience with SOC Architecture. Must have 4yrs+ experience with SOC Verification or Functional Verification. Must have 4yrs+ experience with validation or testing experience, especially in a silicon design team. Preferred Qualifications Good to have 2yrs+ experience with industry standards such as JTAG, Tessent and Debug architecture. Good to have working experience on assertions, coverage and Formal verification Job Type Experienced Hire Shift Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel&aposs PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people&aposs potential - allowing each person use our products to focus, create and connect in ways that matter most to them. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. Show more Show less

Job Area :Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Masters degree in Electrical/Electronic Engineering from reputed institution 8+ years of experience in Physical Design/Implementation Minimum Requirements: Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills.

Job Summary We are seeking an experienced GLS Lead to drive gate level simulation activities, including power-aware GLS, formal verification, and MCP verification. The ideal candidate will lead a team of engineers, ensuring timely delivery of all verification projects and maintaining high quality standards. Key Responsibilities Lead and manage the GLS team, providing technical direction and mentorship. Plan, execute, and oversee gate level simulation (GLS) flows for complex SoC designs. Drive power-aware GLS and ensure coverage of low power verification scenarios. Oversee formal verification and MCP verification activities, ensuring completeness and correctness. Collaborate with design, DV, and other cross-functional teams to resolve issues and optimize verification strategies. Ensure all projects meet established timelines and quality benchmarks. Develop and maintain verification plans, schedules, and status reports. Continuously improve GLS methodologies and best practices. Provide regular updates to management and stakeholders. Required Qualifications Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 8+ years of experience in gate level simulation, power-aware verification, and formal verification. Proven experience leading verification teams and managing multiple projects. Strong understanding of SoC design, verification flows, and EDA tools (e.g., VCS, Questa, Verdi). Hands-on experience with UPF/CPF for power-aware verification. Excellent problem-solving, communication, and leadership skills. Preferred Qualifications Experience with MCP verification methodologies. Familiarity with scripting languages (Perl, Python, TCL). Prior experience in graphics or multimedia SoC verification. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. 5+ years of experience in physical design is mandatory for this position Physical Implementation activities for high performance Cores for 16/14/7/5nm or lower technologies, which includes all or some of the below. Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), Low Power verification, PDN, Timing Closure and / or power optimization Exposure to PD implementation of PPA critical cores. Exposure to timing convergence of high frequency data-path intensive Cores and advanced STA concepts. Able to handle Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes. Understanding of clocking architecture. Tcl/Python/Perl Scripting aware for small automation Strong problem-solving skills , good communication skills and good team player Collaborate with design, DFT and PNR teams and support issue resolutions wrt constraints validation, verification, STA, Physical design, etc.

Qualcomm India Private Limited is seeking a Hardware Engineer to join their Engineering Group, specifically focusing on Hardware Engineering. As a Hardware Engineer at Qualcomm, you will be at the forefront of technology innovation, contributing to the development of cutting-edge products that drive digital transformation and create a smarter, connected future. Your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other hardware components to ensure the successful launch of world-class products. To qualify for this role, you must have a Bachelor's degree, Master's degree, or PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field, along with several years of experience in Hardware Engineering. You should possess a strong background in RTL Design and Hardware Engineering, with expertise in RTL design tools such as Verilog, VHDL, and System Verilog. Additionally, familiarity with synthesis, formal verification, scripting languages (Pearl/Python/TCL), and debugging capabilities at simulation and Silicon environments is required. As a Hardware Engineer at Qualcomm, you will work collaboratively with cross-functional teams to research, design, and implement performance and power management strategies for product development. Your responsibilities will also involve designing low power/power management controller IP blocks, collaborating with technology/circuit design and verification/physical design teams, and integrating low power solutions into wireless SoC chips. Qualcomm is an equal opportunity employer and is committed to providing accommodations for individuals with disabilities throughout the application and hiring process. If you require accommodations, you can reach out to Qualcomm via email at disability-accommodations@qualcomm.com or by phone. Additionally, Qualcomm expects its employees to adhere to all applicable policies and procedures, including the protection of confidential information. Please note that Qualcomm does not accept unsolicited resumes or applications from staffing and recruiting agencies. If you have any inquiries about this Hardware Engineer role, you can contact Qualcomm Careers for more information.,

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 8+ years RTL Design/Hardware Engineering experience or related work experience. Strong Domain Knowledge on RTL design(Verilog/VHDL/System Verilog) , implementation, and integration, micro-architecture & designing cores and ASICs Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc Exposure in scripting (Pearl/Python/TCL) Strong debugging capabilities at simulation, emulation, and Silicon environments Collaborate closely with cross-functional teams to research, design and implement performance and power management strategy for product roadmap Knowledge on Designing low power/power management controller IP blocks including AVS (adaptive voltage scaling), ACD (adaptive clock distribution), on-chip sensor controller Work closely with technology/circuit design team to close IP block specification/requirement. Work closely with verification/physical design team to complete the IP design implementation Support SoC team to integrate low power / power management IP solution into wireless SoC chips and front-end design flows Work closely with system/software/test team to enable the low power feature in SoC products

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 8+ years RTL Design/Hardware Engineering experience or related work experience. Strong Domain Knowledge on RTL design(Verilog/VHDL/System Verilog) , implementation, and integration, micro-architecture & designing cores and ASICs Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc Exposure in scripting (Pearl/Python/TCL) Strong debugging capabilities at simulation, emulation, and Silicon environments Collaborate closely with cross-functional teams to research, design and implement performance and power management strategy for product roadmap Knowledge on Designing low power/power management controller IP blocks including AVS (adaptive voltage scaling), ACD (adaptive clock distribution), on-chip sensor controller Work closely with technology/circuit design team to close IP block specification/requirement. Work closely with verification/physical design team to complete the IP design implementation Support SoC team to integrate low power / power management IP solution into wireless SoC chips and front-end design flows Work closely with system/software/test team to enable the low power feature in SoC products

General Summary: Are you interested in working with a world-class CPU design team? Are you interested in the application of formal methods to the verification of application processors? In contributing to the development of the next generation of formal methodologies in this space? Qualcomm's CPU team has some of the best CPU architects and engineers on the planet, developing the processors that will power the future. Come and join us on this exciting adventure. Sharpen your formal verification skills to their fullest on some of the complex designs ever attempted. Roles and Responsibilities: Work with design team to understand design intent and bring up verification plans and schedules with an eye towards the end-to-end formalization of the refinement from architecture to micro-architecture Define formal verification architecture, develop test plans and build end-to-end formal sign-off environments for Qualcomm CPU components Engage in full-spectrum deployment of model-checking technology to hardware designs including property verification, math proofs, architectural modeling and validation amongst other cutting-edge application areas To be successful in this position you will need: BA/BS degree in CS/EE with 8+ years of practical experience in application of formal methods in hardware or software Strong model checking or theorem proving background/experience in verification of complex systems Experience in writing assertions and associated modeling code in Hardware Description Languages or in proving correctness of architectural specifications using formal methods Working familiarity with model checkers like Jaspergold and VC-Formal or theorem-proving tools such as ACL2 and HOL The ideal candidate will have the following experience: MS/PhD degree in CS/EE; 4+ years of practical experience Strong foundation in formal methods and in their application to hardware specifications and/or implementations Domain knowledge in one or more of these areas: Microprocessor architecture and micro-architecture, instruction set architecture, floating-point math, memory consistency, memory coherency, security architectures Strong software engineering skills with proven ability in automation and proficiency in at least one programming language (C++, Python, TCL etc.) Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Join the dynamic front-end design team at Cisco Silicon One and be a part of the heart of silicon development. Engage in every facet of chip design, from architecture to validation, utilizing the latest silicon technologies to create groundbreaking devices. Cisco Silicon One empowers customers to deploy top-tier silicon across diverse applications, shaping revolutionary solutions by designing and testing advanced ASICs that integrate networking, compute, and storage into a single system. Gain exposure to all aspects of our systems with tightly integrated hardware and software solutions. We are looking for a talented ASIC engineer with a proven track record in high-performance products to make a significant impact in the industry. Join us and push the boundaries of what's possible! As a diligent Design/SDC Engineer, you will work with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Collaborate with Front-end and Back-end teams to refine design and timing constraints for seamless physical design closure. Contribute to developing next-generation networking chips by overseeing full-chip SDCs and working with physical design and DFT teams to close full-chip timing in multiple timing modes. You may also have the option to do block-level RTL design or block or top-level IP integration. Develop efficient methodologies to promote block-level SDCs to full-chip and ensure correctness and quality of SDCs early in the design cycle. Review block-level SDCs, mentor RTL design owners on SDC development, and create full-chip clocking diagrams and related documentation. Minimum Qualifications: - Bachelor's Degree in Electrical or Computer Engineering with 7+ years of ASIC or related experience or Master's Degree in Electrical or Computer Engineering with 5+ years of ASIC or related experience - Experience with block/full chip SDC development in functional and test modes - Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus - Understanding of related digital design concepts (e.g., clocking and async boundaries) - Experience with synthesis tools (e.g., Synopsys DC/DCG/FC), Verilog/System Verilog programming Preferred Qualifications: - Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence) - Experience with Spyglass CDC and glitch analysis - Experience using Formal Verification: Synopsys Formality and Cadence LEC - Experience with scripting languages such as Python, Perl, or TCL Join Cisco, where every individual brings their unique skills and perspectives to power an inclusive future for all. Celebrate diversity, unlock potential, and experience continuous learning and development. Be a part of a community that fosters belonging, learns to be informed allies, and makes a difference through volunteer work. Cisco is the worldwide leader in technology that powers the internet, helping customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals. Take your next step towards a more inclusive future with us!,

Qualcomm India Private Limited is seeking a Hardware Engineer to join the Engineering Group, specifically in the Hardware Engineering department. As a Hardware Engineer, you will be responsible for understanding the Video Codec specifications for respective blocks, micro-architecting sub-block designs, coding, debugging functionalities for all respective blocks, and performing design optimizations for Power/Area/Timing/Performance. The ideal candidate should possess a strong DSP/Multimedia Domain Knowledge on Video Codecs/Computer Vision, along with experience in micro-architecting and designing complex datapath cores for ASICs/SoCs, including AI/ML cores for CV applications. Proficiency in RTL coding using Verilog/VHDL/system Verilog, familiarity with Synthesis and Formal Verification, simulation debugging with Verdi & log file, exposure in scripting, and knowledge of Linting, CDC, Low Power, etc., are highly desirable. In addition to technical skills, the successful candidate should be a good team player, capable of proactive interaction with verification engineers. Strong problem-solving skills, the ability to debug and resolve issues independently, and a commitment to continuous learning are essential for this role. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 2+ years of Hardware Engineering or related work experience, OR - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 1+ year of Hardware Engineering or related work experience, OR - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. For accommodation during the application/hiring process, individuals can contact Qualcomm via email at disability-accommodations@qualcomm.com or through Qualcomm's toll-free number. It is important for all employees at Qualcomm to adhere to applicable policies and procedures, including those related to security and the protection of confidential information. The company expects its employees to comply with these requirements within the permissible limits of applicable law. Please note that Qualcomm's Careers Site is exclusively for individuals seeking jobs at Qualcomm. Staffing and recruiting agencies, as well as individuals being represented by an agency, are not authorized to use this site for submissions. Unsolicited resumes or applications from agencies will not be accepted. For more information about this role, please contact Qualcomm Careers directly.,

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, re-defined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep-learning ignited modern AI - the next era of computing. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life's work, to amplify human imagination and intelligence. The ASIC Hardware Engineering team at NVIDIA is looking for a Distinguished Engineer in Formal Verification to work on some of the most complex verification challenges in advanced computing, graphics and networking chips. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. What you'll be doing: Serve as a key technical leader driving Formal Verification roadmap across multiple projects, defining critical metrics, gathering requirements and addressing complex technical challenges. Drive technical innovation and strategic collaborations to improve verification efficiency and effectiveness across CPU, GPU and SoC chips. Develop and drive adoption of new methodologies and best practices in Formal Verification. Make crucial technical decisions in ambiguous situations, managing risks and keeping commitments and deliverables on track. What we need to see: Deep expertise in Formal Verification with proven track record in taking on complex verification challenges in advanced CPU, GPU and SoC chips. Demonstrated success in leading complex projects to completion, showcasing the ability to influence and achieve results without direct authority in collaborative environments. B.Tech. or M.Tech. degree in Computer Science, Electrical Engineering or related field. At least 18 years of relevant experience. Ways to stand out from the crowd: Proficiency in scripting to automate tasks. Experience in using Generative AI to improve efficiency and accelerate workflows. Excellent analytical and problem-solving skills. Strong interpersonal and stakeholder management skills. With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us and, due to outstanding growth, our engineering teams are rapidly growing. If you are a creative and autonomous engineer with a real passion for technology, we want to hear from you. Make the choice, join our diverse team today! #LI-Hybrid

As a member of the Common Hardware Group (CHG) at Cisco, you will be responsible for delivering cutting-edge silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. Your role will involve designing networking hardware for a diverse range of clients, including Enterprises, Service Providers, the Public Sector, and Non-Profit Organizations worldwide. Cisco Silicon One is a revolutionary silicon architecture that offers customers the flexibility to deploy top-of-the-line silicon across various networking environments. Join our team to be a part of shaping Cisco's innovative solutions by contributing to the design, development, and testing of highly complex ASICs in the industry. You will collaborate closely with verification engineers, designers, and cross-functional teams to ensure the successful verification of ASICs throughout their lifecycle. Your impact will be significant as you contribute to the development of Cisco's groundbreaking data center solutions. Your responsibilities will include architecting block, cluster, and top-level DV environment infrastructure, developing DV infrastructure from scratch, maintaining and enhancing existing DV environments, and developing test plans and tests for qualifying designs at block and cluster level environments. Key responsibilities also involve ensuring complete verification coverage through the implementation and review of code and functional coverage, qualifying the design with Gate Level Simulations on netlist, supporting testing of design in emulation, and collaborating with designers, architects, and software teams to address and debug issues during post-silicon bring-up. To qualify for this role, you should hold a Bachelor's Degree in EE, CE, or a related field, along with at least 5 years of ASIC design verification experience. Proficiency in ASIC verification using UVM/System Verilog, verifying complex blocks and/or clusters for ASIC, building test benches from scratch, and scripting experience with Perl and/or Python is required. Preferred qualifications include experience with Forwarding logic/Parsers/P4, Veloce/Palladium/Zebu/HAPS, formal verification knowledge, and domain experience in protocols like PCIe, Ethernet, RDMA, and TCP. At Cisco, we value diversity, inclusion, and personal development. Our employees are encouraged to learn and grow at every stage of their careers. We celebrate individuality and focus on creating a culture of connection and collaboration. If you are passionate about technology and aspire to be part of a team that drives innovation in the tech industry, Cisco offers a supportive and inclusive environment where you can unleash your potential and make a difference. Join us at Cisco and be a part of our mission to power an inclusive future for all. Take the next step in your career and contribute to building a more connected and sustainable world with us.,

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive design optimizations to improve QoR. Block/Partition signoff closure for STA, PV, LEC, IR/EM, CLP very efficiently. Provide technical leadership and guidance to the physical design team, mentoring junior engineers and fostering a culture of excellence. Work closely with RTL design and DFT teams to understand design requirements and constraints, and drive successful tapout of designs. Support and Development of advanced physical design methodologies and flows for complex semiconductor designs. Requirements Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. 4+ years of experience in physical design of ASICs Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics for Synthesis, PnR, Signoff Closure. Extensive experience with timing closure techniques, power optimization. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Expertise in Synthesis that includes details understanding of RTL, Early PnR timing issues, Constraint issue, design issues. Experience in handling Partitions and blocks for size estimation, pin assignment, CTS. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration. Detailed Knowledge on Clocking methodology and various techniques to improve skew, latency, timing, power. Familiarity with low-power design techniques and methodologies, such as multi-voltage domains and power gating using UPF. Expertise in physical verification, including DRC, Antenna, LVS, PERC, and ERC checks. Expertise in Timing Closure including setup, hold, DRV, SI, Interface issues. Experience with formal verification for RTL to Netlist and Netlist to Netlist. Knowledge of emerging technologies such as machine learning and AI for design automation and optimization.

Physical Implementation activities for Sub systems include Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure, and power optimization. You should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Your expertise should include timing convergence of high-frequency data-path intensive Cores and advanced STA concepts. You should be well-versed with Block level PnR convergence using Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in the latest technology nodes. A good understanding of clocking architecture is essential. Collaboration with design, DFT, and PNR teams to resolve issues related to constraints validation, verification, STA, Physical design, etc. is a critical part of the role. Proficiency in Tcl/Perl Scripting is required. Experience in working as part of a larger team, meeting project milestones and deadlines, and handling technical deliverables with a small team of engineers is expected. Strong problem-solving skills and good communication skills are essential. Qualcomm India Private Limited is looking for candidates with a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. Alternatively, a Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience will be considered. A PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience are also acceptable. Qualcomm is an equal opportunity employer and is committed to providing an accessible process for individuals with disabilities. If you require accommodation during the application/hiring process, you may contact Qualcomm at disability-accommodations@qualcomm.com. Employees at Qualcomm are expected to adhere to all applicable policies and procedures, including those related to security and protection of Company confidential information. Staffing and Recruiting Agencies are advised that Qualcomm's Careers Site is only for individuals seeking a job at Qualcomm. Unsolicited submissions from agencies or individuals being represented by an agency will not be considered. Qualcomm does not accept unsolicited resumes or applications from agencies. For more information about this role, please contact Qualcomm Careers.,

Join our dynamic front-end design team at Cisco Silicon One, where innovation meets cutting-edge technology! As part of the heart of silicon development at Cisco, you'll engage in every facet of chip design, from architecture to validation, using the latest silicon technologies to create groundbreaking devices. Cisco Silicon One is the only unified silicon architecture that empowers customers to deploy top-tier silicon across diverse applications, from top-of-rack switches to expansive data centers. Be a part of shaping Cisco's revolutionary solutions by designing and testing advanced ASICs that integrate networking, compute, and storage into a single system. With tightly integrated hardware and software solutions, you'll gain exposure to all aspects of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready to make a significant impact in the industry. Join us and push the boundaries of what's possible! You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you'll contribute to developing next-generation networking chips. Responsibilities include: - Being a member of the design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. - Option to also do block-level RTL design or block or top-level IP integration. - Helping develop an efficient methodology to promote block-level SDCs to fullchip and to bring fullchip SDC changes back to the block level. - Helping develop and apply a methodology to ensure correctness and quality of SDCs as early as possible in the design cycle. - Reviewing block-level SDCs and clocking diagrams and mentoring other RTL design owners on SDC development. - Creating fullchip clocking diagrams and related documentation. Minimum Qualifications: - Bachelors Degree in Electrical or Computer Engineering with 7+ years of ASIC or related experience or Masters Degree in Electrical or Computer Engineering with 5+ years of ASIC or related experience. - Experience with block/full chip SDC development in functional and test modes. - Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus. - Understanding of related digital design concepts (e.g., clocking and async boundaries). - Experience with synthesis tools (e.g., Synopsys DC/DCG/FC), Verilog/System Verilog programming. Preferred Qualifications: - Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence). - Experience with Spyglass CDC and glitch analysis. - Experience using Formal Verification: Synopsys Formality and Cadence LEC. - Experience with scripting languages such as Python, Perl, or TCL. Join us at Cisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all. Our passion is connection, and we celebrate our employees" diverse set of backgrounds focusing on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best but be their best. We understand our outstanding opportunity to bring communities together, and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer 80 hours each year allows us to give back to causes we are passionate about, and nearly 86% do! Our purpose, driven by our people, is what makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. We ensure that every step we take is a step towards a more inclusive future for all. Take your next step and be you, with us!,

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. 12-14 yrs of work experiences in VLSI domain with Master s/bachelor s degree in engineering Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology Expertise in assertions development/closure, constraint randomization, functional and code coverages, formal verification Expertise in test-bench development Strong RTL and GLS (w/ or w/o SDF) sim debug skills Should be able to manage project schedule and delivery independently Should be good in Perl/Tcl scripting and automation We re doing work that matters. Help us solve what others can t.

As an RTL Design Engineer at Alphawave Semi, you will play a crucial role in the advancement of digital technology by contributing to the next generation Chiplet designs. You will be involved in the complete ASIC development cycle, from concept to product, and work on cutting-edge technologies that power innovation in data-demanding industries. Your responsibilities will include microarchitecting and RTL Design of SoC SubSystem/IP blocks, developing UPF and running CLP checks, ensuring RTL quality checks, creating documentation for hardware blocks, and collaborating with various teams to ensure the successful tapeout of high-quality SoCs. To excel in this role, you should possess a Bachelor's or Master's degree in Electrical, Electronics and Communication, or Computer Science Engineering, along with 8+ years of experience in SoC architecture and full-chip design for multi-million gate SoCs. Your expertise should encompass the design convergence cycle, IP dependencies management, project milestone tracking, and experience in CPU, high-speed serial interfaces, or coherence/noncoherent NOC domains. Your skills in communication, collaboration, and leadership will be essential in working effectively in a fast-paced, distributed team environment. You should have a strong understanding of bus protocols, memory controllers, chip IO design, test plans, verification, synthesis, formal verification, timing closure, post-silicon debug, and decision-making under incomplete information. At Alphawave Semi, we offer a hybrid work environment and a comprehensive benefits package that includes competitive compensation, Restricted Stock Units (RSUs), provisions for advanced education, medical insurance, wellness benefits, educational assistance, advance loan assistance, and office lunch & snack facilities. We are committed to equal employment opportunity and welcome applicants from diverse backgrounds, providing accommodations during the recruitment process to ensure a fair and inclusive environment for all candidates.,