234 Formal Verification Jobs - Page 3

Lead Design Verification Engineer Bangalore We are looking for an experienced Lead Design Verification Engineer (412 yrs) to join our semiconductor team. Youll lead SoC/ASIC/IP verification using SystemVerilog, UVM, SVA, and drive test planning, coverage, regressions, and debug. ???? Must-have: Strong expertise in protocols (PCIe, DDR, USB, AMBA, MIPI, CXL), EDA tools (VCS, Xcelium, Questa), scripting (Python/Perl/Tcl), and low-power/CDC/formal verification. ???? Bonus: Experience with emulation/GLS, lint, DFT awareness, and leadership/mentoring. ???? Location: Bangalore, India ? Experience: 412 years ???? Apply now or share your profile at [HIDDEN TEXT] Show more Show less

About Us: We are starting a new Silicon RD center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrows mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we dont just follow industry trends we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, youll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global RD organization, youll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What We Offer: Creative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. Youll have the opportunity to explore advanced verification technologies alongside skilled experts. Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development. A collaborative and inclusive culture that values diversity and innovation. A competitive compensation and benefits package. Key Responsibilities: Take part in the verification of designs, whether at the block or subsystem level. Participate in defining and implementing UVM-based test environments. Support the creation of Verification Strategies and contribute to the development and execution of Verification Plans. Develop, run, and debug test cases to ensure design quality. Contribute to the improvement and optimization of verification methodologies. Generate documentation throughout the verification lifecycle. Collaborate closely with other verifiers, designers, and architects. Build competence in the technical domain. Engage in cross-team collaboration to ensure successful project delivery. Required Qualifications: Bachelor s degree in electrical or computer engineering. 5+ years industry experience in ASIC IP verification using SystemVerilog and UVM. Experience in / with: developing verification test plans and creating directed/randomized test cases. implementing scoreboards, checkers, bus functional models within UVM environments. AMBA-based designs such as AXI and CHI. SystemVerilog Assertions. Additional Requirements: Experience with Cadence or Synopsys verification suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Experience in low-power design verification. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience in formal verification Experience in verification in one or more of the following hardware domains: ARM-based real-time embedded microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) Primary country and city: India (IN) || Bangalore Req ID: 768637

Take part in the verification of designs, whether at the block or subsystem level. Participate in defining and implementing UVM-based test environments. Support the creation of Verification Strategies and contribute to the development and execution of Verification Plans. Develop, run, and debug test cases to ensure design quality. Contribute to the improvement and optimization of verification methodologies. Generate documentation throughout the verification lifecycle. Collaborate closely with other verifiers, designers, and architects. Build competence in the technical domain. Engage in cross-team collaboration to ensure successful project delivery. Required Qualifications: Bachelor s degree in electrical or computer engineering. 5+ years industry experience in ASIC IP verification using SystemVerilog and UVM. Experience in / with: developing verification test plans and creating directed/randomized test cases. implementing scoreboards, checkers, bus functional models within UVM environments. AMBA-based designs such as AXI and CHI. SystemVerilog Assertions. Additional Requirements: Experience with Cadence or Synopsys verification suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Experience in low-power design verification. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience in formal verification Experience in verification in one or more of the following hardware domains: ARM-based real-time embedded microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.)

Key Responsibilities : We are looking for a highly motivated software engineer to work in the QuestaSim R&D team of the Siemens EDA Development responsibilities will include core algorithmic advances and software design/architecture. You will collaborate with a senior group of software engineers contributing to final production level quality of new components and algorithms and to build new engines and support existent code. Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Are you excited to know more about this Role ? Job Qualification: An ideal candidate should have skills below: B.Tech or M.Tech in Computer Science & Engineering (CSE), Electrical Engineering (EE), or Electronics & Communication Engineering (ECE) from a reputable engineering institution having 8 - 15 years of experience. Strong knowledge of C/C++, algorithms, and data structures. Familiarity with compiler concepts and optimizations. Experience with UNIX and/or LINUX platforms is essential. Excellent problem-solving and analytical skills. Self-motivated with the ability to work independently and guide others towards successful project completion. We are not looking for superheroes, just super minds! Having the below skills will be an added advantage: Strong understanding of basic digital electronics concepts. Familiarity with machine learning (ML) and artificial intelligence (AI) algorithms, particularly their implementation in data-driven tasks. Proficiency in hardware description languages such as Verilog, SystemVerilog, and VHDL. Experience with parallel algorithms and job distribution techniques. Exposure to simulation or formal verification methodologies is a plus.

Key Responsibilities : We are looking for a highly motivated software engineer to work in the QuestaSim R&D team of the Siemens EDA Development responsibilities will include core algorithmic advances and software design/architecture. You will collaborate with a senior group of software engineers contributing to final production level quality of new components and algorithms and to build new engines and support existent code. Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Are you excited to know more about this Role ? Job Qualification: An ideal candidate should have skills below: B.Tech or M.Tech in Computer Science & Engineering (CSE), Electrical Engineering (EE), or Electronics & Communication Engineering (ECE) from a reputable engineering institution having 8 - 15 years of experience. Strong knowledge of C/C++, algorithms, and data structures. Familiarity with compiler concepts and optimizations. Experience with UNIX and/or LINUX platforms is essential. Excellent problem-solving and analytical skills. Self-motivated with the ability to work independently and guide others towards successful project completion. We are not looking for superheroes, just super minds! Having the below skills will be an added advantage: Strong understanding of basic digital electronics concepts. Familiarity with machine learning (ML) and artificial intelligence (AI) algorithms, particularly their implementation in data-driven tasks. Proficiency in hardware description languages such as Verilog, SystemVerilog, and VHDL. Experience with parallel algorithms and job distribution techniques. Exposure to simulation or formal verification methodologies is a plus.

Your Impact Write micro-architecture specifications and participate in reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integration and timing methodology/analysis. Develop and analyze functional coverage. Help define, evolve, and support our design methodology. Collaborate with the verification team to address design bugs and close code coverage. Work closely with the physical design team to close design timing and place-and-route issues. Triage, debug, and root cause simulation, software bring-up, and customer failures Perform diagnostic and post-silicon validation tests in the lab Minimum Qualifications: Bachelor's Degree / Master's Degreein Electrical or Computer Engineering with 7+ years of ASIC design. Prior experience working with Verilog or System Verilog programming skills Experience with simulators/synthesis/static timing constraints and related tools (e.g., VCS, DC, PrimeTime) Experience with debugging and verification methodologies Preferred Qualifications: Understanding of Networking technologies and concepts Scripting experience (Python, Perl, TCL, shell programming) Experience with formal verification tools Experience with emulation

What You'll Do Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. Responsibilities Looking for a Front-end Design ASIC Engineer. Architectural work: in-depth understanding of the architecture, and identification of problems and solutions. All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for low power and area; highlighting issues and standard methodologies for power and area optimization. Document and improve standard methodologies to make product successful. Who You Are Worked in architecture and definition of high-scale, high-performance ASICs. Validated experience in implementation: specification, RTL design, lint, cdc, timing analysis, formal verification, system testing. Validated experience in flow automation (scripting, Makefiles, etc), and establishing guidelines for the team. Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion. BS/MS and 5+/3+ years respectively of hands-on experience in large-scale, high-performance ASIC BS/MS should be in EE/CS. Minimum Qualifications RTL development (Verilog, SystemVerilog, VCS, Spyglass, CDC, Formal verification) Experienced in system debug and SW/HW bringup, system validation of silicon towards FCS. Gate-level understanding of RTL and Synthesis Programming/scripting skills (C, C++, Perl) Hardware Emulation Platforms and tools (such as EVE, Veloce) Good written/verbal interpersonal skills and leadership skills. Who You'll Work With Come join us and be part of the Cisco SiliconOne team and take part in crafting Cisco's groundbreaking Enterprise and Service Provider solutions by crafting some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a rare combination of a startup culture with the benefits of working for the top tier networking company in the world!

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.Job requirements: Experience with Synthesis, constraints, Formal Verification and STA. Good Domain Knowledge on RTL Design, implementation, and Timing analysis. Exposure in scripting (Pearl/Python/TCL). IO timing sta reporting and signoff. Peripheral protocols like spi,i3c,i2c,sdcc/emmc etc Strong debugging capabilities at Synthesis, timing analysis & implementation. Collaborate closely with cross-function team to research, design and implement performance, constraints and power management strategy for product roadmap. Good team player. Need to interact with the other teams/verification engineers proactively. Ability to debug and solve issues independently. STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.

Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications: Bachelors or Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering 5+ years of Hardware Engineering or related work experience. 1+ year in a technical leadership role with or without direct reports. Principal Duties and Responsibilities: 5-7 years of relevant experience in ASIC Physical Verification Good understanding of overall design Flow from RTL to GDS. Hands on Experience on Physical Verification closure of full chip & Hierarchical Designs Hands on DRC & LVS Experience on Lower node Technologies with Synopsys/Cadence/Calibre Tools Good knowledge on PnR flow, ECO implementation Knowledge on Perl / TCL scripting language , SVRF coding is advantage Experience on multi voltage designs Good understanding of other domains of signoff of in Physical Design (STA/PV/IR/FV/CLP) Responsibilities Responsible for Block/ Chip Tile PV closure to achieve the best PPA DRC & LVS closure for Block and Full Chip for complex hierarchical Designs in 4nm/3nm nodes Interaction with IR, IP , ESD & PD teams for Physical Verification Convergence & Resolving Conflicts Able to work on multiple blocks at same time with minimal supervision Responsible for Full Chip LVS & DRC closure Responsible for Analog integration closure for all IP's used in SOC

What You'll Do Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. Responsibilities Looking for a Front-end Design ASIC Engineer. Architectural work: in-depth understanding of the architecture, and identification of problems and solutions. All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for low power and area; highlighting issues and standard methodologies for power and area optimization. Document and improve standard methodologies to make product successful. Who You Are Worked in architecture and definition of high-scale, high-performance ASICs. Validated experience in implementation: specification, RTL design, lint, cdc, timing analysis, formal verification, system testing. Validated experience in flow automation (scripting, Makefiles, etc), and establishing guidelines for the team. Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion. BS/MS and 8+/6+ years respectively of hands-on experience in large-scale, high-performance ASIC BS/MS should be in EE/CS. Minimum Qualifications RTL development (Verilog, SystemVerilog, VCS, Spyglass, CDC, Formal verification) Experienced in system debug and SW/HW bringup, system validation of silicon towards FCS. Gate-level understanding of RTL and Synthesis Programming/scripting skills (C, C++, Perl) Hardware Emulation Platforms and tools (such as EVE, Veloce) Good written/verbal interpersonal skills and leadership skills.

Experience with STA using Primetime and PTPX required Proficient in constraint generation. Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl scripting is required Strong problem solving and ASIC development/debugging skills. Experience with CPU micro-architecture and their critical path. Low power implementation techniques experience. High speed CPU implementation. Place and route tool experience. Constraint management tool and Verilog coding experience Experience (years) : 3+ Year Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

We are seeking a highly motivated and experienced Senior Staff SoC/MCU Verification Engineer to join our team. In this role, you will contribute to the verification of complex System-on-Chip (SoC/MCU) designs, ensuring functionality, performance, and quality meet project and customer specifications. This position requires expertise in advanced verification methodologies, formal verification, strong technical leadership, and excellent problem-solving skills. Staff Engineer, DV We are seeking a highly motivated and experienced Staff SoC/MCU Design Verification Engineer to join our team. In this role, you will contribute to the verification of complex System-on-Chip (SoC/MCU) designs, ensuring functionality, performance, and quality meet project and customer specifications. This position requires expertise in advanced verification methodologies, strong technical leadership, and excellent problem-solving skills. Key Responsibilities - MCU-Level UVM Verification: Implement modular UVM testbenches for SoC subsystems (e.g., sensor hubs, AI accelerators, communication fabrics). - Develop coverage-driven verification plans (functional, code, assertion coverage) aligned with automotive safety and security requirements. - Debug complex SoC-level scenarios (e.g., multi-protocol interactions, power-aware verification). Automotive VIP Integration: Integrate and customize 3rd-party VIPs (e.g., Synopsys, Cadence, Mentor) for automotive protocols. Soft Skills - Demonstrated ability to provide clear and transparent communication within teams and with global customers. - Agile mindset to adapt to dynamic project requirements and timelines. - Innovative thinker capable of contributing ideas to enhance designs or optimize workflows. - Proven ability to manage daily tasks and lead a design team with a sense of ownership and accountability.

Roles & Responsibilities: STA Synthesis Deep understanding and experience of STA tool PrimeTime /Tweaker/ DMSA (PTECO). Knowledge of timing corners/modes, process variations and signal integrity related issues are required. Experience in timing closure of high frequency blocks & subsystems (Ghz range ) Experience in working full-chip STA closure, defining mode requirements and corners for timing closure. Strong Understanding of DFT modes requirements for timing signoff Good understanding of physical design flow and ECO implementation. Strong understanding of SDC constraints, OCV, AOCV, POCV analysis. Strong TCL/scripting knowledge is mandatory. Strong Experience in Synthesis Constraints development, LINT checks, CDC checks Experience in Formal Verification with Synopsys Formality and / or Cadence Conformal LEC. Strong understanding of ECO cycle, should be able to generate and implement functional Ecos Strong Understanding of DFT modes requirements for timing signoff No. of Vacancies 1 Job Nature Full Time Educational Requirements Bachelors or Masters degree in Electrical Engineering or related field Experience Requirements 8 Bengaluru Salary Industry Standard Other Benefits Work on next-gen automotive, IoT, and processor technologies. Gain full lifecycle exposure from spec-to-tape-out. Collaborate with leading semiconductor experts in a dynamic environment. Competitive compensation with strong career growth opportunities.

About the Role: We are seeking a highly experienced Verification Engineer to join our dynamic team, driving innovation in advanced verification methodologies for complex semiconductor designs. You will play a key role in architecting, developing, and deploying verification methodologies for industry-leading IPs and sub-systems. Key Responsibilities: Lead the deployment of verification tools, platforms, and strategies for complex IPs Drive simulation-based and hardware-assisted verification efforts, including debugging and root cause analysis Apply expertise in a broad range of verification technologies, including simulation, static, and formal verification Develop and enhance verification methodologies, including verification cockpits and CAD flows Collaborate cross-functionally with IP design and DV teams as well as tools teams to ensure product quality Mentor and guide junior engineers, fostering a culture of technical excellence Qualifications: 10+ years of experience in verification engineering for complex hardware systems Deep expertise in simulation and debug, with a proven track record of silicon success Hands-on experience with Static/ Formal verification tools and methodologies Experience developing and deploying verification methodologies, including verification cockpits and CAD flows Exposure to hardware-assisted verification environments (FPGA prototyping, emulation) is a strong plus Strong analytical, problem-solving, and communication skills Bachelors or Masters in Electrical Engineering, Computer Engineering, or related field Familiarity with industry-standard verification languages (SystemVerilog, UVM, SVA) Experience with scripting and automation (Python, Perl, TCL) Track record of technical leadership and cross-functional collaboration Why Synopsys: Join a team that powers innovation and values agility, courage, excellence, and trust. We offer opportunities to work on cutting-edge technology and make a real impact. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and accomplished digital design engineer with an unyielding drive for excellence. You thrive in technically challenging environments, where your deep understanding of RTL design and system architecture allows you to craft innovative solutions for complex problems. With a solid foundation in electrical engineering or VLSI, you have accumulated over five years of hands-on experience in designing and implementing ASIC solutions, particularly focusing on high-performance protocols such as DDR, PCIe, USB, or HBM. Your expertise extends beyond individual contributionyou are equally comfortable leading and mentoring small teams, fostering an environment of collaboration and shared learning. You are adept at translating functional specifications into detailed micro-architecture and design documents, always ensuring clarity and precision. Your technical toolkit includes mastery of Verilog/SystemVerilog, and you are well-versed in industry-standard flows encompassing linting, CDC analysis, synthesis, and static timing. Youre not just a technical expert; you are a proactive communicator, an enthusiastic collaborator, and a natural problem solver who takes initiative and ownership of deliverables. Your ability to adapt to a global, multi-site team environment is matched only by your commitment to continuous learning and professional growth. If youre ready to take on a pivotal role in shaping next-generation silicon IP, Synopsys is where your aspirations and impact can soar. What Youll Be Doing: Architecting, designing, and implementing state-of-the-art RTL for the next-generation high-performance DDR PHY and related IP cores. Translating standard and functional specifications into detailed architecture, micro-architecture, and design documentation for medium- to high-complexity features. Contributing as an individual designerhandling RTL coding, lint/CDC analysis, synthesis, debug, and test plan development. Collaborating with global teams across multiple sites, ensuring cohesive project execution and knowledge sharing. Leading or mentoring small teams of designers, providing technical guidance and fostering professional development. Engaging in continuous process improvement, proposing and implementing enhancements to design flows and methodologies. Troubleshooting and resolving design and verification issues, ensuring robust and high-quality deliverables. The Impact You Will Have: Directly contributing to the design and delivery of high-performance IP cores that power industry-leading semiconductor solutions worldwide. Elevating Synopsys reputation for technical excellence and innovation in the IP design space. Accelerating the adoption of advanced protocols and interfaces in cutting-edge technologies. Enabling customers to achieve faster time-to-market and superior silicon performance. Mentoring and uplifting team members, fostering a culture of knowledge sharing and technical growth. Driving continuous improvement in design methodologies, enhancing efficiency and product quality. Supporting Synopsys mission to remain at the forefront of the Era of Pervasive Intelligence through breakthrough silicon solutions. What Youll Need: Bachelors or Masters degree in Electrical Engineering, Electronics, VLSI, or related discipline. 10+ years of relevant industry experience in ASIC digital design, with a focus on protocols like DDR, PCIe, USB, or HBM. In-depth experience with RTL coding in Verilog/SystemVerilog and simulation tools for ASIC design. Strong command of design flows, including lint, CDC, synthesis, static timing analysis, and formal verification. Hands-on expertise in architecting and implementing control path-oriented designs (e.g., asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces). Familiarity with scripting languages such as Perl or Shellan advantage. Demonstrated ability to technically lead or mentor small teams of engineers. Who You Are: A collaborative team player who thrives in a multi-site, multicultural environment. An effective communicator, able to translate complex technical concepts for diverse audiences. A proactive problem-solver with strong analytical and troubleshooting skills. Self-motivated, showing high initiative and ownership of responsibilities. Adaptable and eager to learn, always seeking opportunities for personal and professional growth. Committed to fostering a positive, inclusive, and innovative team culture. The Team Youll Be A Part Of: You will join the R&D Solutions Group at our Bengaluru Design Center, a dynamic and diverse team dedicated to the design and development of industry-leading DesignWare IP cores. As a Technical Individual Contributor, you will collaborate with global experts in a multi-site environment, contributing to technically challenging projects that push the boundaries of silicon design. The team values innovation, continuous learning, and the sharing of knowledge, offering ample opportunities for growth and leadership. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

As a Data Scientist Associate Senior at JPMorgan Chase within the Asset & Wealth Management, you will be an integral part of a dynamic team where your unique skills will contribute to a successful culture and team. Your role involves collaborating with an agile team to create and implement reliable data collection, storage, access, and analytics solutions in a secure, stable, and scalable manner. Your responsibilities include the development, testing, and maintenance of crucial data pipelines and architectures across multiple technical areas within different business functions to support the firm's objectives effectively. In this position, you will design and implement solutions that leverage AI capabilities to address data management challenges. You will also provide guidance on and prioritize research areas that uphold data management and governance standards. Collaboration with lines of business and corporate functions is essential to identify co-development solutions focused on overcoming data management obstacles. The ideal candidate should have formal training or certification in data science concepts along with a minimum of 3 years of practical experience. Demonstrated expertise in deploying and overseeing machine learning models in production environments is necessary. You should possess a strong ability to monitor ML models in production, effectively tackling performance and data quality issues. Proficiency in implementing security best practices and compliance standards for Machine Learning systems is crucial. Experience with infrastructure optimization techniques to improve performance and efficiency is required. Additionally, developing REST APIs using frameworks like Flask or FastAPI for seamless integration into business solutions is expected. Preferred qualifications include experience with formal methods and formal verification, knowledge graphs, graph theory, and data management. These additional skills would be advantageous in fulfilling the responsibilities of the role effectively.,

The Opportunity We&aposre looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrows future by accelerating the critical data communication at the heart of our digital world from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. Our IP Scaling (IPS) organization is focused on creating customized IP for Alphawave Semi&aposs expanding customer base. We deliver industry-leading high-speed interconnect solutions tailored to specific requirements across a wide variety of use-cases including High Performance Computing and Artificial Intelligence. We are looking for an enthusiastic Design Verification Engineer to join our fun and dynamic team of experienced innovators. What you&aposll do: Own the end-to-end verification of new customer features Review design specifications and devise verification plans Build testbenches and analyze test failures to uncover design bugs Facilitate bit-matching of RTL design and MATLAB system models Integrate 3rd party VIPs for compliance testing of standard protocols Build releases of our design IP for customers Support post-silicon validation and bring-up activities Take on opportunities to lead, plan, and coordinate tasks with team members Collaborate closely with Design, Systems, Analog, FW, and PD teams Contribute to the continuous improvement of verification methodologies and processes What you&aposll need: 5+ years of ASIC design verification experience An applied understanding of UVM and verification techniques Experience with constrained-random verification in SystemVerilog and UVM Formal Verification, and Power-aware UPF verification techniques Tools/Languages - SystemVerilog, UVM, Python, Perl, C/C++, GNU Make Verification experience in SerDes PHY, DSP, and Analog mixed signal is desirable Knowledge in Ethernet and PCIe standards is desirable '&aposWe have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process. Show more Show less

The Opportunity We&aposre looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrows future by accelerating the critical data communication at the heart of our digital world from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. Our IP Scaling (IPS) organization is focused on creating customized IP for Alphawave Semi&aposs expanding customer base. We deliver industry-leading high-speed interconnect solutions tailored to specific requirements across a wide variety of use-cases including High Performance Computing and Artificial Intelligence. We are looking for an enthusiastic Design Verification Engineer to join our fun and dynamic team of experienced innovators. What you&aposll do: Own the end-to-end verification of new customer features Review design specifications and devise verification plans Build testbenches and analyze test failures to uncover design bugs Facilitate bit-matching of RTL design and MATLAB system models Integrate 3rd party VIPs for compliance testing of standard protocols Build releases of our design IP for customers Support post-silicon validation and bring-up activities Take on opportunities to lead, plan, and coordinate tasks with team members Collaborate closely with Design, Systems, Analog, FW, and PD teams Contribute to the continuous improvement of verification methodologies and processes What you&aposll need: 5+ years of ASIC design verification experience An applied understanding of UVM and verification techniques Experience with constrained-random verification in SystemVerilog and UVM Formal Verification, and Power-aware UPF verification techniques Tools/Languages - SystemVerilog, UVM, Python, Perl, C/C++, GNU Make Verification experience in SerDes PHY, DSP, and Analog mixed signal is desirable Knowledge in Ethernet and PCIe standards is desirable '&aposWe have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process. Show more Show less

You have a unique opportunity to join Astera Labs, a global leader specializing in purpose-built connectivity solutions that unleash the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform seamlessly integrates PCIe, CXL, and Ethernet semiconductor-based solutions along with the COSMOS software suite, offering a software-defined architecture that is not only scalable but also customizable. Building on strong relationships with hyperscalers and the data center ecosystem, we are at the forefront of innovation, delivering flexible and interoperable products that are transforming modern data-driven applications. Explore more about our groundbreaking work at www.asteralabs.com. As a candidate, you should possess a Bachelor's degree in electrical engineering (EE), with a preference for a Master's or Ph.D. in EE, accompanied by a background in Math or Computer Science. You should have a minimum of 8 years of experience in formal verification or 7 years in traditional design verification (DV). A strong work ethic, adept at managing multiple tasks in a dynamic environment, is essential. Your ability to plan for customer meetings, work independently, and exhibit an entrepreneurial mindset with a customer-centric approach are key attributes. Proficiency in cross-functional collaboration is also vital for this role. Your responsibilities will include developing detailed formal verification (FV) test plans based on design specifications and collaborating with design teams to enhance micro-architecture specifications. You will identify crucial logic components and micro-architectural properties to ensure design correctness. Implementing formal verification models, abstractions, and assertions, utilizing assertion-based model checking to detect corner-case bugs will be part of your role. You will apply complexity reduction techniques, develop scripts for enhanced productivity, and assist in implementing assertions and formal verification testbenches for RTL at unit/block levels. Your involvement in design reviews and collaboration with design teams to optimize design quality based on formal analysis feedback will be crucial. Proficiency in System Verilog/Verilog and scripting abilities with Python or Perl are required. Preferred candidates will have hands-on experience with formal verification tools like Synopsys VCFormal and Cadence JasperGold, along with familiarity in automating formal verification workflows within a CI/CD environment. At Astera Labs, we value diversity and inclusivity, believing that creativity and innovation thrive in a team with varied ideas, backgrounds, and experiences. We actively encourage individuals with diverse backgrounds, including people of color, LGBTQ+ and non-binary individuals, veterans, parents, and persons with disabilities, to apply and be part of our dynamic team.,

We are seeking a Director of Engineering (Design Verification) to oversee and expand our DV practice. With over 15 years of experience in SoC/ASIC verification, exceptional technical expertise, demonstrated leadership abilities, and the talent to motivate high-performing teams, you will play a pivotal role in our organization. Responsibilities include leading end-to-end SoC/ASIC Design Verification programs, establishing DV methodologies, flows, and best practices (UVM, SV, C-based), delivering technical leadership and practical problem-solving, managing and guiding top-performing engineering teams, collaborating with cross-functional teams for project success, driving customer engagement, ensuring delivery excellence, and supporting business development through pre-sales and technical discussions. The ideal candidate will possess a minimum of 15 years of semiconductor design verification experience, including at least 5 years in a leadership capacity. Proficiency in SystemVerilog, UVM, C/C++ co-simulation, and testbench architecture is essential. In-depth knowledge of ARM architecture, AMBA protocols (AXI, CHI, APB), high-speed interfaces (PCIe, DDR, Ethernet), Formal Verification, GLS, coverage closure, GLS methodology/flows, VIP Integration & Sequence usage, C-SV co-simulation, and Python scripting is required. Strong skills in people management, mentoring, and stakeholder engagement are also critical. Joining Seminovaa offers you the chance to be part of a rapidly growing semiconductor services company, led by its founder. You will have the opportunity to shape and lead the Design Verification practice, working on cutting-edge projects in AI, Automotive, Networking, and High-Performance Computing. Our collaborative, innovation-driven culture provides global exposure and a dynamic work environment. Apply now by sending your profile to careers@seminovaa.com. #SemiconductorJobs #VLSICareers #ChipDesign #NowHiring #Seminovaa #DFTengineers #Verificationengineers #PhysicalDesignEngineers,

Experience in Logic design / RTL coding is a must. Experience is SoC design and integration for complex SoCs is a must. Experience in Verilog/System-Verilog is a must. Experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint and CDC. Experience in Synthesis / Understanding of timing concepts is a plus. Experience in ECO fixes and formal verification. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture. Excellent oral and written communications skills. Proactive, creative, curious, motivated to learn and contribute with good collaboration skills Role: Design Verification Engineer Industry Type: Electronic Components / Semiconductors Department: Engineering - Hardware & Networks Employment Type: Full Time, Permanent Role Category: Hardware Education UG: Any Graduate PG: Any Postgraduate

Job description Meta is looking for ASIC Engineer, Formal Verification to join our dynamic team and embark on a rewarding career journey. Develop and implement ASIC design methodologies, including design, verification, and testing Collaborate with cross-functional teams to identify and understand requirements and develop solutions that meet business needs Develop and maintain design specifications, test plans, and documentation Participate in the full ASIC development cycle, including architecture, RTL design, verification, and synthesis Perform design optimization and analysis to ensure optimal performance and power efficiency Ensure compliance with industry standards and guidelines. Strong knowledge of ASIC design methodologies and tools. Excellent communication and interpersonal skills Strong analytical and problem-solving skills

As an experienced Verification Engineer with a minimum of 5 years of experience, your primary responsibility will be to lead the verification of DDR memory controller and PHY designs in compliance with DDR standards like DDR3, DDR4, DDR5, and other memory interface protocols. You will be required to develop and implement scalable, reusable, and efficient verification environments and testbenches for DDR designs using SystemVerilog, UVM, and other industry-standard methodologies. Ensuring protocol compliance is crucial, which includes validating command, data, and clock synchronization, read/write cycles, burst transfers, refresh cycles, error handling, and power management. Your role will involve creating detailed verification plans based on DDR specifications and requirements, focusing on corner cases, timing, and protocol validation for full coverage. Running simulations, debugging issues using tools like Questa, VCS, or ModelSim, and applying advanced debugging techniques such as waveform analysis, assertion-based verification, and code coverage will be part of your daily tasks. You will set up and manage regression testing for DDR functionality to ensure continuous validation and early detection of design issues. Achieving high functional and protocol coverage is vital, ensuring that timing constraints, corner cases, and failure scenarios are thoroughly verified. Implementing formal verification techniques to validate critical components of the DDR design, ensuring correctness in timing and data flow, and verifying crucial operations will also be part of your responsibilities. This position requires a Bachelor's or Master's degree in ECE/EEE or VLSI/Electronics from a reputable institution. The position is based in Bangalore/Hyderabad.,

The Verification role requires you to be proficient in Functional and Performance verification, utilizing effective methodologies at different levels such as Module, Subsystem, SoC, and System. It is essential to have the skills to translate requirements into a verifiable plan. You will collaborate with SoC and IP developers locally and globally to implement best practices and enhance productivity continuously. A meticulous approach towards achieving zero defects is crucial. Your responsibilities will include creating verification test benches, verification components, test cases for simulation, formal verification, and emulation. Additionally, you will be responsible for debugging failures and formulating simulation scenarios for various analyses. Your key tasks will involve team leadership, technical guidance, and Verification planning. You will be responsible for developing, fine-tuning, and implementing verification test benches. Furthermore, you will create verification test bench components like drivers, monitors, response checkers, and leverage advanced UVM VIPs. Your role will also entail generating direct and constrained-random stimuli using C and SystemVerilog, examining RTL code, functional coverage, and assertion results. You will be expected to work on functional coverage development and system Verilog assertions. Proficiency in formal verification techniques, robust debugging skills, failure re-creation, and root cause analysis are essential requirements. Strong debugging and logical reasoning skills are crucial for this position. To excel in this role, you must have a strong background in C and UVM/SystemVerilog-based Test environments. Understanding the design/architecture and the ability to debug RTL/Gate netlist are mandatory skills. Coverage-driven Verification expertise is required to fulfill the Functional and Performance requirements of the SoC and manage regression effectively. Knowledge of Microcontroller architecture, ARM Cores, Interconnect (NIC, FlexNoC), Cache Coherency, and Bus Protocols like AHB/AMBA, AXI, ACE is essential. Additional skills that would be advantageous for this role include experience with Memory controllers (Flash, SRAM, DDR3/4/LPDDR), Protocols such as PCIe, MIPI, GPU, Ethernet, and Serial/Quad flash. Familiarity with Formal verification methodologies and Apps, AVIP, PinMuxing Verification, Randomization, and Low Power intent verification using UPF is beneficial. Exposure to pre-silicon validation/emulation tools like Veloce, Zebu, FPGA Prototyping would be considered a plus.,

As a Silicon Design Engineer 2 at AMD, your role involves collaborating with formal experts and designers to verify formal properties and drive convergence. You will have the opportunity to work on modern, complex processor architecture, digital design, and verification in a team-oriented environment. Your strong analytical and problem-solving skills will be pivotal in understanding design specifications and creating scenarios to verify the design effectively. Communication skills are essential as you coordinate with RTL engineers to implement logic design for improved clock gating and verify different aspects of the design. Your responsibilities will include writing tests, sequences, and testbench components in SystemVerilog and UVM to achieve verification of the design. You will be accountable for verification quality metrics such as pass rates, code coverage, and functional coverage. Prior experience in design concepts and RTL implementation at the project level would be advantageous. Familiarity with formal tools and functional verification tools by VCS, Cadence, or Mentor Graphics is preferred. A solid understanding of computer organization and architecture is also important for this role. To excel in this position, you should possess a Bachelor's or Master's degree in computer engineering or Electrical Engineering. AMD offers a supportive work culture that values innovation, collaboration, and diversity. Join us in advancing next-generation computing experiences and being part of a team that pushes the boundaries of technology.,