Location: Bangalore Location: 1-15 Years Preferred Education B.Tech/M.Tech Area of Expertise RTL / Logic Development in VHDL/Verilog Full FPGA development flow from logic design, place route, timing analysis closure Experience with advanced Xilinx/Intel FPGA families and the Xilinx/Intel development tools including Vivado/Quartus Making testbenches for functional simulation of IP/FPGA design Troubleshooting and debugging FPGA implementations on boards Knowledge of any scripting language such as bash/Perl/python Highly motivated, self-starter with good interpersonal skills and a strong team player Excellent communication, critical thinking, and problem-solving skills Show more Show less
You should be an ASIC designer with a minimum of 1-15 years of experience in RTL design using Verilog/System Verilog. Your expertise should cover all aspects of the RTL design flow, including Specification/Microarchitecture definition, design and verification, Timing Analysis, DFT, and Implementation. You should also have experience in Integration, RTL signoff tools, UPF/Low power signoff, CDC/RDC, and Lint. Your domain knowledge should be strong in Clocking, System modes, Power management, debug, interconnect, safety, security, and other architectures. As a highly motivated individual, you should be a self-starter with excellent interpersonal skills and the ability to work effectively in a team. Strong communication, critical thinking, and problem-solving skills are essential for this role. Preferred education for this position is any degree.,
As a FPGA Development Engineer in Bangalore, you will be responsible for RTL / Logic Development in VHDL/Verilog and managing the full FPGA development flow from logic design to place route, timing analysis closure. Your role will involve working with advanced Xilinx/Intel FPGA families and their respective development tools like Vivado/Quartus. You will be creating testbenches for functional simulation of IP/FPGA designs and troubleshooting and debugging FPGA implementations on boards. Proficiency in scripting languages such as bash, Perl, or Python will be beneficial for this role. We are looking for a highly motivated individual who is a self-starter with excellent interpersonal skills and the ability to work effectively in a team. Strong communication, critical thinking, and problem-solving skills are essential for success in this position. If you have a B.Tech/M.Tech degree and 1-15 years of experience in FPGA development, we encourage you to apply for this exciting opportunity.,
As an RTL / Logic Development Engineer in Bangalore, you will be responsible for the following: - Developing RTL/logic in VHDL/Verilog - Executing full FPGA development flow including logic design, place route, timing analysis closure - Working with advanced Xilinx/Intel FPGA families and development tools like Vivado/Quartus - Creating testbenches for functional simulation of IP/FPGA design - Troubleshooting and debugging FPGA implementations on boards - Utilizing scripting languages such as bash/Perl/python Qualifications: - B.Tech/M.Tech in a relevant field - 1-15 years of experience in FPGA development - Highly motivated, self-starter with good interpersonal skills - Strong team player with excellent communication, critical thinking, and problem-solving abilities (Note: No additional details of the company were provided in the job description.),
As an Analog Circuit Designer at our company in Bangalore, you will be responsible for designing Analog Designs on advanced process technologies. Your key responsibilities will include: - Deep understanding of Circuit design/physical design of Analog Designs - Expertise in designing blocks like Analog to Digital converters, Amplifiers, Switch-cap circuits, Voltage, and Current Reference Generation circuits, GPIO, Differential Tx/Rx, oscillators, ESD, etc. - Proficiency in Reliability aware design and familiarity with Aging and RV tools - Ability to design floor plan and routing in Layout - Knowledge of Industry-standard tools such as Cadence design Environment (ADEXL or Virtuoso), DRC, LVS, and post-layout extraction tools - Familiarity with RTL behavioral coding and simulations, timing extractions of custom blocks - Strong communication skills and proven leadership experience - Self-driven and proactive nature to own and deliver high-quality end-to-end Analog designs - Fast learner with good problem-solving skills, multitasking ability, and attention to quality and detail - Expertise in mixed-signal designs and data-converters (Discrete / Continuous-time Sigma-Delta) is a major plus Qualifications required for this role: - B.Tech/M.Tech degree - 1-15 years of experience in Analog Circuit Design If you are looking for a challenging role where you can utilize your expertise in Analog Circuit Design and work with cutting-edge technologies, then this opportunity is for you.,
Company Description Blueberry Semiconductors is a VLSI Design services company specializing in Design, Physical Implementation, Formal Verification, Design for Test (DFT), Verification and Silicon validation, FPGA Implementation, Rapid Prototyping, and embedded software and systems, including firmware verification. The company has employee-friendly policies that ensure high levels of employee satisfaction. The leadership team has extensive experience from large multinational companies and leading service providers. The Founders and Core team members are committed to transforming innovative concepts into silicon and leveraging the talent in India to elevate its status in the global semiconductor industry. Role Description Key Responsibilities Lead formal verification of complex IP-level RTL designs using property checking methodologies. Develop, code, and maintain System Verilog Assertions (SVA) for design properties. Build formal verification environments/testbenches from scratch and integrate with RTL designs. Dive deep into microarchitecture specifications , extract verification requirements, and craft formal test plans. Apply divide-and-conquer, abstraction, and complexity reduction techniques to tackle large designs effectively. Drive verification to closure with clear sign-off criteria . Collaborate with design teams and provide early bug detection and root-cause analysis using formal. Leverage and verify industry-standard protocols (AMBA AXI/AHB/APB, PCIe, USB, I2C, SPI, etc.). Mentor and coach engineers in formal verification tools, flows, and best practices, building team strength. What We’re Looking For 4+ years of strong hands-on experience in Formal Verification at the IP level. Proficiency in System Verilog Assertions (SVA) . Proven track record of building formal verification testbenches from scratch. Ability to comprehend microarchitecture specs and map them into verification requirements. Skill in applying formal abstraction, modularization, and scalability techniques . Mandatory: Hands-on experience with at least one commercial formal verification tool (Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, OneSpin). Solid understanding of AMBA protocols and other high-speed/serial protocols. Strong communication and documentation skills. Passion for mentoring and enabling engineers to excel in formal verification. What’s In It For You? Be part of a newly formed consulting team specializing in Formal Verification. Learn directly from industry veterans and accelerate your technical depth. Opportunity to define methodologies and influence best practices in formal verification. Exposure to next-generation semiconductor designs and industry-leading IPs. A culture that celebrates innovation, ownership, and growth . Build a flourishing career path in one of the most in-demand and high-impact areas of VLSI verification. Qualifications Expertise in Formal Verification Strong Analytical Skills and Communication abilities Experience in Customer Service and Insurance Verification Able to lead a team and work collaboratively with cross-functional teams Experience in the semiconductor industry is a plus Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or related field
As an ASIC designer with a minimum of 1-15 years of experience in RTL design using Verilog/System Verilog, you play a crucial role in the RTL design flow. Your responsibilities include: - Specification/Microarchitecture definition - Design and verification - Timing Analysis - DFT, and Implementation - Integration - RTL signoff tools - UPF/Low power signoff - CDC/RDC - Lint Your domain knowledge should encompass Clocking, System modes, Power management, debug, interconnect, safety, security, and other architectures. Your expertise in these areas will be invaluable in contributing to the success of the projects. As a highly motivated individual, you should be a self-starter with excellent interpersonal skills and the ability to work effectively in a team. Strong communication, critical thinking, and problem-solving skills are essential for this role. The preferred education for this position is any degree.,
Deep understanding of Circuit design/ physical design of Analog Designs on advanced process technologies Expertise in analogy design of blocks like Analog to Digital converters, Amplifiers, Switch-cap circuits, Voltage, and Current Reference Generation circuits, GPIO, Differential Tx / Rx, oscillators, ESD, etc Expertise in Reliability aware design and familiarity with Aging and RV tools. > Ability to design floor plan and routing in Layout Good grasp of Industry-standard tools such as Cadence design Environment (ADEXL or Virtuoso) Knowledge of DRC, LVS, and post-layout extraction tools, etc Familiarity with RTL behavioral coding and simulations, timing extractions of custom blocks Strong communicator and proven leadership experience, self-driven, proactive nature to own and deliver high-quality end to end Analog designs Fast learner, good problem-solving skills, multitasking ability, and attention to quality and detail. Expertise in mixed-signal designs and data-converters (Discrete / Continuous-time Sigma-Delta) is a major plus Apply now Please enable JavaScript in your browser to complete this form. Name * Email * Phone * File Upload Click or drag a file to this area to upload. Comment Submit
Experience doing physical design targeted to the 7nm/16nm FinFet process Good knowledge of cell libraries various views and models Good understanding of static timing analysis (STA), EM/IR, and sign-off Strong hands-on experience with Chip Level / Sub-chip level floor planning, > partition, pin assignment, Power planning, Bump Planning, Pad Ring Creation, > Block level physical implementation, timing closure, physical verification, Chip level integration of different sub-blocks, and custom macros/IPs, Timing, IR/EM analysis and closure, Physical Verification - block and chip level EDA Tool Expertise: Innovus, Tempus/PrimeTime-SI, Voltus/RedHawk, StarXT/Quantus, Calibre,LEC, etc Good software and scripting skills (Python, tcl) Good communication skills and the ability and desire to work as part of a team Self-driven individual and an excellent team player Good communication abilities Apply now Please enable JavaScript in your browser to complete this form. Name * Email * Phone * File Upload Click or drag a file to this area to upload. Comment Submit
Knowledge of various DFT technologies for example JTAG, Mbist, Scan Experience with RTL Coding- Verilog, System Verilog, VHDL Excellent in Scripting languages for example Perl/Tcl/Tk/Python Exposure to Change Management Software for example Perforce is a strong plus Excellent problem-solving and analytical skills Excellent communication, teamwork, and networking skills Experience with Industry Standard DFT EDA Tools is preferred Apply now Please enable JavaScript in your browser to complete this form. Name * Email * Phone * File Upload Click or drag a file to this area to upload. Comment Submit
RTL / Logic Development in VHDL/Verilog Full FPGA development flow from logic design, place route, timing analysis closure Experience with advanced Xilinx/Intel FPGA families and the Xilinx/Intel development tools including Vivado/Quartus Making testbenches for functional simulation of IP/FPGA design Troubleshooting and debugging FPGA implementations on boards Knowledge of any scripting language such as bash/Perl/python Highly motivated, self-starter with good interpersonal skills and a strong team player Excellent communication, critical thinking, and problem-solving skills Apply now Please enable JavaScript in your browser to complete this form. Name * Email * Phone * File Upload Click or drag a file to this area to upload. Comment Submit
Hands-on experience in developing Analog Layout /IO layout design Good exposure on FinFet layouts in lower nodes Expertise in using the best and latest features of Cadence and Calibre DRC/LVS Good exposure to ESD, LUP, antenna layout challenges, and analyzing/fixing EMIR issues Capable of working independently and with the team and getting work done The ability to work communicate effectively with global engineering teams Apply now Please enable JavaScript in your browser to complete this form. Name * Email * Phone * File Upload Click or drag a file to this area to upload. Comment Submit
Strong SV/UVM fundamentals Experience of building Test benches from scratch Assertions driven verification Coverage driven verification Any protocol Experience Highly motivated, self-starter with good interpersonal skills and a strong team player Excellent communication, critical thinking, and problem-solving skills Apply now Please enable JavaScript in your browser to complete this form. Name * Email * Phone * File Upload Click or drag a file to this area to upload. Comment Submit
Experienced in RTL design using Verilog / System Verilog ASIC designers with experiences in all aspects of RTL design flow from Specification/Microarchitecture definition to design and verification, Timing Analysis, DFT and Implementation Integration, RTL signoff tools, UPF/Low power signoff and CDC/RDC, Lint Strong domain knowledge of Clocking, System modes, Power management, debug, interconnect, safety, security, and other architectures Highly motivated, self-starter with good interpersonal skills and a strong team player Excellent communication, critical thinking, and problem-solving skills Apply now Please enable JavaScript in your browser to complete this form. Name * Email * Phone * File Upload Click or drag a file to this area to upload. Comment Submit
Role Overview: At Blueberry Semiconductors, you have the opportunity to join a verification team dedicated to a Next-Gen AI SoC for Edge & Automotive applications. As a Lead Verification Engineer, you will play a crucial role in driving the verification strategy for a full-fledged AI SoC. This involves building verification frameworks from scratch, influencing design decisions, and ensuring performance and quality meet the highest automotive-grade standards. You will work alongside industry experts and be part of an exciting journey in developing cutting-edge technologies for edge computing and automotive intelligence. Key Responsibilities: - Own the SoC-level verification strategy, planning, and closure. - Deliver exceptional verification quality and support designers effectively. - Create scalable UVM environments for multi-protocol data fabrics. - Drive coverage metrics, randomization quality, and regression efficiency. - Mentor mid-level engineers, contribute to verification methodology evolution, and work closely with cross-functional teams including architecture, design, DFT, and prototyping. Qualification Required: - 10+ years of hands-on experience in SoC/IP verification using SystemVerilog & UVM. - Strong background in protocols such as PCIe, Ethernet, UCIe, AXI, and Interlaken. - Proficient in debugging, performance optimization, and committed to achieving first-pass success silicon. Additional Company Details: At Blueberry, you will collaborate with professionals who have a track record of developing and delivering numerous complex SoCs. The company values depth, curiosity, and ownership, offering continuous learning opportunities where your contributions directly impact silicon products that are deployed globally. Join Blueberry and be part of a team that is at the forefront of innovation in AI SoC verification for edge and automotive applications.,
Company Description Blueberry Semiconductors is a VLSI Design services company specializing in Design, Physical Implementation, Formal Verification, Design for Test (DFT), Verification and Silicon validation, FPGA Implementation, Rapid Prototyping, and embedded software and systems, including firmware verification. The company has employee-friendly policies that ensure high levels of employee satisfaction. The leadership team has extensive experience from large multinational companies and leading service providers. The Founders and Core team members are committed to transforming innovative concepts into silicon and leveraging the talent in India to elevate its status in the global semiconductor industry. Role Description Key Responsibilities Lead formal verification of complex IP-level RTL designs using property checking methodologies. Develop, code, and maintain System Verilog Assertions (SVA) for design properties. Build formal verification environments/testbenches from scratch and integrate with RTL designs. Dive deep into microarchitecture specifications , extract verification requirements, and craft formal test plans. Apply divide-and-conquer, abstraction, and complexity reduction techniques to tackle large designs effectively. Drive verification to closure with clear sign-off criteria . Collaborate with design teams and provide early bug detection and root-cause analysis using formal. Leverage and verify industry-standard protocols (AMBA AXI/AHB/APB, PCIe, USB, I2C, SPI, etc.). Mentor and coach engineers in formal verification tools, flows, and best practices, building team strength. What We're Looking For 4+ years of strong hands-on experience in Formal Verification at the IP level. Proficiency in System Verilog Assertions (SVA) . Proven track record of building formal verification testbenches from scratch. Ability to comprehend microarchitecture specs and map them into verification requirements. Skill in applying formal abstraction, modularization, and scalability techniques . Mandatory: Hands-on experience with at least one commercial formal verification tool (Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, OneSpin). Solid understanding of AMBA protocols and other high-speed/serial protocols. Strong communication and documentation skills. Passion for mentoring and enabling engineers to excel in formal verification. What's In It For You Be part of a newly formed consulting team specializing in Formal Verification. Learn directly from industry veterans and accelerate your technical depth. Opportunity to define methodologies and influence best practices in formal verification. Exposure to next-generation semiconductor designs and industry-leading IPs. A culture that celebrates innovation, ownership, and growth . Build a flourishing career path in one of the most in-demand and high-impact areas of VLSI verification. Qualifications Expertise in Formal Verification Strong Analytical Skills and Communication abilities Experience in Customer Service and Insurance Verification Able to lead a team and work collaboratively with cross-functional teams Experience in the semiconductor industry is a plus Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field