Front End Synthesis and Implementation Engineer

2 - 7 years

4 - 9 Lacs

Posted:3 days ago| Platform: Naukri logo

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Job Description

Front End Synthesis and Implementation Engineer - Job Description Front End Synthesis and Implementation Engineer
Join the India team of a cutting-edge, well-funded storage startup in Silicon Valley as the

Front End Engineer

responsible for implementing complex SoCs using ARM architecture. As a Front End Engineer, you will work on SoC RTL and its implementation and quality checks such as synthesis, lint, CDC, and other aspects of the SoC implementation process. You will be involved in checks and flow management for both high-performance, multi-million gate complex IPs and SoCs. You will also be responsible for Power, Performance, and Area (PPA) analysis and optimization, as well as ensuring implementation quality of the entire ASIC.

Requirements
  • Minimum BE/BS degree (Masters preferred) in Electrical/Electronics Engineering/VLSI.
  • 2+ years of practical experience in front end design implementation.
  • Strong fundamentals in digital ASIC design.
  • Understanding of IP and SoC design and implementation methodology and challenges.
  • Knowledge of one or more design flows such as Synthesis, Constraint Development and Verification, STA, Floorplanning, Lint, CDC, Low Power and UPF, Power Estimation, Formal Verification, ECO Implementation.
  • Hands-on expertise with industry-standard implementation and verification tools like Synopsys Design Compiler/Fusion Compiler, Formality/LEC, Spyglass Lint and CDC, VCLP, Power Explorer, PrimePower, Synopsys RTL Architect, Constraint Analyzer tools, Conformal ECO.
  • Proficiency in TCL and Perl scripting and flow automation.
  • Excellent communication and teamwork skills.

Responsibilities
  • Work on SoC and IP implementation methodology and flows to meet PPA goals.
  • Contribute to flow automation to enhance usability for design teams and improve development schedules.
  • Provide early feedback on design issues and propose solutions.
  • Collaborate with Backend teams to achieve PPA goals during PnR.
  • Work with IP and SoC Design teams to optimize designs for PPA targets.
  • Run and ensure all quality checks on IP and SoC RTL for first-pass success of ASIC.

Location
Bangalore, India

Contact
Email:

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