294 Asic Design Jobs

As a Senior Silicon Design Engineer (SMTS) at AMD, you will be an integral part of the GFX sub-system (Graphics Power Management) verification team. Your role will involve collaborating with lead architects and block design teams to understand the features to be implemented and verified. You will be responsible for developing robust test plans for both synthetic and real workload trace, debugging verification test failures, and ensuring that the design meets functional, performance, and power expectations. To excel in this role, you must have a strong background in ASIC design and be proficient in debugging Verilog RTL code using simulation/emulation tools. Your analytical thinking and problem-solving skills, attention to detail, and ability to work effectively with diverse teams will be crucial for success. Additionally, having good English communication skills, both verbal and written, is essential. Preferred qualifications for this position include a minimum of 12 years of experience in ASIC verification, proficiency in Verilog, System Verilog, UVM methodologies, and C/C++ programming. A solid academic background with a B.E/B.Tech or M.E/M.Tech degree in ECE/Electrical Engineering/Computer Engineering with Digital Systems/VLSI as a major is required. Candidates with graphics pipeline experience and deep knowledge of computer architecture will be given preference. Being a self-starter who can independently drive tasks to completion, while also possessing strong teamwork and interpersonal skills, is essential for this role. This position is based in Hyderabad, India. If you are looking to be part of a dynamic team that is dedicated to pushing the limits of innovation and solving the world's most important challenges, then AMD is the place for you. Join us in advancing technology and making a meaningful impact in the industry, communities, and the world.,

Eridu AI India Private Limited, a wholly owned subsidiary of Eridu Corporation, Saratoga, California, USA, is seeking highly motivated and talented professionals for its R&D center in Bengaluru. Eridu AI is a Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. The company introduces innovative solutions across semiconductors, software, and systems to enhance AI data center performance, increase GPU utilization, and reduce capex and power consumption. Led by a team of experienced Silicon Valley executives and engineers, Eridu AI's solution has been widely recognized by hyperscalers. We are currently looking for an RTL Design Director to lead our Networking IC team in Bengaluru. As a part of the Design Group, you will play a crucial role in defining, specifying, architecting, executing, and productizing cutting-edge Networking devices. This position offers a unique opportunity to shape the future of AI Networking and work on real-world problems. Responsibilities: - Lead the offshore RTL team and provide technical guidance. - Collaborate with Chip and System Architects to translate architecture requirements into microarchitecture and design implementation. - Conduct RTL coding, code reviews, and debugging. - Document microarchitecture and RTL subsystems. - Define development flows to enhance efficiency and quality. - Coordinate with other teams for successful RTL implementation. - Utilize domain experience in Ethernet, PCIe, and protocols for informed design decisions. Qualifications: - MS/BS degree with a minimum of 15+ years of experience. - Demonstrated success in tape-outs and productization, preferably in networking devices. - Ability to translate architecture-level descriptions into implementable designs with clear documentation. - Proficiency in addressing clock/reset/power domain challenges and safe design practices. - Experience in optimizing hardware for product performance. - Strong knowledge of industry tools and best practices for RTL development. - Understanding of networking protocols and ASIC design flow. - Familiarity with DFT and physical implementation requirements. Join us at Eridu AI to be a part of a world-class team working on groundbreaking technology that shapes the future of AI infrastructure. Your work will directly contribute to transforming data center capabilities and developing next-generation AI networking solutions. The starting base salary will be determined based on relevant skills, experience, qualifications, and market trends. For more information, visit our website at eridu.ai.,

This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; - Grade Specific Focus on Electrical, Electronics and Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers.

Challenging and Interesting work on building and enhancing Indias only completely open-source RISC-V based SHAKTI processors. Learn everything about the entire flow from spec to silicon. Work on state-of-the-art research topics and engineering efforts. Exposure to engage with foreign universities and support in preparation to pursue higher studies in India/Abroad. Exposure to engage with leading industry partners thereby improving your career trajectory and exposure. International Publications can also be achieved as part of tenure, boosting your research potential for higher studies. Required Skill Set Must have basic expertise in at least one of: verilog, vhdl, bluespec system verilog and/or chisel. Must have knowledge: digital design, pipelining Basic computer architecture knowledge, include one or more of : in-order cores, out-of-order cores, processors, caches, SoC development, memory architecture, etc. Good to have experience with FPGAs , performance modelling, workload analysis/benchmarking, python scripting, knowledge of peripheral and communication IPs

As part of a diverse team at Google, you will be working on developing custom silicon solutions for direct-to-consumer products. Your role will involve contributing to the innovation that drives products loved by millions globally, shaping the future of hardware experiences with a focus on performance, efficiency, and integration. You will specifically be involved in the development of a cutting-edge Application-specific integrated circuit (ASIC) aimed at accelerating machine learning computation in data centers. Working collaboratively with various teams such as architecture, verification, power and performance, and physical design, you will be responsible for specifying and delivering high-quality designs for next-generation data center accelerators. Your problem-solving skills will be put to the test as you tackle technical challenges using innovative micro-architecture and practical logic solutions, while evaluating design options with considerations for complexity, performance, power, and area. The Technical Infrastructure team at Google is responsible for the architecture that supports everything users see online. From maintaining data centers to building future Google platforms, this team plays a crucial role in enabling Google's product portfolio. As part of this team, you will be involved in defining and driving the implementation of physical design methodologies, taking ownership of design partitions or top-level, ensuring the closure of timing and power consumption aspects of the design, contributing to design methodology, libraries, and code reviews, as well as defining physical design-related rule sets for functional design engineers.,

Qualcomm India Private Limited is seeking a Hardware Engineer with expertise in complex high-performance RTL design, particularly on DSP or processor based sub-systems. You should be proficient in hardware design using Verilog, System Verilog, or VHDL and have knowledge of on-chip bus interface protocols like AXI, APB, and AHB. Experience in model development (SystemC, or C++), RTL to gates synthesis (Synopsys DCG or Cadence Genus), design rule and CDC checking (SVA assertions, Spyglass, 0-in), and working on high-performance low power RTL design is essential. Familiarity with scripting languages such as PERL, Python, TCL, C, etc., is also required. As a Hardware Engineer at Qualcomm, your responsibilities will include developing micro-architecture, designing and documenting specific ASIC modules, and sub-systems. You will own the RTL, ensuring its development, assessment, and refinement to meet power, performance, area, and timing goals. Troubleshooting architecture, design, or verification issues using sound ASIC engineering practices, and leveraging various design tools to enhance design quality will be part of your role. Additionally, you will collaborate with the design verification team to execute the functional verification strategy and contribute innovative ideas for IP core and process flow enhancements. The ideal candidate should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field with at least 2 years of Hardware Engineering experience. Alternatively, a Master's degree with 1+ years of relevant experience or a PhD in a related field will also be considered. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. Reasonable accommodations can be requested by emailing disability-accommodations@qualcomm.com or calling Qualcomm's toll-free number. The company expects all employees to adhere to applicable policies and procedures, including those related to security and protection of confidential information. Please note that Qualcomm's Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies are not authorized to use the site for submissions. Unsolicited resumes or applications from agencies will not be accepted. For further information about this role, reach out to Qualcomm Careers directly.,

As an ASIC Design Engineer at our Bangalore location, you will join a dynamic team focused on delivering high-speed ASICs for complex systems. Your role will involve defining and architecting high-performance blocks, conducting micro-architecture and logic design, collaborating with verification and physical design teams, and ensuring maximum throughput with minimal power consumption. Your expertise in Verilog RTL coding, knowledge of tools like Synopsys Design Compiler and Verplex LEC, experience in networking ASIC design, familiarity with memory subsystems, clock synchronization, and serial interfaces, as well as strong problem-solving and debugging skills will be essential. Effective communication and leadership abilities are key for success in this role. A Master's or Bachelor's degree in Electrical Engineering is required, along with a minimum of 5 years of experience in ASIC design.,

You are a highly experienced RTL Design Engineer with 12-20 years of experience, specializing in PCIe IP development. Based in Noida/Bangalore, you will be responsible for designing and supporting the RTL of Cadence's PCIe IP solution. Your role will involve working with existing RTL, adding new features, ensuring customer configurations are clean, supporting customers, and ensuring design compliance with LINT and CDC guidelines. To qualify for this position, you must hold a BE/BTech/ME/MTech degree in Electrical/Electronics/VLSI and have extensive experience as a design and verification engineer, with a focus on RTL design using Verilog. Additionally, you should have experience with System Verilog, UVM-based environments, AXI3/4/5, and preferably PCIe. Previous experience in RTL design of complex protocols and IP development teams is highly advantageous. As a member of the Cadence High-Speed SerDes PHY IP Front end Design team, you will be responsible for defining microarchitecture, leading ASIC design, collaborating with cross-functional teams, mentoring junior members, and fostering a high-performance team culture. Requirements for this role include a Bachelor's degree in Electronics Engineering with at least 7 years of experience, a Master's degree with 5 years, or a Ph.D. with 2 years in Digital Design. You should have hands-on experience in micro-architecting digital blocks, RTL implementation in Verilog/SV, SDC definition, STA, Lint Checks, CDC, and Synthesis. Knowledge of protocols such as Ethernet, USB, PCIe, MIPI(DPHY), and HDMI/Display is desired, along with the ability to work closely with Analog design teams and develop high-speed critical digital circuits and signal processing blocks.,

Job Summary: Seeking an experienced FPGA developer to join our team and work on the design and development of complex FPGA-based systems. The ideal candidate will have a strong background in FPGA design, verification, and implementation, as well as experience working with hardware and software engineers to integrate FPGA designs into larger systems.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. About The Role As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Additional About The Role Additional About The Role Job Role * Work with multiple SOC Design teams to rollout robust Logic Synthesis, UPF synthesis, QoR optimization and netlist Signoff flows* Provide implementation flows support and issue debugging services to SOC design teams across various site* Develop and maintain 3rd party tool integration and product enhancement routines * Should lead implementation flow development effort independently by working closely with design team and EDA vendors * Should drive new tool evaluation, methodology refinement for PPA optimization Skill Set * Proficiency in Python/Tcl * Familiar with Synthesis tools (Fusion Compiler/Genus), * Fair knowledge in LEC, LP signoff tools* Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking* Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus* Should be sincere, dedicated and willing to take up new challenges Experience 13+ years of experience in RTL,UPF & Physical aware Synthesis for cutting edge technology nodes, logic equivalence checking, Scripting and Netlist Timing Signoff Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Job Responsibilities Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 4+ years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Minimum 4+ years of experience in PD Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: General Summary: Qualcomm is the world's leading developer of next generation of always on Display technologies and is committed to building a world-class organization that will lead the industry. Be part of the team developing next generation Display subsystems and Display peripherals. The ASIC Systems Architect is responsible for system architecture definition activities supporting a sophisticated multimedia Low Power Display subsystem catering to various market segments like mobile, XR, compute, IOT, Wearables and automotive products. Candidates will be responsible for all aspects of the ASIC hardware architecture definition/validation including the following: Owning end to end system architecture Capturing detailed technology requirements working closely with product, hardware and software engineering teams for deriving subsystem hardware specification. Engage with all stakeholders and collaborate with cross functional teams to define robust architecture Defining architecture validation plans and reviewing development results Optimization and debug via modelling, system simulation and testing across key criteria including power and performance. Collaborating, reviewing and enabling design and system teams to execute independently from the specifications Engage and provide support from Concept to Commercialization, Post-silicon commercialization support and customer engineering documentation Defining and patenting novel architectures that drive industry leadership. Job Function: Oversees hardware architecture for ASIC systems development for a variety of products. Determines architecture design, and validation via system simulation. Defines module interfaces/formats for simulation. Ability to analyze and solve complex problems through various mechanisms. Ability to optimize architecture for Area, Performance and power efficiency. Evaluates all aspects of the HW architecture flow from high-level development to validation and review. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. Uses System tools, such as, MathWorks MATLAB, SIMULINK, VISIO and other toolboxes. Uses language such as HDL, C/C++, System C, Perl, Python. Provides technical expertise for next generation initiatives. Leverages experience in image processing, SoC hardware and computer architecture concepts to develop proposals to address system Display requirements using processor, memory, bus and low-power design techniques. Uses expertise in low-power design methodology, optimization and validation using various CAD tools and design techniques to optimize system power. Leverages experience in digital system performance analysis and systems modelling to ensure performance goals met. Leverages Verilog/VHDL and digital hardware design tools such as Synopsys/Cadence/Mentor ASIC design and simulation tool sets, power analysis and simulation, scripting languages (Python, Perl, TCL, C, etc.) to optimize system. Effectively utilizes advanced problem solving and ASIC engineering practices to resolve complex architecture, design, or verification problems. Writes technical documentation and provides technical expertise for design or project reviews and project meetings. Acts as a tech lead on small to large projects and owns team deliverables of the project Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum Qualifications: Bachelor's degree in, Electronics/Computer Science Engineering, or related field and 7+ years of ASIC design, verification, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, or related work experience. OR PhD in Science, Engineering, or related field. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 10-15 years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience Education Requirements RequiredBachelor's, Electrical Engineering or equivalent experiencePreferredMaster's, Electrical Engineering or equivalent experience Keywords Innovus, FC, UPF, STA, Formal Verification, Genus, Primetime, Tempus, SOD Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: About The Role Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in. You will be joining a successful engineering team whose deliveries can be found in billions of mobile, compute and IoT products worldwide. Based out of Qualcomm's Bangalore office, this role offers a position in Low Power controller IP cores and subsystem digital design targeted for variety of industry leading Snapdragon SoCs for mobile, compute, IoT and Automotive markets. Key Responsibilities Micro-architecture and RTL design for Cores / subsystems. Work in close coordination with Systems, Verification, SoC, SW, PD & DFT teams for design convergence. Enable SW teams to use HW blocks. Qualify designs using static tool checks including Lint, CDC, LEC and CLP. Synthesis, LEC and Netlist CLP Report status and communicate progress against expectations. Preferred Qualifications 4 to 10 years of strong experience in digital front end design (RTL design) for ASICs Expertise in RTL coding in Verilog/SV/VHDL of complex designs with multiple clock domains and multiple power domains Familiar with UPF and power domain crossing Experience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI Experience in low power design methodology and clock domain crossing designs Experience in Spyglass Lint/CDC checks and waiver creation Experience in formal verification with Cadence LEC Understanding of full RTL to GDS flow to interact with DFT and PD teams Expertise in Perl/TCL/Python language Experienced in database management flows with Clearcase/Clearquest. Expertise in post-Si debug is a plus Excellent oral and written communications skills to ensure effective interaction with Engineering Management and team members. Team player, self-motivated, should be able to work with minimal supervision. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve Delivering an experience-first, AI-Native Network pivots on the creativity and commitment of our people It requires a consistent and committed practice, something we call the Juniper Way ASIC Engineer Design Silicon Systems Technology Group (SST) seeks ASIC Design Engineers to develop next generation of ASICs for new core routers, switches, and firewalls Opportunity Snapshot: We are looking to hire sharp ASIC Design Engineer with excellent communication and leadership skills You will be part of a fast paced team responsible for delivering high-speed ASICs for large, complex systems You will have a significant opportunity to interact with system design teams across geographies Open communications, empowerment, innovation, teamwork and customer success are the foundations of the team with "pay for performance" culture Thus, you set your own limits for learning, achievements and rewards Responsibilities: Define and architect high-performance blocks for the latest, most advanced networking ASICs Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power Collaborate with the verification team in the development of the testplan and assist in debugging test failures Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes Required Skills: 5+ years of ASIC design experience Strong Verilog RTL coding skills Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus Knowledge of high performance memory subsystems Knowledge of multi-domain clock synchronization and high-speed serial interfaces Strong problem solving and ASIC debugging skills Excellent written and verbal communications skills MSEE or BSEE is required

As an Applications Engineer (AE) at Synopsys, you will play a crucial role in driving innovation and shaping the future in the Era of Pervasive Intelligence. You will have the opportunity to work with high-end customers in the Mobile Industry Processor Interface (MIPI) domain, providing top-tier technical support and guidance with your strong technical background in ASIC design. Your role will involve partnering with customers through the full cycle of ASIC design, conducting reviews on major design milestones, and ensuring successful integration of Synopsys MIPI IP solutions into customers" SoCs. Your impact will be significant as you enhance customer satisfaction by providing expert support, drive innovation through collaboration on cutting-edge SoC designs, and contribute to the development of industry-leading IP solutions. You will expand Synopsys" market presence in the MIPI domain and support the growth of Synopsys" IP portfolio by addressing customer needs and promoting the adoption of Synopsys IP through impactful documentation. To succeed in this role, you will need a Bachelor's degree with 5+ years or a Master's degree with 2+ years of relevant experience in the ASIC design process. Proficiency in Verilog HDL, synthesis, simulation, and verification is required, and knowledge of Place and Route, Design Reuse, Physical Design, or Analog Design is a plus. Familiarity with MIPI UFS/UniPro protocols, high-speed SERDES, or parallel interfaces is advantageous, as well as experience with Synopsys tool suites. Strong verbal and written communication skills in English are essential. As an Applications Engineer at Synopsys, you will join a dedicated and innovative team focused on supporting customers in the Synopsys Intellectual Property (IP) domain. You will have the opportunity to collaborate with a customer-centric approach, drive customer success, and advance the capabilities of Synopsys IP solutions. Synopsys offers a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process. If you are an excellent communicator, a problem solver who thrives in a dynamic environment, a collaborative team player with a passion for technology and continuous learning, then you are the perfect fit for this role.,

We are hiring RTL Design Engineers with strong expertise in developing high-performance digital designs for ASIC/SoC products. Contact-7982405927

Were hiring a talented RTL Design Engineer to join our team in Hyderabad and contribute to advanced ASIC/SoC projects. Key Responsibilities: Perform RTL integration for ASIC/SoC designs Debug CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) violations Analyze and resolve timing and CLP (Clock Level Planning) issues Apply strong digital design fundamentals in RTL development Tackle complex design problems with excellent debugging skills Requirements: 3+ years of experience in RTL design and integration Solid foundation in digital logic design Strong problem-solving and debugging abilities

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: ASIC Design. Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: ASIC Synthesis. Experience: 3-5 Years.

ASIC RTL DESIGN ENGINEER (4 to 10 Years) IP/SoC Design Company: ACL Digital (Wafer space Semiconductor) Location [Bangalore/Pune/Chennai/Noida] Experience: 4 to 10 Years Openings: 6 Positions Job Description Sr RTL Design Engineer We are seeking a seasoned RTL Design Engineer with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in designing state of the art solutions for automotive camera and display systems. Responsibilities Microarchitecture definition and RTL implementation ensuring optimal performance, power, area. Collaborate with software teams to define configuration requirements, verification collaterals etc. Work with verification teams on assertions, test plans, debug, coverage etc. Proficiency in Verilog/System Verilog Very google understanding of ASIC design methodologies Qualifications and Preferred Skills Graduate/Post Graduate/PhD in Electrical/Electronics 4-10 years hands-on experience in microarchitecture and RTL development Proficiency in developing micro-architecture from the design requirements, defining the H/W- S/W interface. In-depth understanding of MIPI CSI and DSI protocols Experience designing IP blocks for video and audio design Proficiency in Verilog, System Verilog Familiarity with industry-standard EDA tools and methodologies Experience with large high-speed, pipelined, and low power designs Excellent problem-solving skills and attention to detail Strong communication and collaboration skills Experience in designs complying to automotive functional safety will be a plus

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive design optimizations to improve QoR. Block/Partition signoff closure for STA, PV, LEC, IR/EM, CLP very efficiently. Provide technical leadership and guidance to the physical design team, mentoring junior engineers and fostering a culture of excellence. Work closely with RTL design and DFT teams to understand design requirements and constraints, and drive successful tapout of designs. Support and Development of advanced physical design methodologies and flows for complex semiconductor designs. Requirements Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. 4+ years of experience in physical design of ASICs Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics for Synthesis, PnR, Signoff Closure. Extensive experience with timing closure techniques, power optimization. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Expertise in Synthesis that includes details understanding of RTL, Early PnR timing issues, Constraint issue, design issues. Experience in handling Partitions and blocks for size estimation, pin assignment, CTS. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration. Detailed Knowledge on Clocking methodology and various techniques to improve skew, latency, timing, power. Familiarity with low-power design techniques and methodologies, such as multi-voltage domains and power gating using UPF. Expertise in physical verification, including DRC, Antenna, LVS, PERC, and ERC checks. Expertise in Timing Closure including setup, hold, DRV, SI, Interface issues. Experience with formal verification for RTL to Netlist and Netlist to Netlist. Knowledge of emerging technologies such as machine learning and AI for design automation and optimization.

Qualcomm India Private Limited is a leading technology innovator that strives to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems. This involves working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams is essential to meet performance requirements and develop innovative solutions. To qualify for this position, you should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field along with 4+ years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years or a PhD with 2+ years of relevant work experience would be considered. We are seeking bright ASIC design engineers with strong analytical and technical skills to be part of a dynamic team responsible for delivering Snapdragon CPU design for Mobile, Compute, and IOT markets. Key responsibilities include participating in ASIC development projects, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will be involved in creating design experiments, conducting PPA comparison analysis, and collaborating closely with RTL design, Synthesis, low power, Thermal, Power analysis, and Power estimation teams to optimize Performance, Power, and Area (PPA). Additionally, developing Place & Route recipes for optimal PPA, tabulating metrics results for analysis, and contributing to the ASIC flow with low power, performance, and area optimization techniques are crucial aspects of this role. The ideal candidate should have 10-15 years of High-Performance core Place & Route and ASIC design Implementation work experience. Proficiency in Place & Route with FC or Innovus, experience with STA using Primetime and/or Tempus, and strong problem-solving skills are preferred qualifications. Knowledge in constraint generation and validation, power domain implementation, formal verification, scripting languages like Perl/Tcl, Python, C++, as well as exposure to Verilog coding and CPU micro-architecture will be advantageous. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com. The company's work environment is inclusive and supportive of individuals with disabilities. Applicants should adhere to all relevant policies and procedures, including security measures and confidentiality of company information. Qualcomm does not accept unsolicited resumes or applications from staffing agencies. For more information about this role, please reach out to Qualcomm Careers.,

. Location: Bangalore/Kolkata Experience: 3+ years Opportunity Snapshot: We are looking to hire sharp ASIC Design Engineer with excellent communication and leadership skills. You will be part of a fast paced team responsible for delivering high-speed ASICs for large, complex systems. You will have a significant opportunity to interact with system design teams across geographies. Open communications, empowerment, innovation, teamwork and customer success are the foundations of the team with "pay for performance" culture. Thus, you set your own limits for learning, achievements and rewards. Responsibilities: Define and architect high-performance blocks for the latest, most advanced networking ASICs Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power Collaborate with the verification team in the development of the testplan and assist in debugging test failures Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes Required Skills: 3+ years of ASIC design experience Strong Verilog RTL coding skills Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus Knowledge of high performance memory subsystems Knowledge of multi-domain clock synchronization and high-speed serial interfaces Strong problem solving and ASIC debugging skills Excellent written and verbal communications skills MSEE or BSEE is required WHERE WILL YOU DO YOUR BEST WORK

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers.Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLLAdditional responsibilities:logic (RTL) design, timing closure, CDC analysis etc.Understand and Design Power efficient logic.Agile project planning and execution.RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Minimum 8+ years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Verilog