As the Lead Verification Engineer at a cutting-edge storage startup in Silicon Valley, you will be responsible for tackling IP and SoC level verification challenges within a Multi-core, complex, high-performance ASIC environment. Your role will involve understanding internal requirements and complexities of the SOC, designing verification methodologies, environments, and test plans, and collaborating with the design team to ensure high-quality verification for first-pass success of the SoC. Located in Bangalore, KA, India, you should hold a BA/BS degree in Electrical/Electronics Engineering with over 10 years of practical experience. Strong fundamentals in digital ASIC design and verification, expertise in ARM cores and related infrastructure, familiarity with AMBA bus protocols, and experience with Verilog, SystemVerilog, UVM, and other verification tools are essential. Knowledge of major SOC interfaces like PCIE, DRAM, Flash, I2C, SSP, and UART is desirable, along with an understanding of IP designs and verification requirements. Your responsibilities will include defining and developing verification methodologies and test plans based on functional coverage, project management, contributing to IP and SoC verification, collaborating with the design team for design quality improvement, mentoring team members, and establishing processes for verification and quality improvements. Additionally, you will be involved in Gate Level Simulations (GLS), emulation, FPGA-based, and Post Si validation. To excel in this role, you must possess excellent communication and leadership skills to lead a team of verification engineers effectively. Your ability to review test plans, verification tests, and coverage for team members, as well as your strong test creation, debugging capabilities, and functional coverage understanding, will be critical for the success of the projects.,
As a Senior SoC/Staff SoC Design Engineer at the cutting-edge storage startup in Silicon Valley, your primary role will be to design complex SoC using ARM architecture. You will be responsible for contributing to SoC architecture for a multi-core ARM SOC, defining SoC microarchitecture and design, and designing and implementing the CPUSS subsystem. Additionally, you will work closely with the emulation and firmware teams to debug silicon functional issues and integrate various IPs and interface components into the SoC. Your tasks will also include RTL simulation, synthesis, lint, CDC checks, and assisting in emulation, FPGA, and prototyping efforts. Key Responsibilities: - Contribute to SoC architecture for a multi-core ARM SOC - Define SoC microarchitecture and design - Design and implementation of the CPUSS subsystem - Work closely with emulation and firmware teams for debugging - Design clock-reset architecture and RTL implementation - Integrate all IPs into the SoC - Collaborate with the verification team for complete SoC verification - Perform RTL simulation and debug - Conduct synthesis, lint, CDC checks - Assist in emulation, FPGA, prototyping efforts Qualification and Mandatory Skillset Requirements: - Minimum BE/BS degree in Electrical/Electronic Engineering/VLSI (Masters preferred) with 5 to 10 years of practical experience - Strong fundamentals in digital ASIC design - Expertise in ARM v8 and v9 specifications and their impact on SoC system architecture - Multiple project experience with ARM-based ecosystem components - Familiarity with AMBA bus protocols, system memory hierarchy, system debug infrastructure, and multi-core SOC designs - Exposure to ARM platform architecture specifications - Strong experience with Verilog, SystemVerilog, DC/DC-T based synthesis, constraints development, and RTL level checks - Understanding of major SOC interfaces like PCIE, DRAM, Flash, I2C, SSP, UART - Capable of working with multiple IP vendors and other teams - Excellent communication and leadership qualities to lead the design team,
As the Verification Lead Engineer at the India team of a cutting-edge storage startup in Silicon Valley, you will be responsible for taking on IP and SoC level verification challenges. Your role will involve understanding the internal requirements and complexities of the SOC, architecting the verification environment and solutions, and designing the SoC and IP verification methodology, environment, test plan, and tests. Collaboration with the design team will be essential to ensure high-quality verification for the first pass success of the SoC. **Key Responsibilities:** - Define and develop verification methodology, environment, and test plans driven by functional coverage - Project management including building schedules, optimizing critical paths, managing resource allocation, and driving team execution to achieve project goals - Contribute to IP and SoC verification - Work closely with the design team to improve design quality through verification - Review test plans, verification tests, and coverage for other team members - Mentor team members for technical growth in verification - Establish processes for verification and quality improvements - Contribute to Gate Level Simulations (GLS), emulation, FPGA-based, and Post Si validation **Qualifications Required:** - BA/BS degree in Electrical/Electronics Engineering with 10+ years of practical experience - Strong fundamentals in digital ASIC design and verification - Expertise in ARM cores and related infrastructure (Coresight, NIC/NOC, bus interconnects, etc.) - Familiarity with AMBA bus protocols, system memory hierarchy, system debug infrastructure, and multi-core SOC - Strong experience with Verilog, SystemVerilog, UVM, and/or other verification methodologies - Understanding of major SOC interfaces like PCIE, DRAM, Flash, I2C, SSP, UART - Understanding of IP designs and verification requirements - Strong test creation, debug capability, and functional coverage understanding - Understanding of Gate Level Simulations (GLS) with timing and related debug capability - Excellent communication and leadership qualities to mentor and lead a team of verification engineers Location: Bangalore, KA, India Join this dynamic team to drive innovation and make significant contributions to the verification process of high-performance ASICs.,
Title: SoC Design Position: Senior SoC/Staff SoC Design Engineer -CPUSS Location: Bangalore, KA. India Company and Candidature Brief: Join the India team of most cutting-edge and well-funded storage startup in Silicon Valley as the Sr/Staff SOC Design Engineer responsible for designing complex SOC using ARM architecture. As a Sr/Staff SOC Design Engineer with a focus on ARM Ecosystem Components and Architecture, you will work to understand the internal requirements and complexities of our SOC system and architect the SoC. You will help design the SoC RTL, Integrate IPs and define top level logic. You will also work with verification team to make sure that high quality verification is achieved for first pass success of SoC. You will also participate in architecture/product definition through early involvement in the product life cycle. For a detailed information about us visit the company website:www.scaleflux.com Roles And Responsibilities Contribute to SoC architecture for a multi-core ARM SOC Define SoC micro architecture and design Design and implementation of CPUSS subsystem Working closely with the emulation and firmware teams to debug silicon functional issues. Build SoC around key ARM subsystem components and other IPs including various interfaces Design of clock-reset architecture and RTL implementation Integration of all IPs into SoC Work with verification team for complete SoC verification, review test plans RTL Simulation and debug Synthesis, Lint, CDC checks Assist in emulation, FPGA, prototyping efforts Qualification and Mandatory Skillset Requirements: Minimum BE/BS degree (Masters preferred) in Electrical/Electronic Engineering/VLSI with 5 to 10 years of practical experience Strong fundamentals in digital ASIC design Expertise in ARM v8 and v9 specifications and their impact to SoC system architecture Multiple project experience with ARM based ecosystem components (A-series ARM Cores, SMMU, GIC, Coresight, NIC and other complex bus interconnects) Familiarity with AMBA bus protocols, system memory hierarchy, system debug infrastructure and multi-core SOC designs Exposure to ARM platform architecture specifications Strong experience with Verilog, SystemVerilog, DC/DC-T based synthesis, constraints development and RTL level checks. Low power methodology knowledge will be a plus. Understanding of major SOC interfaces like PCIE, DRAM, Flash, I2C, SSP, UART. Capable of working with multiple IP vendors and other teams Excellent communication and leadership quality to lead design team