As the Lead Verification Engineer at a cutting-edge storage startup in Silicon Valley, you will be responsible for tackling IP and SoC level verification challenges within a Multi-core, complex, high-performance ASIC environment. Your role will involve understanding internal requirements and complexities of the SOC, designing verification methodologies, environments, and test plans, and collaborating with the design team to ensure high-quality verification for first-pass success of the SoC. Located in Bangalore, KA, India, you should hold a BA/BS degree in Electrical/Electronics Engineering with over 10 years of practical experience. Strong fundamentals in digital ASIC design and verification, expertise in ARM cores and related infrastructure, familiarity with AMBA bus protocols, and experience with Verilog, SystemVerilog, UVM, and other verification tools are essential. Knowledge of major SOC interfaces like PCIE, DRAM, Flash, I2C, SSP, and UART is desirable, along with an understanding of IP designs and verification requirements. Your responsibilities will include defining and developing verification methodologies and test plans based on functional coverage, project management, contributing to IP and SoC verification, collaborating with the design team for design quality improvement, mentoring team members, and establishing processes for verification and quality improvements. Additionally, you will be involved in Gate Level Simulations (GLS), emulation, FPGA-based, and Post Si validation. To excel in this role, you must possess excellent communication and leadership skills to lead a team of verification engineers effectively. Your ability to review test plans, verification tests, and coverage for team members, as well as your strong test creation, debugging capabilities, and functional coverage understanding, will be critical for the success of the projects.,
