50 Lec Jobs

You should have 3+ years of experience in RTL, UPF & Physical aware Synthesis for cutting-edge technology nodes, logic equivalence checking, Scripting, and Netlist Timing Signoff. Proficiency in Python/Tcl is required. You should be familiar with Synthesis tools such as Fusion Compiler/Genus and have fair knowledge in LEC, LP signoff tools. Proficiency in VLSI front-end design steps including Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking is essential. Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus. You should be sincere, dedicated, and willing to take up new challenges. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Qualcomm is an equal opportunity employer that provides reasonable accommodations for individuals with disabilities during the application/hiring process. If you require accommodations, you may contact Qualcomm at disability-accommodations@qualcomm.com. Qualcomm expects its employees to adhere to all applicable policies and procedures, including security and confidentiality requirements regarding Company confidential information and other proprietary data. Please note that Qualcomm's Careers Site is for individuals seeking jobs at Qualcomm. Staffing and recruiting agencies are not authorized to use this site for submissions. Qualcomm does not accept unsolicited resumes or applications from agencies. For more information about this role, kindly contact Qualcomm Careers. 3074295,

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the worlds leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of whats next in electronics and the world. Job Description Location: NOIDA Exp-7-15Y We are seeking a highly skilled & experienced Synthesis & Static Timing Analysis (STA) expert to join our Flows & Methodologies Team. This role requires strong analytical skills, attention to detail, and the ability to work collaboratively with cross-functional teams. Proficiency in relevant EDA tools and a solid understanding of digital design principles are essential for success in these positions Scope Of Responsibilities As part of the Design Enablement team of the organization, you need to work closely with SoC cross functional teams to develop and define Synthesis & STA flow & methodology to meet SoC & IP level objectives on low geometry nodes (3/5/16nm) Your scope of work will cover tools and flows definition, requirement management for SoC designs You will work with EDA Vendors to proactively review latest tools and flows offerings in Synthesis & STA domains. Evaluate latest offerings and benchmark with organization used tools, flows, and methodologies. You will be an actor of change for deploying new tools & methodologies across the organization Qualifications Bachelor or Master or Ph.D. in Electronics Engineering and specialization in VLSI domain Good understanding of RTL, Synthesis, LEC, VCLP, Timing Constraints, UPF, Timing Closure & Signoff Experience with EDA tools like Genus, Fusion Compiler, Primetime, Tempus, Conformal Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Can do attitude,?openness to new environment, people and culture Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus Ability to work independently and as part of a team Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier . As the industrys leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, To Make Our Lives Easier . At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make peoples lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark Join Renesas. Lets Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Show more Show less

Strong on Digital Design, SV, UVM. Hands-on experience in any of the DV protocols like PCIe, USB 3.0, DDR 3/4/5, AMBA, Ethernet (10G/100G), SATA, and MIPI (CSI/DSI), UFS, CXL Also Hiring PD, RTL, DFT Apply& Share resume to mansoor@hisoltech.com

You have an exciting opportunity to join a dynamic team at MarvyLogic in Bengaluru/Bangalore. With over 10 years of experience in ASIC RTL Design and a Graduate Degree in Electrical/Electronics Engineering (Post Graduate degree is a plus), you will be a valuable addition to our team. As a member of our team, you will be responsible for various tasks related to ASIC RTL Design. Your expertise in Verilog/System Verilog proficiency, experience with multiple clock and power domains, and integration and validation of high-speed PCIe IP core will be crucial. You will also need familiarity with PCIe protocol analyzers and debug, as well as PCIe driver and application software for Linux/Windows. Your role will involve RTL Design and implementation of interface logic between PCIe controller and DMA engines for high-performance networking applications. You will be creating block-level micro-architecture specifications, reviewing vendor IP integration guidelines, and running integrity check tools to ensure compliance throughout the design flow. In addition to your technical responsibilities, you will also need to work and communicate effectively with multi-site teams. Your experience in ASIC product life cycle, including requirements, design, implementation, test, and post-silicon validation, will be essential in this role. If you are passionate about technology solutions and enjoy working in a collaborative environment, we encourage you to apply for this position. Join us at MarvyLogic and be a part of building futuristic and impactful solutions that make a difference in various industries. Your experience with emerging technologies and your contributions to our team may help you evolve both professionally and personally, leading to a more fulfilling life.,

You are invited to apply for the position of "ASIC RTL Engineer" at Semi Leaf consulting Service located in Bangalore. With 3-8 years of experience, if you are available to join within 30 days and prefer working in a WFO mode, this opportunity might be just for you. As an ASIC RTL Engineer at Semi Leaf, your responsibilities will include working on ASIC RTL design, RTL Logic Synthesis, LEC, Conformal, ECO, FC Check, and having proficiency in either TCL or Python. You must have Synthesis or Implementation experience, familiarity with the Linux environment, excellent communication skills, and experience with at least one serial protocol like UART, I2C, SPI. Skills with SOC Architecture, experience in CDC and Lint, and working on Cortex-M4 core/Sub-system verification/execution environment bring-up are desirable. Additionally, you should be able to develop verification infrastructure for Cortex-M4 Core/Sub-system bring-up, have knowledge of Coresight/Functional Debug architecture, and expertise in UVM/SV knowledge to develop scoreboard/checkers. If you are interested in this opportunity and possess the required experience, kindly share your updated resume with vagdevi@semi-leaf.com. Referrals are also highly appreciated. Join us at Semi Leaf consulting Service and be part of a team of experts dedicated to finding candidates with specialized skills in Semiconductor/VLSI/EDA & Embedded domains.,

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Responsibilities Defining chip and macro level power domains System Level Power Modeling Mixed signal power analysis Power Island/Power Gating/Power Isolation Structural Low power design of level shifter and isolation cell topology and associated rules Architectural analysis and development of digital power optimization logic/circuits/SW Work with Power Management IC developers for power grid planning Creating detailed architecture and implementation documents Education Requirements RequiredBachelor's, Computer Engineering and/or Electrical Engineering PreferredMaster's, Computer Engineering and/or Electrical Engineering Work with cross-functional teams on SoC Power and architecture for mobile SoC ASICs. Skills/Experience At least 4-12 years of experience are required in the following areas Low power intent concepts and languages (UPF or CPF) Power estimation and reduction tools (PowerArtist/PTPX,Calypto) Power dissipation and power savings techniques- Dynamic clock and voltage scaling Power analysis (Leakage and dynamic) and thermal impacts Power Software features for power optimization Voltage regulators including Buck and Low Drop out ASIC Power grids and PCB Power Distribution Networks Additional skills in the following areas are a plus: Mobile Baseband application processors chipset and power grid understanding UPF-based synthesis and implementation using Design Compiler Structural low power verification tools like CLP or MVRC Outstanding written and verbal communication skills Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Synthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation. Development of signoff quality constraints and the development of power intent constraints. May also include running RTL Lint, CLP, MEMBIST, DFT DRC etc. TCL script development in addition to running/analyzing/debugging designs. Hands on with Synopsys DCG/Genus/Fusion Compiler. Hands on with Synopsys Prime Time including constraint development for complex blocks with multiple clock domains. Hands on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development Experience with either RTL development or Physical Design is also a plus 6+ years experience Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

THE ROLE: The focus of this role is to execute the front end implementation of sub-blocks or IP. This involves ownership of synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure. Co-ordinate with design team and PNR teams. KEY RESPONSIBILITIES: Responsible for front end implementation of IPs which includes synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure Collaborate with designer and PNR teams to achieve closure. Execute as per schedule. Complete quality delivery for synthesis and timing closure. Debug and resolve technical issues PREFERRED EXPERIENCE: Experienced in synthesis and timing closure Good to have experience in LEC, CLP Have handled blocks with complex designs, high frequency clocks and complex clocking complete understanding of timing constraints, low power aspects and concepts of DFT Have debug experience to solve issues. scripting and automation ACADEMIC CREDENTIALS: Bachelors with 2 years of experience or Masters degree with 1 years of experience in Electrical Engineering

The culture at MarvyLogic is defined by its people. We foster a culture of passion for technology solutions that have a direct impact on businesses. We prioritize the pursuit of individual passions among our employees. Working with us offers you the opportunity to gain a comprehensive understanding of various industries and cutting-edge technologies. This exposure enables us to develop solutions that are not only forward-thinking but also highly impactful. Being a part of MarvyLogic can facilitate your personal growth, leading you towards a more fulfilling life. You should possess a Graduate Degree in Electrical/Electronics Engineering with over 10 years of experience (a post Graduate degree would be an added advantage). The job location is in Bengaluru/Bangalore. As a candidate for this position, you are expected to have a minimum of 10 years of experience in ASIC RTL Design and demonstrate proficiency in Verilog/System Verilog. Your expertise should extend to working with multiple clock and power domains. You should have a strong background in integrating and validating high-speed PCIe IP cores, including controllers and PHY SerDes. Experience with PCIe protocol analyzers and debugging is essential, as well as familiarity with PCIe driver and application software for both Linux and Windows environments. Your responsibilities will include RTL design and implementation of interface logic between PCIe controllers and DMA engines for high-performance networking applications. You will be required to create block-level micro-architecture specifications detailing interfaces, timing behavior, design tradeoffs, and performance objectives. Additionally, you will need to review vendor IP integration guidelines and ensure compliance throughout the design process. Running integrity check tools such as Lint/CDC/DFT/LEC/UPF to meet coding and implementation standards will also be part of your role. You will play a crucial role in the design verification process by reviewing test plans, coverage reports, writing assertions, and implementing design modifications to enhance verification quality. Furthermore, you will be involved in the physical implementation process by providing synthesis constraints, timing exceptions, and making design updates to achieve area, power, and performance targets. Key Responsibilities: - Collaborate effectively with multi-site teams - Conduct reviews of FPGA netlist releases (block/chip) - Demonstrate experience in the full ASIC product life cycle, including requirements, design, implementation, testing, and post-silicon validation.,

You should have 2-3 years of experience in STA & Synthesis engineering. The position is based in Hyderabad. It is essential that you possess expertise in AMD TB flow for at least 2 years. Proficiency in scripting languages like tcl, python, and perl is required. You should have a good understanding of synthesis, static timing analysis (STA), logic equivalence checking (LEC), and constraint logic programming (CLP). As part of the role, you should be able to independently debug issues and effectively communicate the root cause along with the solution. If you meet these requirements and are interested in this opportunity, please send your updated resume to janagaradha.n@acldigital.com.,

As a qualified candidate for this role, you should possess a Bachelor's degree in Electrical Engineering or a related field, or demonstrate equivalent practical experience. Additionally, you should have at least 3 years of hands-on experience with Front-End CAD tools and a proven track record of writing production scripts using languages such as Python or TCL. Ideally, you would hold a Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field. It would be advantageous to have a deep understanding of Institute of Electrical and Electronics Engineers (IEEE) Unified Power Format (UPF) standards, as well as knowledge in Machine Learning (ML) based acceleration and Register-Transfer Level (RTL) concepts including connectivity, feedthroughs, re-partitioning, UPF, and Local Enhanced Content (LEC). Joining our team means being part of a collective effort to innovate and create custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will be instrumental in shaping cutting-edge hardware experiences that are enjoyed by millions globally. At Google, we strive to organize the world's information and make it universally accessible and useful by leveraging the synergy of AI, Software, and Hardware technologies. In this role, your responsibilities will include developing methodologies for various front-end tasks, collaborating closely with front-end teams to address requirements effectively, coordinating with cross-functional domains to facilitate the development and deployment of Computer Aided Design (CAD) solutions, advocating for enhancements from electronic design automation (EDA) vendors to cater to Google's custom needs, and partnering with EDA and verification teams to pioneer new industry solutions.,

As a VLSI Design Engineer at Kinara, you will be part of a dynamic team focused on edge AI technology, pushing the boundaries of what's achievable in machine learning and artificial intelligence. You will contribute to the development of state-of-the-art AI processors and high-speed interconnects, ensuring unmatched performance, power efficiency, and scalability to meet the demands of modern AI applications. Your role will involve working on cutting-edge semiconductor projects, requiring a blend of technical expertise, problem-solving skills, and collaborative teamwork. Your responsibilities will include defining micro-architecture and creating detailed design specifications, developing RTL code based on system-level requirements using Verilog, VHDL, or SystemVerilog, implementing complex digital functions and algorithms in RTL, and executing comprehensive test plans to verify RTL designs. You will optimize designs for power, performance, and area constraints, conduct simulation and debugging activities to ensure design accuracy, collaborate with verification engineers to develop test benches and validate RTL against specifications, and apply your strong understanding of digital design principles and concepts. To excel in this role, you should possess proficiency in writing and debugging RTL code, experience with synthesis, static timing analysis, and linting tools, familiarity with scripting languages like Python, Perl, or TCL for automation, and expertise in processor subsystem design, interconnect design, or high-speed IO interface design. A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, along with 5+ years of experience in RTL design and verification, is required. Proven experience in digital logic design using Verilog, VHDL, or SystemVerilog, familiarity with simulation tools such as VCS, QuestaSim, or similar, and hands-on experience with RTL design tools like Synopsys Design Compiler and Cadence Genus is preferred. At Kinara, we offer an innovative environment where technology experts and mentors collaborate to tackle exciting challenges. We believe in sharing responsibilities and valuing diverse viewpoints. If you are passionate about making a difference in the field of edge AI technology, we invite you to join our team and contribute to creating a smarter, safer, and more enjoyable world. Your application is eagerly awaited as we look forward to reviewing your qualifications and experiences. Make your mark with us at Kinara!,

Qualcomm India Private Limited is seeking a talented individual to join our Engineering Group, specifically focusing on Hardware Engineering. In this role, you will be responsible for developing micro-architecture and RTL design for Cores related to security, with a primary focus on block level design. Your responsibilities will also include enabling software teams to utilize hardware blocks effectively, as well as running ASIC development tools such as Lint and CDC. Additionally, you will be expected to report progress status and communicate effectively against set expectations. To be considered for this position, you must hold a Bachelor's degree in Engineering, Information Systems, Computer Science, or a related field, along with a minimum of 5 years of Hardware Engineering experience. Preferred qualifications include 5 to 10 years of work experience in ASIC/SoC Design, proficiency in RTL design using Verilog/System Verilog, and knowledge of cryptography concepts such as public/private key, hash functions, and encryption algorithms. Experience in Root of Trust and HW crypto accelerators, defining HW/FW interfaces, Linting, CDC, and LEC will be advantageous. Proficiency in database management flows using tools like Clearcase/Clearquest, as well as programming skills in Verilog, C/C++, Python, and Perl are highly desirable. Excellent oral and written communication skills, along with a proactive and collaborative approach to work, will also be key to success in this role. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please reach out to disability-accommodations@qualcomm.com. It is essential that all employees adhere to applicable policies and procedures, particularly those concerning the protection of confidential information. Please note that Qualcomm does not accept unsolicited resumes or applications from staffing and recruiting agencies. If you have any inquiries about this role, please contact Qualcomm Careers directly.,

Qualcomm India Private Limited is looking for a passionate STA and Synthesis Engineer to join their Engineering Group in Chennai. As an integral part of the cross-functional engineering teams, you will be engaged in all phases of design and development cycles, specifically focusing on Synthesis, Static Timing Analysis, and LEC of SoC/Cores. Your responsibilities will include full chip and block level timing closure, IO budgeting for blocks, logical equivalence checks between RTL to Netlist and Netlist to Netlist, as well as implementing low-power techniques such as clock gating, power gating, and MV designs. Additionally, you will be involved in ECO timing flow and should be proficient in scripting languages like TCL and Perl. The ideal candidate should possess a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 2+ years of experience in Hardware Engineering. Alternatively, a Master's degree with 1+ year of relevant experience or a PhD in the aforementioned fields is also acceptable. Applicants with 1-5 years of experience are encouraged to apply. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact Qualcomm at disability-accommodations@qualcomm.com or refer to their toll-free number for assistance. Qualcomm also emphasizes the importance of compliance with company policies and procedures, including security measures for protecting confidential information. Staffing and Recruiting Agencies are advised that Qualcomm's Careers Site is exclusively for individuals seeking job opportunities directly with Qualcomm. Agency submissions will be considered unsolicited, and Qualcomm does not accept unsolicited resumes or applications from agencies. For further details about this role, please reach out to Qualcomm Careers.,

As the owner of Ethernovia's India digital hardware team, you will be responsible for all aspects of digital design and digital verification. This position requires both hands-on technical contribution as well as managerial and technical leadership. You will hire and build your own team to plan and execute the design, verification, and validation of advanced automotive communication semiconductors and systems. Key Qualifications: - BS and/or MS in Electrical Engineering, Computer Science, or related field - Minimum 15+ years combined of ASIC design, verification, and leadership experience - Strong understanding of ASIC design and verification fundamentals and industry standard methodologies - Experience with Verilog/System Verilog, UVM, Python, TCL, C/C++ - Experience with the full verification flows, from spec to coverage analysis to gate level sims with SDF - Experience with all aspects of digital SoC design, from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and static timing analysis to deliver a design meeting target power, performance, and area goals - Successful track record of leading and growing a digital hardware team - Debugging failures in simulation to root cause problems - Self-motivated and able to work effectively both independently and collaboratively - Startup attitude and expected compensation required Additional Success Factors: - Experience in any of the following areas: Networking (PCIe, Ethernet, MAC, PHY, Switching, TCP/IP, security, and other industry standard protocols), Video standards, protocols, processing, Digital signal processing filters, Third party IP (SerDes, controllers, processors, etc.), Modular and Reusable Testbench architecture, Design for re-use of pre and post-silicon tests and infrastructure, Automation of testbench creation, tests, regression, or EDA tools, Knowledge of SystemC and/or DPI Personal Skills: - Excellent communication/documentation skills - Attention to details - Collaboration across multidisciplinary and international teams What you'll get in return: - Technology depth and breadth expansion that can't be found in a large company - Opportunity to grow your career as the company grows - Pre-IPO stock options - Cutting-edge technology - World-class team - Competitive base salary - Flexible hours - Flexible vacation time to promote a healthy work-life balance,

You should hold a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or possess equivalent practical experience. Additionally, you should have at least 5 years of experience in Application-Specific Integrated Circuit (ASIC) design for test, encompassing the silicon life cycle through DFT pattern bring-up on Automatic Test Equipment (ATE) and manufacturing. It is crucial to have familiarity with ATPG, Low Value (LV), Built-in self-test (BIST), or Joint Test Action Group (JTAG) tool and flow. Ideally, you should also have experience with a programming language like Perl, along with expertise in Synthesis, Lint, Change Data Capture (CDC), Local Enhanced Content (LEC), DFT timing, and Static Timing Analysis (STA). Proficiency in performance design DFT techniques, understanding of the end-to-end flows in Design, Verification, DFT, and Partner Domains (PD), and the ability to scale DFT would be advantageous. As part of our dynamic team, you will be involved in developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a pivotal role in the innovation of products that are cherished by millions globally. Your skills will influence the next wave of hardware experiences, delivering exceptional performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team synergizes the best of Google AI, Software, and Hardware to craft profoundly beneficial experiences. We are dedicated to researching, designing, and advancing new technologies and hardware to enhance computing speed, seamlessness, and power, ultimately striving to enhance people's lives through technology. Your responsibilities will include collaborating with a team dedicated to Design for Testing (DFT) verification, Pattern generation, Standard Delay Format (SDF) simulations, Static Timing Analysis (STA) checks. You will be tasked with crafting Pattern delivery using Automatic Test Pattern Generation (ATPG), engaging in Silicon bring-up, working on Yield, Vmin or Return Materials/Merchandise Authorization (RMA) debug, and delivering debug patterns while conducting Silicon data analysis.,

1.DV 2.PD 3.DFT 4.RTL 5.PD(VLCP)/(EMIR) 6.PV 7.STA/Synthesis

Qualcomm India Private Limited is seeking a Hardware Engineer to be a part of the Engineering Group, specifically in the Hardware Engineering team. As a Qualcomm Hardware Engineer, you will be involved in various aspects of planning, designing, optimizing, verifying, and testing electronic systems. This role will require you to work on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to contribute to the development of cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. To be considered for this position, you must have a minimum of a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field, along with at least 3 years of Hardware Engineering or related work experience. Alternatively, a Master's degree with 2+ years of experience or a PhD with 1+ year of experience in the same fields will also be considered. Proficiency in Synthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation, and the development of signoff quality constraints and power intent constraints is required. Experience with TCL script development, RTL development, or Physical Design will be advantageous. The ideal candidate should have at least 6 years of experience in Hardware Engineering. Qualcomm is an equal opportunity employer and is committed to providing reasonable accommodations for individuals with disabilities during the application/hiring process. If you require an accommodation, please contact disability-accommodations@qualcomm.com. Qualcomm expects its employees to adhere to all applicable policies and procedures, including those related to the protection of company confidential information. Please note that Qualcomm's Careers Site is intended for individuals seeking job opportunities directly with Qualcomm. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes through the Careers Site. Unsolicited submissions from agencies will not be accepted. For more information about this role, please reach out to Qualcomm Careers directly.,

Qualification: - BE Electrical with 3-5 years experience, Order Execution Manager for MV GIS Goa works, take care Contract Review at booking stage, preparation of details execution planning & engineering drawings. Aware on latest IEC / IEE standards applicable to MV switchgear. Secure the approval from concern authority and timely loading to factory. & monitoring to ensure maintain / improve booking margins, UOV monitoring, Revenue forecasting, supporting to BA team for payment collection, LD recovery, other open topic about contract if any,

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. Job Overview: Person will be responsible for developing next generation SoCs for mobile products and its adjacencies. The role will require the candidate to understand and work on all aspects of VLSI development from micro architecture and platform architecture, front end design, and design convergence. The person is also responsible for overseeing physical design and verification aspects. : - Full chip design for multi million gates SoC- Digital design and development (RTL)- Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification- Manage IP dependencies, planning and tracking of all front end design related tasks- Driving the project milestones across the design, verification and physical implementations Minimum Qualifications: - Minimum 15 years of solid experience SoC design- Developing architecture and micro-architecture from specs- Understanding of various bus protocols AHB, AXI and peripherals like USB, SDCC- Understanding of Memory controller designs and Microprocessors is an added advantage- Understanding of Chip IO design and packaging is an added advantage- Familiarity with various bus protocols like AHB, AXI is highly desired- Ability to review top level test plans- Expertise in Synopsys Design Compiler Synthesis and formal verification with Cadence LEC- Working knowledge of timing closure is a must - Should have good post silicon bring up and debug experience - Should have good SoC integration exposure and its challenges - Should have good exposure to design verification aspects - Having SoC specification to GDS to commercialization experience is highly desired - Needs to makes effective and timely decisions, even with incomplete information.- Should possess a strong understanding of a particular technical area and accumulated significant experience in this area and other related areas.- Provides direction, mentoring, and leadership to a small to medium sized groups.- Should possess strong communication and leadership skills to ensure effective communication with Program Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

As a candidate for the role, you should possess a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or have equivalent practical experience. Additionally, you need to have at least 5 years of experience in Application-Specific Integrated Circuit (ASIC) design for test, including managing the silicon life cycle through DFT pattern bring-up on Automatic Test Equipment (ATE) and manufacturing. It is crucial that you have familiarity with ATPG, Low Value (LV), Built-in Self Test (BIST), or Joint Test Action Group (JTAG) tool and flow. Preferred qualifications for this position include proficiency in a programming language such as Perl, along with experience in Synthesis, Lint, Change Data Capture (CDC), Local Enhanced Content (LEC), DFT timing, and Static Timing Analysis (STA). An understanding of performance design DFT techniques, end-to-end flows in Design, Verification, DFT, and Partner Domains (PD), as well as the ability to scale DFT will be advantageous. Joining our team means being part of a group that continually pushes boundaries, focusing on developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a pivotal role in the innovation that underpins products adored by millions globally. Your expertise will be instrumental in shaping the next wave of hardware experiences, delivering unmatched performance, efficiency, and integration. At Google, our mission is to organize the world's information and make it universally accessible and useful. Our collaborative team leverages the best of Google AI, Software, and Hardware to create exceptionally helpful experiences. We are dedicated to researching, designing, and developing new technologies and hardware to make computing faster, seamless, and more powerful, ultimately aiming to enhance people's lives through technology. In this role, your responsibilities will include collaborating with a team focusing on Design for testing (DFT) verification, Pattern generation, Standard Delay Format (SDF) simulations, and Static Timing Analysis (STA) checks. You will be tasked with writing a Pattern delivery using Automatic Test Pattern Generation (ATPG), contributing to Silicon bring-up, working on Yield, Vmin or Return Materials/Merchandise Authorization (RMA) debug, and delivering debug patterns, as well as performing Silicon data analysis.,

As a Hardware Engineer at Qualcomm, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams is essential to meet performance requirements and deliver innovative solutions. To qualify for this role, you must hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with a minimum of 4 years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years of experience, or a PhD with 2+ years of experience can also be considered. Additionally, candidates with a Bachelor's degree and 2+ years of experience, a Master's degree and 1+ year of experience, or a PhD with relevant experience are eligible. The ideal candidate should possess good hands-on experience in Floorplanning, PNR, and STA flows, as well as knowledge of Placement/Clock Tree Synthesis (CTS) and optimization. Familiarity with signoff domains such as LEC, CLP, and PDN is required, along with proficiency in Unix/Linux, Perl, TCL scripting. Key responsibilities include taking ownership of PNR implementation on the latest nodes, covering tasks like Floorplanning, Placement, CTS, and post-route activities. Signoff knowledge is crucial, encompassing areas like STA, Power analysis, FV, low power verification, and PV. A quick learner with strong analytical and problem-solving skills will excel in this role. Qualifications for this position include a minimum of 15 years of Hardware Engineering experience or related work experience, along with expertise in PNR flow for advanced tech nodes like 4nm, 5nm, 7nm, and beyond.,

About The Role Skill required: Network Services - Cisco Routing and Switching Operations Designation: Business Advisory Associate Qualifications: Any Graduation Years of Experience: 1 to 3 years About Accenture Combining unmatched experience and specialized skills across more than 40 industries, we offer Strategy and Consulting, Technology and Operations services, and Accenture Song all powered by the worlds largest network of Advanced Technology and Intelligent Operations centers. Our 699,000 people deliver on the promise of technology and human ingenuity every day, serving clients in more than 120 countries. Visit us at www.accenture.com What would you do "Helps transform back office and network operations, reduce time to market and grow revenue, by improving customer experience and capex efficiency, and reducing cost-to-serveLooking for a candidate who has expertise in Networking and has good knowledge on fundamentals of NetworkA solution that validates the ability to install, configure, operate, and troubleshoot medium-size route and switched networks." What are we looking for "Agility for quick learningAbility to work well in a teamProcess-orientationWritten and verbal communicationNetwork fundamentalsUnderstanding all the networking devices:Routers, switches, etc.IP connectivity, access, addressing, and servicesNetwork security fundamentalsInstallation, Configuration, Operation, Administration, and Troubleshooting Fundamental IPv4 & IPv6 Business NetworksExcellent CommunicationProblem Solving SkillsFlexibilityTeamworkExperience and working knowledge on OSI Layer 1 (Physical) and 2 (Datalink) troubleshooting (WAN point to point connection) Experience and working knowledge with IP, WAN, OSI layer, TCP/IP models, IPv4/v6 addressing, subnetting and Ethernet. Layer 1 to Layer 3 fault isolation and troubleshooting with telco providers and onsite technicians. Experience working with internal groups (e.g., order entry, test & turn-up, sales), and third party client/vendors and LEC s (preferred). Familiarity with SDH, SONET, and Ethernet concepts Basic knowledge of cabling infrastructure such as patch panels, cross-connects and fiber types. Experience working with internal groups (e.g., order entry, test & turn-up, sales), and third party client/vendors and LEC s (preferred). Experience working with global carriers in North America, LATAM, APAC, and/or EMEA Experience working in a multi-vendor DWDM optical environment Good English written/verbal communication and customer engagement skills Strong focus on providing an outstanding user experience Must be detail-oriented, with strong organizational skills Able to work independently and also in a team environment" Roles and Responsibilities: "In this role you are required to solve routine problems, largely through precedent and referral to general guidelines Your expected interactions are within your own team and direct supervisor You will be provided detailed to moderate level of instruction on daily work tasks and detailed instruction on new assignments The decisions that you make would impact your own work You will be an individual contributor as a part of a team, with a predetermined, focused scope of work Please note that this role may require you to work in rotational shiftsProvide 24/7/365 monitoring of ticket queue, phones, and IRC channelManage network events such as:Fiber cuts/ Leased Wave outage - Notify dark fiber providers of outage and manage event to resolution, verify quality of remedial work by measuring power levels etc., and provide all stakeholders with periodic updatesLink Down, Latency, Packet Loss, Network Traffic Issues and Routing and BGP issues - FamiliarityProvide 24/7/365 monitoring of ticket queue, phones, and IRC channelManage network events such as:Fiber cuts/ Leased Wave outage - Notify dark fiber providers of outage and manage event to resolution, verify quality of remedial work by measuring power levels etc., and provide all stakeholders with periodic updatesLink Down, Latency, Packet Loss, Network Traffic Issues and Routing and BGP issues - Familiarity and understanding of router show commands and how to interpret the outputManage client s optical network, manage alarms and faults in a multi-vendor environment, andTracking of all work in ticketing system network interconnects with internal and external network operatorsTrack and maintain a repository of RFOs and vendor improvements/actions and be able to represent client during external calls with 3rd party providersManage troubleshooting, confirming fix and restoring traffic from network incidents reported by internal teams and third-party teams, engaging field resources and inventory teams as necessary.Track, coordinate and manage hardware recalls / minor card or part replacement, RMA part delivery, initiate production change requests and work with onsite techs for faulty card/part replacementRead/Parse vendor notifications and translate to Clients Production Change Request (PCR s)Look up affected circuits to include them in change requestEscalate any emergency change requests for immediate review and schedulingNavigate ambiguity with unclear notifications from vendors - escalating as necessary or referring notification to other internal client teams" Qualification Any Graduation

You will be joining a leading training institute in the semiconductor industry that is constantly seeking dedicated individuals who are enthusiastic about achieving excellence and eager to expand their knowledge. Our work environment is dynamic, fostering innovation and creativity, and we provide avenues for personal and professional growth through training programs, mentorship, and coaching. The position available is for Synthesis/STA in either Bengaluru or Noida with a requirement of 3-12 years of experience and a BTECH/MTECH qualification. Key Responsibilities: - Demonstrated proficiency in timing concepts and the ability to independently close timing of Block/SoC. - Hands-on experience in generating constraints. - Proficiency in Logical synthesis tools such as Design compiler/ Rc compiler. - Familiarity with Formal Verification and comfortable using LEC/formality tools. - Ability to generate and implement functional Ecos. - Experience in Pre-layout and Post layout timing analysis using industry standard tools like Primetime/ETS. - Hands-on experience in crosstalk timing closure. - Understanding of Path based analysis, AOCV, DMSA is advantageous. - Knowledge of the complete physical Design flow is considered a plus. If you are a self-driven, innovative individual with a strong commitment to excellence, we encourage you to submit your resume and cover letter to our HR department. Be part of our dedicated team of professionals and contribute to the advancement of the semiconductor industry.,

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Looking for a highly talented and a technically strong leader with an eye for quality to lead a high performing and talented team of engineers in the implementation domain for Display Sub-System. Able to handle multiple project execution that are time critical and complex Able to communicate effectively with all stakeholders across the organization Able to collaborate with cross functional teams for upholding the best practices and enabling smooth execution Focus on improving execution efficiency and improve on the optimizations in area, power and performance. Able to grow the team in terms of technical depth and size as we do more and more projects Able to innovate and bring fresh ideas Bachelor’s or master’s degree in engineering with 9-13+ Years of experience. Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools. Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure. Experience in all aspects of timing closure for multi-clock domain designs. Should be familiar with MCMM synthesis and optimization. Should have good understanding of low-power design implementation using UPF. Experience with scripting language such as Perl/ Python, TCL. Experience with different power optimization flows or technique such as clock gating. Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation Should be able to handle ECOs and formal verification and maintain high quality matrix Responsibilities include Synthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation. Development of signoff quality constraints and the development of power intent constraints. May also include running RTL Lint, CLP, MEMBIST, DFT DRC etc. TCL script development in addition to running/analyzing/debugging designs. Hands on with Synopsys DCG/Genus/Fusion Compiler. Hands on with Synopsys Prime Time including constraint development for complex blocks with multiple clock domains. Hands on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development Experience with either RTL development or Physical Design is also a plus