73 Lec Jobs

As an experienced ASIC RTL Design Engineer at MarvyLogic, you will be responsible for designing cutting-edge solutions that impact various industries. Your role will involve working with multiple clock and power domains, integrating and validating MIPI cores, debugging, and implementing CSI/DSI controllers. Your expertise in Verilog/System Verilog will be crucial in creating micro-architecture specifications, reviewing vendor IP integration guidelines, and running integrity check tools to ensure compliance with coding standards. Additionally, you will play a key role in the design verification and physical implementation processes to meet performance goals. **Key Responsibilities:** - Utilize your 10+ years of ASIC RTL Design experience to develop innovative solutions - Demonstrate proficiency in Verilog/System Verilog and experience with multiple clock and power domains - Integrate and validate CSI/DSI/DPHY/CPHY/other MIPI cores, including controllers and SerDes - Debug CSI/DSI issues and design and implement CSI/DSI controllers - Create block-level micro-architecture specifications outlining interfaces, timing behavior, and design tradeoffs - Review vendor IP integration guidelines and ensure compliance throughout the design flow - Run integrity check tools such as Lint/CDC/DFT/LEC/UPF to meet coding and implementation guidelines - Participate in design verification and physical implementation processes to achieve area, power, and performance goals **Qualifications Required:** - 10+ years of ASIC RTL Design experience - Graduate Degree in Electrical/Electronics Engineering (Post Graduate degree is a plus) - Experience with CSI/DSI debug and FPGA netlist releases - Familiarity with ASIC product life cycle (requirements, design, implementation, test, and post-silicon validation) - Strong communication skills and ability to collaborate with multi-site teams At MarvyLogic, we foster a culture that values passion for technology solutions and individual growth. Working with us will provide you with exposure to diverse industries and emerging technologies, helping you evolve both professionally and personally towards a more fulfilling life.,

As a Hardware Engineer at Qualcomm India Private Limited, you will be responsible for the physical design aspects of ASICs, including Place and Route (PnR) flow and methodology. Your key responsibilities will include: - Executing complete PD ownership from netlist to GDS2, encompassing HM level PV, LEC, low-power checks, PDN, and STA closure - Implementing Voltage Islands and low power methodologies, flows, and implementation - Debugging Congestion and Clock Tree Synthesis (CTS) issues - Utilizing PnR tools such as Innovus/Fusion compiler and flow - Familiarity with Sign-off methodologies and tools (PV/PDN/STA/FV/CLP/Scan-DRC(tk)) - Enhancing existing methodologies and flows - Proficiency in scripting languages like TCL, PERL, and PYTHON - Working effectively in a global team environment - Communicating status and issues of owned tasks effectively Qualifications required for this role include: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 4+ years of Hardware Engineering experience, or - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 3+ years of Hardware Engineering experience, or - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 2+ years of Hardware Engineering experience - 4-10 years of experience in physical design, including floorplanning, PNR, CTS, and signoff checks If you are an individual with a disability and need accommodation during the application/hiring process, Qualcomm is committed to providing accessible support. You may contact disability-accommodations@qualcomm.com for assistance. Qualcomm expects all employees to adhere to applicable policies and procedures, including those related to confidentiality and security. Please note that Qualcomm's Careers Site is intended for individuals seeking jobs directly at Qualcomm, and staffing/recruiting agencies are not authorized to submit profiles, applications, or resumes through this platform. If you require more information about this role, please reach out to Qualcomm Careers directly.,

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Experience: Minimum 2 to 4 years of hands on experience in Synthesis and LEC Job Role Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools. Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure. Experience in all aspects of timing closure for multi-clock domain designs. Should be familiar with MCMM synthesis and optimization. Should have good understanding of low-power design implementation using UPF. Experience with scripting language such as Perl/ Python, TCL. Experience with different power optimization flows or technique such as clock gating. Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation Should be able to handle ECOs and formal verification and maintain high quality matrix Skill Set Proficiency in Python/Tcl Familiar with Synthesis tools (Fusion Compiler/Genus) , Fair knowledge in LEC, LP signoff tools Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus Should be sincere, dedicated and willing to take up new challenges

General Summary: Job Function : Camera Design Lead/Staff Candidate will be responsible for design/developing next generation SoCs sub systems for mobile phone camera . Candidate will be working on ASIC based on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI development cycle like architecture, micro architecture, Synthesis/PD interaction and design convergence. Skills/Experience 5-10 years with Masters (6 to 10 years with Bachelors) Solid experience in digital front end design for ASICsSolid Expertise in RTL microarchitecture and design coding in Verilog/SV for complex designs with multiple clock and power domainsExpertise with various bus protocols like AHB, AXI and NOC designs Experience in low power design methodology and clock domain crossing designsUnderstanding of full RTL to GDS flow to interact with DFT and PD teams Experience in Tools like Spyglass Lint/CDC checks and waiver creationExperience in formal verification with Cadence LEC Experience in mobile Multimedia/Camera design is a plus DSP /ISP knowledge is a plus. Working knowledge of timing closure is a plusExpertise in Perl, TCL language is a plusExpertise in post-Si debug is a plus Good documentation skillsAbility to create unit level test plan General Should possess good communication skills to ensure effective interaction with Engineering Management and mentor group members. Should be self-motivated and good team working attitude and need to function with little direct guidance or supervision Responsibilities Digital design and development (RTL) working in close collaboration with Multi-site leadsDeveloping the micro architecture and implementing the design using Verilog/SV. Integrate and deliver complex subsystem to SoCDesign and implement defined tasks independently. Work in close coordination with Systems, Verification, SoC team , SW team, PD & DFT teams to get the goals completed.Analyze reports/waivers or run various tools : Spyglass, 0-in, DC-Compiler, Prime time, synthesis, simulation etc Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Qualcomm India Private Limited is a leading technology innovator that is at the forefront of pushing the boundaries of what's possible to enable next-generation experiences and drive digital transformation towards creating a smarter, connected future for all. As a Qualcomm Hardware Engineer, your role will involve planning, designing, optimizing, verifying, and testing electronic systems. This includes working on a variety of systems such as yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams to develop solutions and meet performance requirements is a key aspect of your responsibilities. To be considered for this role, you should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 3+ years of Hardware Engineering or related work experience. Alternatively, a Master's degree with 2+ years of experience or a PhD with 1+ year of experience in the aforementioned fields will also be suitable. The ideal candidate must possess a minimum of 4 to 6 years of hands-on experience in Synthesis and LEC. Strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry-standard tools are essential. Experience in writing timing constraints for synthesis, STA, timing closure, and pipelining for performance optimization, as well as familiarity with MCMM synthesis and optimization, are required. Additionally, a good understanding of low-power design implementation using UPF is expected. Proficiency in scripting languages such as Perl/Python, TCL, and experience with different power optimization flows like clock gating are advantageous. The ability to work independently with design, DFT, and PD teams for netlist delivery and timing constraints validation, as well as handling ECOs and formal verification, are crucial aspects of the job role. The desired skill set includes proficiency in Python/Tcl, familiarity with Synthesis tools (Fusion Compiler/Genus), fair knowledge in LEC, LP signoff tools, and proficiency in VLSI front-end design steps such as Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking. Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is considered a plus. Being sincere, dedicated, and willing to take up new challenges are also qualities that Qualcomm values in its employees. Qualcomm is an equal opportunity employer committed to providing an accessible and inclusive hiring process for individuals with disabilities. If you require accommodations during the application/hiring process, please reach out to Qualcomm at disability-accomodations@qualcomm.com or through their toll-free number. Qualcomm also expects its employees to adhere to all applicable policies and procedures, including those related to the protection of Company confidential information and other proprietary data. Note that Qualcomm does not accept unsolicited resumes or applications from agencies. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes through Qualcomm's Careers Site. For further information about this role, please contact Qualcomm Careers directly.,

High Performance DSP core Implementation(Synthesis) Senior Lead Engineer General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Experience: Minimum 4 to 6 years of hands on experience in Synthesis and LEC Job Role Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools. Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure. Experience in all aspects of timing closure for multi-clock domain designs. Should be familiar with MCMM synthesis and optimization. Should have good understanding of low-power design implementation using UPF. Experience with scripting language such as Perl/ Python, TCL. Experience with different power optimization flows or technique such as clock gating. Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation Should be able to handle ECOs and formal verification and maintain high quality matrix Skill Set Proficiency in Python/Tcl Familiar with Synthesis tools (Fusion Compiler/Genus) , Fair knowledge in LEC, LP signoff tools Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus Should be sincere, dedicated and willing to take up new challenges

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Experience: Minimum 2 years of hands-on experience in Synthesis and LEC Job Role Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools. Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure. Experience in all aspects of timing closure for multi-clock domain designs. Should be familiar with MCMM synthesis and optimization. Should have good understanding of low-power design implementation using UPF. Experience with scripting language such as Perl/ Python, TCL. Experience with different power optimization flows or technique such as clock gating. Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation Should be able to handle ECOs and formal verification and maintain high quality matrix Skill Set Proficiency in Python/Tcl Familiar with Synthesis tools (Fusion Compiler/Genus) , Fair knowledge in LEC, LP signoff tools Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus Should be sincere, dedicated and willing to take up new challenges

You should have a minimum of 4 years of experience in the field. You must be proficient in using Synthesis and netlist validation tools, particularly LEC and Spyglass checks, as well as scan insertion and DRC debug. It is essential to be well-versed in both Synopsys and Mentor Graphics DFT flows. Your expertise should also include experience in Scan Compression for Hierarchical and Modular EDT, ATPG, and Coverage debug, along with the ability to manage multiple clock domains and familiarity with the OCC flow. You should have practical experience in BIST and BISR insertion and Validation with SMS and MBIST Architect. Hands-on experience with JTAG, IJTAG, and SSN is required. You should be familiar with P1500 and have experience in managing wrapper cells and test integration. Knowledge of INTEST and EXTEST modes, as well as working knowledge on Cell Aware ATPG, is important for this role. Additionally, strong communication and Automation skills are a must for this position.,

We are looking for a highly skilled Synthesis & Static Timing Analysis (STA) expert to join our Flows & Methodologies Team in Noida with a hybrid work model where you will be required to work 3 days in the office. As an ideal candidate for this role, you should have a minimum of 6 to 15 years of experience along with strong analytical skills, attention to detail, and the ability to collaborate effectively with cross-functional teams. Proficiency in EDA tools and digital design principles is a must-have for this position. Your key responsibilities will include working closely with SoC cross-functional teams to define and develop Synthesis & STA methodologies for advanced nodes such as 3nm, 5nm, and 16nm. You should possess a strong knowledge of RTL, Synthesis, LEC, VCLP, Timing Constraints, UPF, Timing Closure & Signoff. Experience with EDA tools like Genus, Fusion Compiler, PrimeTime, Tempus, and Conformal will be beneficial for this role. Additionally, strong scripting skills in Perl, TCL, and Python for automation and flow development are required. If you meet the above requirements and are excited about this opportunity, click on the Apply option or share your resume with Heena at heena.k@randstad.in.,

As an RTL Design Engineer at Alphawave Semi, you will play a crucial role in the advancement of digital technology by contributing to the next generation Chiplet designs. You will be involved in the complete ASIC development cycle, from concept to product, and work on cutting-edge technologies that power innovation in data-demanding industries. Your responsibilities will include microarchitecting and RTL Design of SoC SubSystem/IP blocks, developing UPF and running CLP checks, ensuring RTL quality checks, creating documentation for hardware blocks, and collaborating with various teams to ensure the successful tapeout of high-quality SoCs. To excel in this role, you should possess a Bachelor's or Master's degree in Electrical, Electronics and Communication, or Computer Science Engineering, along with 8+ years of experience in SoC architecture and full-chip design for multi-million gate SoCs. Your expertise should encompass the design convergence cycle, IP dependencies management, project milestone tracking, and experience in CPU, high-speed serial interfaces, or coherence/noncoherent NOC domains. Your skills in communication, collaboration, and leadership will be essential in working effectively in a fast-paced, distributed team environment. You should have a strong understanding of bus protocols, memory controllers, chip IO design, test plans, verification, synthesis, formal verification, timing closure, post-silicon debug, and decision-making under incomplete information. At Alphawave Semi, we offer a hybrid work environment and a comprehensive benefits package that includes competitive compensation, Restricted Stock Units (RSUs), provisions for advanced education, medical insurance, wellness benefits, educational assistance, advance loan assistance, and office lunch & snack facilities. We are committed to equal employment opportunity and welcome applicants from diverse backgrounds, providing accommodations during the recruitment process to ensure a fair and inclusive environment for all candidates.,

Qualcomm India Private Limited is seeking an experienced individual for the role of Micro-Architect and RTL Design Engineer to take ownership of the System Memory Management Unit (SMMU) IP for the next generation System-on-Chip (SoC) for smartphones, tablets, and other product categories. The SMMU performs virtual to physical address translation, dynamic allocation, and access control of DDR memory, designed in accordance with the ARM SMMU architecture spec. In this role, you will collaborate with Hardware and Software teams to comprehend design requirements, specifications, and interface details for the SMMU IP. You will be responsible for developing a micro-arch design specification that is optimized for performance, area, power, and software use cases. Additionally, you will implement the design spec in RTL coding language, ensuring code quality through various checks such as Lint, CDC, Synthesis, DFT, and low power checks. You will also work with the SoC level performance modeling team on latency, bandwidth analysis, and fine-tuning hardware configuration. The ideal candidate should possess expertise in VLSI logic design, ARM system architecture, memory management, virtual memory concepts, and core sight architecture. Knowledge of on-chip interconnect protocols like APB/AHB/AXI/ACE/ACE-Lite is essential, along with strong debugging, analytical, and problem-solving skills. A good understanding of the ASIC design convergence cycle and effective communication and collaboration abilities are also required. Desired skills include experience in designs optimized for low power, proficiency in scripting languages (Python or Perl) for automation initiatives, and working knowledge of Synthesis, DFT, LEC, functional cover points/assertions, and formal verification. The minimum qualifications for this role include a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field, with 4+ years of Hardware Engineering or related work experience. Alternatively, a Master's degree with 3+ years of experience or a PhD with 2+ years of experience is also acceptable. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com. Additionally, Qualcomm expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. Please note that Qualcomm's Careers Site is intended for individuals seeking job opportunities directly with Qualcomm. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes through the site. Unsolicited submissions from agencies will not be considered. For more information about this role, please reach out to Qualcomm Careers.,

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems. You will work on a variety of systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams will be essential to develop solutions and meet performance requirements. To be considered for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with at least 3+ years of Hardware Engineering or related work experience. Alternatively, a Master's degree with 2+ years of experience or a PhD with 1+ year of experience is also acceptable. A minimum of 2 to 6 years of hands-on experience in Synthesis and LEC is required for this position. Key responsibilities include having a strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools. You should be experienced in writing timing constraints for synthesis, STA, timing closure, and pipelining for performance optimization. Additionally, familiarity with MCMM synthesis and optimization, low-power design implementation using UPF, scripting languages like Perl/Python, TCL, power optimization flows like clock gating, and working independently with design, DFT, and PD teams for netlist delivery are important aspects of the role. The desired skill set for this position includes proficiency in Python/Tcl, familiarity with Synthesis tools such as Fusion Compiler/Genus, knowledge in LEC, LP signoff tools, and VLSI front end design steps like Verilog/VHDL, Synthesis, QoR optimization, and Equivalence Checking. Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression, and the ability to handle ECOs and formal verification are also required. Being sincere, dedicated, and willing to take up new challenges are qualities Qualcomm is looking for in potential candidates. Qualcomm is an equal opportunity employer committed to providing reasonable accommodations for individuals with disabilities during the application/hiring process. If you require an accommodation, you can reach out to Qualcomm's disability accommodations team. Qualcomm also expects its employees to adhere to all applicable policies and procedures, including security and confidentiality requirements. Please note that Qualcomm's Careers Site is intended for individuals seeking a job at Qualcomm directly. Staffing and recruiting agencies or individuals represented by an agency are not permitted to use this site for submissions. Unsolicited resumes or applications from agencies will not be accepted, and Qualcomm is not responsible for any fees related to such submissions. For further information about this role, you can contact Qualcomm Careers.,

You should have a minimum of 12 years of experience in ASIC design, with proficiency in Verilog coding, RTL design, and creating complex control path and data path designs. It is essential to have knowledge of interface Protocols such as UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display, Ethernet, and SATA. Familiarity with RTL checks including LINT, SDC, CDC, synthesis flow, LEC, and timing constraints is required. Experience in writing Verilog testbench and conducting simulations will be beneficial. At Cadence, we are seeking individuals who are passionate about technology and innovation. Join us in making a significant impact on the world of technology. Let's work together to solve challenges that others find insurmountable.,

The Manager, DFT will be responsible for implementing the hardware Memory BIST (MBIST) features that support ATE, in-system test, debug, and diagnostics needs of the memories in design. You will work closely with the design, design-verification, and backend teams to enable the integration and validation of the test logic in all phases of the design and backend implementation flow. The job requires you to have good scripting skills and the ability to design and debug with minimal oversight. You will also be involved in high-quality pattern release to the test team and support silicon bring-up and yield improvement. The ideal candidate for this role should be an ASIC Design DFT engineer with 10+ years of related work experience encompassing a broad mix of technologies. You should have knowledge of the latest state-of-the-art trends in Memory testing and silicon engineering. Hands-on experience in JTAG & IJTAG protocols, MBIST, and scan architectures is essential. Your verification skills should include System Verilog, LEC, and validating test timing of the design. Experience working with gate-level simulations, and debug with VCS and other simulators is required. Understanding the testbench in System Verilog, UVM/VMM is considered an addon. Post-silicon validation and debug experience, along with the ability to work with ATE patterns, is a crucial aspect of this role. Additionally, you should possess strong verbal communication skills and the ability to thrive in a dynamic environment. Proficiency in scripting skills such as Python/Perl is also required for this position.,

Job Description for DV You will be part of the team verifying IPs and SoCs leading to first Si success. Manage and lead a team of Verification engineers IP verification is coverage driven using latest industry standard methodologies and HVLs. Work involves defining verification strategy, writing test plans, developing efficient test benches and test cases. Code coverage, Functional coverage and assertions are desired. ARM based SoC verification experience is an added advantage. Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell Scripts etc. is a great plus. Multiple positions with emphasis on AMS and Power aware verification. Should have worked on GLS. Key Responsibilities: Lead Verification Efforts: Manage and mentor a team of IP and SoC verification engineers. Drive verification strategy to ensure first silicon success. Verification Planning & Execution: Define test plans and verification methodologies using UVM/OVM. Develop and maintain reusable testbenches and test cases. Coverage & Quality Assurance: Ensure high-quality verification through code coverage, functional coverage, and assertions. Perform Gate-Level Simulations (GLS) and Low Power Verification. Collaboration & Communication: Work closely with design, architecture, and validation teams. Provide regular updates and technical guidance to stakeholders. Tool & Script Development: Automate verification tasks using scripting languages like Python, Perl, Shell, and Tcl. Utilize industry-standard tools for emulation, LEC, and AMS verification. Primary Skills: Verilog, SV, UVM/OVM, IP Verification, SoC Verification, scripting Perl, Python, Shell, and Tcl. Secondary Skills: Test bench / model / VIP development, Functional coverage, GLS, LEC, Emulation, AMS, ARM, Protocols AHB/AXI/APB, Ethernet, USB, PCIe, I2C, SPI, CAN, Mipi CSI/DSI, LPDDR. Show more Show less

Qualcomm India Private Limited is seeking a skilled Hardware Engineer to join their Engineering Group. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, as well as digital/analog/RF/optical systems. Your role will involve working on cutting-edge technologies to launch world-class products and collaborating with cross-functional teams to develop solutions that meet performance requirements. To be considered for this role, you should possess a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field with at least 2 years of Hardware Engineering experience. Alternatively, a Master's degree with 1+ year of relevant experience or a PhD in a related field will also be considered. You should have proficiency in Python/Tcl, familiarity with Synthesis tools, and knowledge of VLSI front end design steps. As a Hardware Engineer at Qualcomm, you will work on Logic & Physical aware Synthesis, QoR optimization, constraints development, and implementation flow development. You should be able to lead a team, handle multiple projects, drive new tool evaluation, and refine methodologies for PPA optimization. Additionally, you are expected to be sincere, dedicated, and willing to take on new challenges. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, you can contact Qualcomm at disability-accommodations@qualcomm.com. The company expects its employees to adhere to all applicable policies and procedures, including security requirements for protecting confidential information. This is a great opportunity for individuals with a passion for hardware engineering and a desire to work on innovative technologies in a collaborative environment. If you meet the qualifications and are ready to take on new challenges, we encourage you to apply and join the Qualcomm team.,

We are seeking highly motivated, energetic, and team-oriented individual contributors who can work on synthesis, LEC, and constraints for NXPs digital IPs, working in close collaboration with the RTL team. Key Responsibilities Work closely with the architects and RTL team on synthesis, LEC, and constraints of NXP digital IPs Carry out floor planning, and physically aware synthesis on high-performance IPs Perform timing and power analysis on the design database (db), improve the recipe, and provide timing feedback to the RTL team Leads or solo owners are expected to work with minimal micro-management needs. They should be able to communicate with other project members to manage task divisions and deliveries Responsible for delivering the weekly status with desired metrics information Key Technical Skills Self-starter with 312 years of relevant experience in synthesis, LEC, and constraints at the IP level. Candidate should be able to set up the synthesis and LEC flows from scratch Strong fundamentals of synthesis and place & route (P&R) Good scripting knowledge (TCL, Perl, Python) Knowledge of Fusion Compiler, Genus/Innovus, and Primetime Mandatory Key Skills TCL,Perl,Python,micro-management,Design Engineering,RTL.

Synthesis, Static Timing Analysis and LEC of SoC/Cores Full chip and block level timing closure, IO budgeting for blocks Logical equivalence check between RTL to Netlist and Netlist to Netlist Knowledge of low-power techniques including clock gating, power gating and MV designs ECO timing flow Proficient in scripting languages (TCL and Perl). Minimum Qualifications: Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Role: US/UK Accounting - Knowledge Lead Location: Pune/Bangalore (Reporting Office once in a 3 months on Company Expenses) Shift: For US: 3 - 6 Years experience after CA & CA-inter Should be experienced from Insurance industry Shift: 3:00 PM - 12:00 AM month-end 4-5 Days 6:00 - 3:00 AM For UK: 4 - 7 Years experience after CA Shift: 1:00 PM - 10:00 PM Skills Required: International Accounting Final Accounting US / UK GAAP/IFRS *************************************************************************** IMMEDIATE JOINERS REQUIRED Send your updated CV directly to: 9152808909 *************************************************************************** Remote work Only Quarterly 10 Days Work from office (Travel and Stay by Company) Desired Candidate Profile: Chartered Accountant for LEC/Statutory reporting, Controllership functions Shift Timings: 1:00 pm - 10:00 pm OR 3:00 pm - 12:00 am. This needs to be flexible during month end/peak BDs and might change to mirror UK/US. Good working knowledge of accounting standards (US / UK GAAP/IFRS), account reconciliations, and month end close experience Excellent Communication Key Responsibilities: Review, process, gather, and compile accounting transactions and documents throughout the month for completeness, accuracy, and compliance with general accounting principles and established internal control policies and procedures. Ensure financial integrity and timely monthly, quarterly and year end close processes. Partner with stakeholders across Divisional Financial Operations to improve financial and accounting accuracy Record and review journal entries related to Divisional branch results Review and investigate reconciliation variances, assisting management to develop appropriate action plans addressing issues identified Provide support for internal and external audits including control walkthroughs, documentation support and inquiry response Manage multiple projects simultaneously and coordinate cross-functionally to meet strict project execution deadlines

The ASIC/SOC Front End Design Engineer role involves setting up ASIC QA flows for RTL design quality checks, understanding top-level interfaces, clock structure, reset structure, RAMs, CDC boundaries, and power domains. You will be responsible for executing various design steps such as Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, and CLP. Additionally, you will create clock constraints, false paths, multi-cycle paths, IO delays, exceptions, and waivers while reviewing flow errors, design errors, and violations. As an ASIC/SOC Front End Design Engineer, you will debug CDC and RDC issues, provide RTL fixes, and support the DFX team for DFX controller integration, Scan insertion, MBIST insertion, and DFT DRC & MBIST checks. The role also involves managing multiple PNR blocks, building wrappers, porting flows or designs to different technology libraries, generating RAMs based on targeted memory compilers, and integrating them with the RTL. Functional verification simulations will be run as necessary. The ideal candidate for this position should hold a B.E/M.E/M.Tech or B.S/M.S in EE/CE with 3 to 5 years of relevant experience in ASIC design flow, particularly in sub-20nm technology nodes. Proficiency in modern SOC tools like Spyglass, Synopsys design compiler & primetime, Questa CDC, Cadence Conformal, and VCS simulation is required. Experience in signoff of front end quality checks & metrics for various project milestones is essential. Additionally, familiarity with TCL, Perl, and Python scripting is preferred. This position is based in Hyderabad with an immediate start date. The desired candidate should have 3 to 5 years of experience in the field.,

As a Silicon Design Engineer 2 at AMD, your role is crucial in executing the front end implementation of sub-blocks or IP. You will be responsible for tasks such as synthesis, LEC, CLP, prelayout STA, and postlayout STA/Timing closure. Collaborating with the design team and PNR teams is essential to achieve closure and execute tasks as per schedule. Your key responsibilities include ensuring quality delivery for synthesis and timing closure, as well as debugging and resolving technical issues efficiently. The ideal candidate for this role should have experience in synthesis and timing closure, with additional experience in LEC and CLP being a plus. Handling blocks with complex designs, high-frequency clocks, and complex clocking should be within your expertise. A complete understanding of timing constraints, low power aspects, and concepts of DFT is necessary, along with the ability to debug and resolve issues effectively. Proficiency in scripting and automation will be beneficial in this role. To qualify for this position, you should hold a Bachelor's degree with 2 years of experience or a Master's degree with 1 year of experience in Electrical Engineering. Your academic credentials will play a significant role in showcasing your eligibility for this role at AMD. Join us at AMD, where together we advance technology and strive for innovation to solve the world's most important challenges. Your contributions as a Silicon Design Engineer 2 will be instrumental in building great products that shape next-generation computing experiences across various domains such as the data center, artificial intelligence, PCs, gaming, and embedded systems. Let's push the limits of innovation and make a difference in our industry, communities, and the world.,

You are invited to apply for a job opportunity in Bengaluru and Hyderabad if you meet the qualifications for any of the following positions: ASIC RTL Design Engineers Design Verification Engineers Analog Design Engineers Linux Device Driver Engineers Blue-Tooth Engineers Specific experience requirements include: - RISC-V processor experience, 4+ years, in Bangalore - Design Verification with PCIE, 5+ years, in Bangalore - DFT with Synopsys Tool experience (Tetrax max / Verdi), 4+ years, in Bangalore and Hyderabad - RTL Design Development, synthesis, CDC, LEC, and static timing analysis The positions available are suitable for individuals with 4 to 15 years of experience. Multiple positions are currently open in both locations.,

Qualcomm India Private Limited is seeking a skilled Hardware Engineer to join the Engineering Group, specifically the Hardware Engineering team. In this role, you will be responsible for developing micro-architecture and RTL design for security-related Cores, focusing on block level design. Your tasks will include enabling software teams to utilize hardware blocks efficiently and running ASIC development tools such as Lint and CDC. It will be crucial for you to report progress and communicate effectively against set expectations. As a qualified candidate, you should hold a Bachelor's degree in Engineering, Information Systems, Computer Science, or a related field, with a minimum of 5 years of Hardware Engineering experience. Additionally, having 5 to 10 years of work experience in ASIC/SoC Design is preferred. Proficiency in RTL design using Verilog/System Verilog and knowledge of cryptography concepts like public/private key, hash functions, encryption/signatures algorithms (such as AES, SHA, GMAC, etc.) will be beneficial for this role. Experience in Root of Trust, HW crypto accelerators, defining HW/FW interfaces, Linting, CDC, LEC, and database management flows with tools like Clearcase/Clearquest will be advantageous. Strong programming skills in Verilog, C/C++, Python, and Perl are essential. Excellent oral and written communication skills, proactive attitude, creativity, curiosity, motivation to learn and contribute, and good collaboration skills are also desired qualities. Qualcomm is an equal opportunity employer committed to providing accessible accommodations for individuals with disabilities throughout the application/hiring process. If you require assistance, please contact disability-accommodations@qualcomm.com. The company expects its employees to comply with all relevant policies and procedures, including those regarding the protection of confidential information. If you are a staffing or recruiting agency, please note that Qualcomm's Careers Site is exclusively for individuals seeking employment directly with Qualcomm. Unsolicited submissions from agencies will not be accepted. For more information about this Hardware Engineering position, please reach out to Qualcomm Careers directly.,

You should have 3+ years of experience in RTL, UPF & Physical aware Synthesis for cutting-edge technology nodes, logic equivalence checking, Scripting, and Netlist Timing Signoff. Proficiency in Python/Tcl is required. You should be familiar with Synthesis tools such as Fusion Compiler/Genus and have fair knowledge in LEC, LP signoff tools. Proficiency in VLSI front-end design steps including Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking is essential. Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus. You should be sincere, dedicated, and willing to take up new challenges. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Qualcomm is an equal opportunity employer that provides reasonable accommodations for individuals with disabilities during the application/hiring process. If you require accommodations, you may contact Qualcomm at disability-accommodations@qualcomm.com. Qualcomm expects its employees to adhere to all applicable policies and procedures, including security and confidentiality requirements regarding Company confidential information and other proprietary data. Please note that Qualcomm's Careers Site is for individuals seeking jobs at Qualcomm. Staffing and recruiting agencies are not authorized to use this site for submissions. Qualcomm does not accept unsolicited resumes or applications from agencies. For more information about this role, kindly contact Qualcomm Careers. 3074295,

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the worlds leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of whats next in electronics and the world. Job Description Location: NOIDA Exp-7-15Y We are seeking a highly skilled & experienced Synthesis & Static Timing Analysis (STA) expert to join our Flows & Methodologies Team. This role requires strong analytical skills, attention to detail, and the ability to work collaboratively with cross-functional teams. Proficiency in relevant EDA tools and a solid understanding of digital design principles are essential for success in these positions Scope Of Responsibilities As part of the Design Enablement team of the organization, you need to work closely with SoC cross functional teams to develop and define Synthesis & STA flow & methodology to meet SoC & IP level objectives on low geometry nodes (3/5/16nm) Your scope of work will cover tools and flows definition, requirement management for SoC designs You will work with EDA Vendors to proactively review latest tools and flows offerings in Synthesis & STA domains. Evaluate latest offerings and benchmark with organization used tools, flows, and methodologies. You will be an actor of change for deploying new tools & methodologies across the organization Qualifications Bachelor or Master or Ph.D. in Electronics Engineering and specialization in VLSI domain Good understanding of RTL, Synthesis, LEC, VCLP, Timing Constraints, UPF, Timing Closure & Signoff Experience with EDA tools like Genus, Fusion Compiler, Primetime, Tempus, Conformal Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Can do attitude,?openness to new environment, people and culture Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus Ability to work independently and as part of a team Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier . As the industrys leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, To Make Our Lives Easier . At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make peoples lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark Join Renesas. Lets Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Show more Show less