85 Design Compiler Jobs

Requirement Details: Role: Synthesis Engineer Experience: 4+ years Location: Bangalore (Preferred) Skill Set: Hands-on experience in logic synthesis using Design Compiler Strong understanding of timing , low-power requirements , and constraints validation

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

Front End Synthesis and Implementation Engineer - Job Description Front End Synthesis and Implementation Engineer Join the India team of a cutting-edge, well-funded storage startup in Silicon Valley as the Front End Engineer responsible for implementing complex SoCs using ARM architecture. As a Front End Engineer, you will work on SoC RTL and its implementation and quality checks such as synthesis, lint, CDC, and other aspects of the SoC implementation process. You will be involved in checks and flow management for both high-performance, multi-million gate complex IPs and SoCs. You will also be responsible for Power, Performance, and Area (PPA) analysis and optimization, as well as ensuring ...

General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ...

Job Details: Job Description: As an IP Structural/Physical Design Engineer, you will be working alongside Elite IP and SoC design teams to deliver next-generation Xeon products and related IPs for Server markets. We are looking for candidates with experience as physical design engineers as part of the Structural Design Expert Team in the IP organization. You will be fluent in all aspects of IP physical design flow from high-level block design to synthesis, place and route and timing and power convergence to build a design database that is ready for manufacturing. Your responsibilities will include all aspects of RTL2GDSII physical design flow convergence including but not be limited to: Over...

General Summary: Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primet...

General Summary: Responsibilities will include To be strong designer who is able to work independent on one of the peripheral IPs come up with design and microarchitecture solutions guide/mentor juniors engage with external teams to drive/resolve cross team dependencies. Take complete responsibility of one or more project and drive that independently. Being able to make schedule estimates is a plus. People management experience is a plus Skills & Requirements needed 12+ years of work experience in ASIC IP cores design Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering Knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and ...

As an ASIC/SoC Design Engineer at Qualcomm India Private Limited, you will be responsible for Logic design, micro-architecture, RTL coding, and integration for complex SoCs. Your expertise in Verilog/System-Verilog and knowledge of AMBA protocols such as AXI, AHB, and APB will be crucial. You will collaborate with verification and validation teams, work on low power SoC design, multi-clock designs, and asynchronous interfaces. Your experience with tools like Lint, CDC, Design compiler, and Primetime will be essential for successful ASIC development. Additionally, your understanding of constraint development, timing closure, and synthesis concepts will be beneficial. **Key Responsibilities:**...

As a Senior SoC Design Engineer at Qualcomm India Private Limited, you will be utilizing your 10-16 years of experience in SoC design. Your responsibilities will include working with AMBA protocols such as AXI, AHB, and APB, understanding SoC clocking/reset/debug architecture, and dealing with peripherals like USB, PCIE, and SDCC. It is crucial to have expertise in memory controller designs, microprocessors, constraint development, and timing closure. Collaboration with SoC verification and validation teams for pre/post Silicon debug will be an integral part of your role. Additionally, hands-on experience in Low power SoC design, Multi Clock designs, Asynchronous interface, and proficiency i...

As an experienced Logic Design Engineer at Qualcomm India Private Limited, your role will involve the following key responsibilities: - Hands-on experience in Logic design, micro-architecture, and RTL coding, with a strong emphasis on SoC design and integration for complex SoCs. - Proficiency in Verilog and System-Verilog, along with a solid understanding of AMBA protocols like AXI, AHB, and APB, as well as SoC clocking, reset, debug architecture, and peripherals such as USB, PCIE, and SDCC. - Knowledge of Memory controller designs, microprocessors, and experience in constraint development and timing closure. - Collaboration with the SoC verification and validation teams for pre/post Silicon...

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIOR SILICON DESIGN ENGINEER (AECG ASIC PD ENGINEER) The Role The position will involve w...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Description Responsibilities will include To be strong designer who is able to work independent on one of the peripheral IPs come up with design and microarchitecture solutions guide/mentor juniors engage with external teams to drive/resolve cross team dependencies. Take complete responsibility of one or more project and drive that independently. Being able to make schedule estimates is a plus. People management experience is a plus Skills & Requirements needed 12+ years of work experience in ASIC IP cores design Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering K...

Role Overview: As a Hardware Engineer at Qualcomm, you will be responsible for the Logic design, micro-architecture, and RTL coding of complex SoCs. Your expertise will be crucial in ensuring the successful design and integration of SoCs, as well as collaborating with verification and validation teams for pre/post Silicon debug. Key Responsibilities: - Hands-on experience with SoC design and integration - Proficiency in Verilog/System-Verilog - Knowledge of AMBA protocols such as AXI, AHB, and APB - Understanding of SoC clocking, reset, debug architecture, and peripherals like USB, PCIE, and SDCC - Familiarity with Memory controller designs and microprocessors - Experience in constraint deve...

Description The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history. Roles & Responsibilities: - Collaborate with architecture, timing, and logic design teams making a crucial impact on delivering cutting edge & Low power SOCs. - Perform I/O, bump & RDL (redistri...

General Summary: Responsibilities will include To be strong designer who is able to work independent on one of the peripheral IPs come up with design and microarchitecture solutions guide/mentor juniors engage with external teams to drive/resolve cross team dependencies. Take complete responsibility of one or more project and drive that independently. Being able to make schedule estimates is a plus. People management experience is a plus Skills & Requirements needed 4-8 years of work experience in ASIC IP cores design Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering Knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and ...

Collaborate with architecture, timing, and logic design teams making a crucial impact on delivering cutting edge & Low power SOCs. Perform I/O, bump & RDL (redistribution layer) planning, hard IP integration, partitioning, pin and feedthrough planning, repeater insertion, power grid generation. Perform special interface, and interconnect planning, bus routing, sequential pipeline planning and top-level design for testability (DFT). Be responsible for driving efficiency and quality improvements to the overall FC methodology including floorplan optimization for better utilization/QoR/runtime and timing and physical aware feedthrough/pin placement. Be responsible for coordinating collateral han...

General Summary: Responsibilities will include To be strong designer who is able to work independent on one of the peripheral IPs come up with design and microarchitecture solutions guide/mentor juniors engage with external teams to drive/resolve cross team dependencies. Take complete responsibility of one or more project and drive that independently. Being able to make schedule estimates is a plus. People management experience is a plus Skills & Requirements needed 8 to 10 years of work experience in ASIC IP cores design Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering Knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture ...

As a member of Qualcomm India Private Limited's Wireless IP team, you will be responsible for designing and developing cutting-edge RTL for next-generation cellular and Wi-Fi modem IPs used in mobile, wearable, and IoT platforms. Your role will involve working on high-performance, low-power digital designs throughout the full VLSI development cycle, from architecture and micro-architecture to RTL implementation and SoC integration. By collaborating with global teams, you will have the opportunity to contribute to market-leading wireless solutions. Key Responsibilities: - Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog. - Develop micro-architectu...

You have a rewarding opportunity at Qualcomm India Private Limited in the Engineering Group, specifically in the Hardware Engineering team. As a Senior SoC Design Engineer, you will play a crucial role with your extensive experience in SoC design and expertise in various protocols and architectures. Let's delve deeper into the responsibilities and qualifications required for this role: **Role Overview:** - Utilize your 15+ years of experience in SoC design to contribute effectively to the team - Demonstrate proficiency in AMBA protocols such as AXI, AHB, and APB, as well as SoC clocking/reset/debug architecture - Showcase your knowledge of peripherals like USB, PCIE, and SDCC - Gain an under...

Alternate Job Titles: Senior ASIC Physical Design Engineer Physical Implementation Engineer Senior Level IC Physical Design Specialist Senior SoC Physical Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and driven engineer with a solid foundation in integrated circuit (IC) design and physica...

Role & responsibilities: The candidate will be responsible for implementing the place and route of design blocks including floorplanning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc . The candidate will also be responsible for block level physical design closure in terms of timing, power, DRC/LVS etc. Preferred candidate profile : • 4-7 years of experience in ASIC Physical Design. • Have good knowledge of entire physical design process from floorplan till GDSgeneration. • Good Exposure to Physical Verification Process. • Have hands-on experience in latest sub-micron technologies below 10 nm • H...

Responsibilities: Collaborate with cross-functional teams on project deliverables. Optimize timing closure through innovative techniques. Perform physical verification using Synopsys tools.

ASIC Design Engineer Job Title: ASIC Design Engineer Experience: 14 years Education: B.E/B.Tech or M.Tech in EE, ECE, VLSI Responsibilities: Design RTL for ASIC blocks/IPs Perform logic synthesis and DFT insertion Work with verification and backend teams to close timing and area Debug issues in simulation, synthesis, and STA stages Ensure design complies with low power and clock domain constraints Requirements: Good knowledge of RTL coding, clock gating, and synthesis constraints Hands-on with Synopsys or Cadence design tools Familiarity with ASIC design flow

Meta is hiring talented individuals to join our Infrastructure organization as ASIC Frontend Implementation Engineers (RDC/CDC). In this role, you will play a critical part in designing and developing efficient System on Chip (SoC) and IP for data center applications.As an ASIC Frontend Implementation Engineer, your primary focus will be on the front-end implementation process and static verification tools, transforming RTL designs into optimized netlists. You will utilize your expertise in RTL Lint, CDC analysis, timing constraints, and synthesis to ensure seamless integration of various components to build efficient System on Chip (SoC) and IP for data center applications.By joining our te...

We are seeking a highly experienced Senior DFT Engineer with 8+ years of hands-on expertise in developing and implementing DFT architectures for complex SoCs. The ideal candidate should have a solid background in scan insertion, ATPG, BIST, and silicon debug. Key Responsibilities: Define and implement DFT architecture for digital and mixed-signal SoCs Perform scan insertion, boundary scan, and ATPG pattern generation Integrate Memory BIST (MBIST) and Logic BIST (LBIST) Drive DFT verification and post-silicon validation/debug Collaborate with RTL, synthesis, STA, and backend teams to ensure testability Ensure high test coverage, test time optimization, and compliance with ATE requirements Req...