Posted:2 hours ago|
Platform:
Work from Office
Full Time
The candidate will be responsible for implementing the place and route of design blocks including floorplanning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc . The candidate will also be responsible for block level physical design closure in terms of timing, power, DRC/LVS etc.
• 4-7 years of experience in ASIC Physical Design.
• Have good knowledge of entire physical design process from floorplan till GDSgeneration.
• Good Exposure to Physical Verification Process.
• Have hands-on experience in latest sub-micron technologies below 10 nm
• Hands on experience in leading PnR tools Synopsys ICC/ICC2
• Experience in low power designs and handling congestion or timing critical tiles will be preferred
• Should be a quick learner and have good attention to detail
• Experience in ECO implementation preferred
• Scripting skills in Perl/Tcl/Python etc
• Must have good communication & problem-solving skills.
• Should be able to handle PnR tasks with minimal supervision
Altcognito Systems
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