33 Caliber Jobs

Job Requirements At Quest Global, it's not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better placeto make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster. Key Responsibilities Key Responsibilities: Delivery Leadership Lead the Define and drive end-to-end RTL-to-GDSII flows, tai...

Hi Greetings!! Immediate openings for Leadsoc technologies pvt ltd. Role & responsibilities Expertise in Calibre DRC flows, DRC fixes. Preferred candidate profile 3+ PV Engineer Bangalore Immediate to 30 days Interested candidates can send updated resumes to basheer.unnisa@leadsoc.com or Contact HR Basheera- 8310938311.

Responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must. Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Excellent problem-solving skills in physical verification of custom layout. Demonstrate high quality and accurate execution to meet project schedule/milestones in multiple project environment. Ability to guide junior team-members in their execution of Sub block-level layouts & review critical items....

Job Description: Develop DRC/LVS runsets using Calibre and optimize rule decks. Support analog and physical design automation. Develop and debug P-cells/Pycells and layout scripts. Contribute to library development and design verification flows. Qualification: BS/MS in EE/CS with scripting and UNIX/Linux experience

Must have 3-5 of experience in standard cell layout, analog, mixed-signal and custom digital block designs in advanced CMOS process. Should have expertise in multiple standard cell layout library developments. Should be able to perform standard

1 Job Description for Memory Layout Location: Bangalore Experience : 3yrs-10 Yrs - Memory leaf cell layout development - Migration of layout from one tech node to another - Block and top level integration - Quality and timely delivery - EM-IR, area intensive layouts, Quality checks (QC) - Understanding of design rules for 90nm and below - Understanding of design rules for 14ff and 16ff is a plus. - Drive multiple projects and provide necessary technical guidance to the engineers - Understanding of DFM and DFY - Understanding of memory compiler architectures - Good debugging skills - Knowledge of scripting in PERL/Shell/TCL scripting etc - Proficient with tools like Cadence Virtuoso, Calibre ...

Role & responsibilities Leading a team of 3-5 engineers for block-level implementation. Collaborating with a cross-functional team for project planning and completion. Contribute to enhancement of methodologies and flow. Overseeing timing closure, power optimization, and physical verification using industry-standard EDA tools. Managing resources and schedules to ensure timely and quality deliverables. Technical leadership to analyze and debug complex issues and recommend. Supporting and developing best practices in design methodology, quality assurance, and continuous process improvement Preferred candidate profile Experience of Netlist-to-GDS design flow, including floor-planning, placement...

As a Layout Design Engineer at RFIC Solutions Inc., you will be responsible for the Layout design of RF and Analog circuits in a fast-paced environment. Your key responsibilities will include: - Excellent problem solving skill of DRC, LVS issues - Parasitic extraction of layout and layout quality checking - Custom layout experience must include high frequency circuits such as LNAs, Mixers, VCOs, etc. - Full familiarity with Cadence Virtuoso and ADS (Advance Design System) Caliber tools for 65nm and lower design processes - Full understanding of hierarchical planning (top down and bottom up) and integration To qualify for this role, you should have an M.Tech or BE/B.Tech in Electronics and Te...

Role Overview: Looking for experienced Physical Design Engineer with 4+ years in block-level implementation. The role emphasizes PnR, STA, and logic implementation, driving designs that meet PPA requirements while ensuring sign-off quality. Key Requirements: *Hands-on in floor planning, placement, CTS, routing, and optimization. *Strong background in PnR flows, resolving timing, congestion, power, and SI challenges. *Skilled in STA analysis, ECO handling, and top-level support. *Tool expertise with Synopsys / Cadence and logic equivalence checks. *Proficient in design rule checks (DRC/LVS) and PPA-driven optimizations. *Familiarity with low-power techniques and scripting (TCL, Perl, Python).

B.Sc. / MSc in Biotechnology or equivalent with 2-6+ years of experience in vaccines or biosimilar manufacturing _ handle instruments such as pH meter, Osmometer, Conductivity meter, and manage samples QC experience is desirable 8452025846

We’re hiring Analog Layout Engineers (3–7 years) with hands-on experience in lower technology nodes, layout design, and DRC/LVS verification. Location: Hyderabad. Immediate joiners preferred.

Looking for a Senior VLSI Engineer (PV) with 10+ years of experience in IC design front-to-backend flow, strong in Physical Verification, C-shell scripting, Tcl/Perl, and Linux/UNIX environments. Location: Bangalore. Required Candidate profile Experienced VLSI Physical Verification professional skilled in C-shell,Tcl, and Perl scripting with deep knowledge of IC design flow& UNIX/Linux environments. Proven expertise in semiconductor design.

Job Description A layout technical expert taking chip top ownership of analog-on-top ASIC developments. Hands-on technical contributor, able to take chiptop ownership including tape-out procedures. A teamplayer, able to collaborate within a global layout team and cross-discipline stakeholders. Required experience: 15+ years of experience in custom analog layout Experience with nodes in the range of 22nm-40nm-180nm is a must. Experience with BCD technologies is a must. Proven track record of owning chip top layout. Must be able to independently go through required tape-out procedures and take corrective actions. Must be able to take ownership of internal layout flows, continuously work on imp...

As a Lead Software Developer at Siemens Healthineers, you will have the opportunity to contribute to groundbreaking projects that directly impact patient care and drive advancements in the medical field. You will play a pivotal role in shaping the architecture of our platform and integrated software solutions. Collaborating with cross-functional teams, you will design, develop, and optimize an existing imaging system based on the syngo framework. Your responsibilities include leveraging your extensive experience in software development within an agile environment to deliver high-quality, scalable solutions. Demonstrating mastery in software development principles, you will apply your experti...

Knowledge of tools like measuring tape vernier caliber diallage, piler. O&M of utility equipment, pump motor, gearbox, boiler ETP. Alignments of pumps spider coupling. Knowledge of safety, PPE, PM, checklist, fill-up & planner. Team coordinator.

Role & responsibilities: The candidate will be responsible for implementing the place and route of design blocks including floorplanning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc . The candidate will also be responsible for block level physical design closure in terms of timing, power, DRC/LVS etc. Preferred candidate profile : • 4-7 years of experience in ASIC Physical Design. • Have good knowledge of entire physical design process from floorplan till GDSgeneration. • Good Exposure to Physical Verification Process. • Have hands-on experience in latest sub-micron technologies below 10 nm • H...

Roles and Responsibilities Design analog layouts using Cadence Virtuoso for FinFET devices with PLL and SerDes interfaces. Perform DRC, LVS, and mixed signal simulations to ensure design integrity. Collaborate with cross-functional teams to resolve design issues and optimize designs. Develop expertise in Caliber technology for high-speed I/O applications. Ensure compliance with industry standards and company guidelines.

We are hiring for our client for the role Analog Layout Engineer Exp - 4 to 8 Years Location - Hyderabad NP - Immediate to 20 Days Mode - WFO Job Description: Must have experience in System Verilog Must have experience UVM Test Must have experience Dram or Sram Must have experience DDR 4 or DDR 5 or LPDDR 4 or LPDDR 5 Must have experience AMS Verification

Responsibilities: * Design, test & verify physical designs using Primetime, Innovus & PNR. * Collaborate with cross-functional teams on floor planning & timing closure.

Physical design engineers - MNC BULK HIRE - 100% WFH MUST: 7 t0 14 YEARS AS physical design engineer MUST: 7+ years of experience in ASIC physical design , Strong with industry-standard tools (e.g., Innovus, ICC2, PrimeTime, Voltus, Calibre) Required Candidate profile Solid understanding of timing, signal integrity, IR drop, and physical verification Good scripting skills (TCL, Python, or Perl) for flow automation EXP with advanced nodes & UPF WHATSAPP@9108687980

We are looking for an experienced IO Layout Engineer to join our team in Bangalore. The role involves custom IO layout design, optimization, and sign-off at advanced technology nodes. Responsibilities: Create and optimize IO circuit layouts including ESD structures and analog IOs. Perform floor planning, placement, routing, and parasitic extraction. Ensure DRC, LVS, ERC compliance using industry-standard tools. Collaborate with circuit and verification teams for sign-off. Automate layout flows using scripting for better productivity. Required Skills: 3-8 years in IO / Custom Layout. Strong knowledge of Cadence Virtuoso and Calibre/Assura verification. Experience with advanced nodes (28nm & b...

You will be responsible for preparing and reviewing validation documents such as Area Qualification for new facilities, Factory Acceptance Test (FAT), Installation Qualification (IQ), Operational Qualification (OQ), Performance Qualification (PQ), Control System Qualification, commissioning, validation & re-qualification, and Revision Qualification for equipment/utilities/facilities. You will generate reports that summarize results, specifications, and acceptance criteria. Your role will also involve authoring documents in ValGenesis. In addition, you will track SOPs due for review, circulate them for comments, update comments, initiate change control, initiate ERA workflow, and follow up fo...

Application Deadline: 31 July 2025 Department: Finance Employment Type: Permanent Full Time Location: Gurgaon India Description Company Overview: At Lummus Technology, innovation thrives, and excellence is a shared pursuit When you join the Lummus Family, you are empowered to make an impact and be part of a dynamic team that celebrates creativity, encourages professional development, and fosters collaboration, From our technology portfolio to our global workforce, Lummus is growing at a rapid pace, and we hope that you will grow with us during this exciting time, Key Responsibilities Accounts payable, Receive approved invoices from facilities and other departments recipient of goods and 3rd ...

Role & responsibilities Leading a team of 3-5 engineers for block-level implementation. Collaborating with a cross-functional team for project planning and completion. Contribute to enhancement of methodologies and flow. Overseeing timing closure, power optimization, and physical verification using industry-standard EDA tools. Managing resources and schedules to ensure timely and quality deliverables. Technical leadership to analyze and debug complex issues and recommend. Supporting and developing best practices in design methodology, quality assurance, and continuous process improvement Preferred candidate profile Experience of Netlist-to-GDS design flow, including floor-planning, placement...

Responsibilities: Physical design verification and Power analysis. Experienced with usage of tools Calibre, Innovus and Voltus Hands on layout edits in Innovus and analysis of power reports from Voltus. Apply & share resume to mansoor@hisoltech.com