The candidate will be responsible for implementing the place and route of design blocks including floor planning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc. The candidate will also be responsible for block level physical design closure in terms of timing, power, DRC/LVS etc. REQUIREMENTS: 4-9 years of experience in ASIC Physical Design Have good Hands on entire physical design process from floorplan till GDS generation Good Exposure to Physical Verification Process Have hands-on experience in latest sub-micron technologies below 7nm Hands –on experience in leading PnR tools Synopsys ICC/ICC2 Experience in low power designs and handling congestion or timing critical tiles will be preferred Should be a quick learner and have good attention to detail Experience in ECO implementation preferred Scripting skills in Perl/Tcl/Python etc Must have good communication & problem-solving skills. Should be able to handle PnR tasks with minimal supervision Location :: Hyderabad & Bangalore *Adds on advantage atleast one or two projects has worked in AMD projects in his / her carier. Thanks, P Mohankrishna, Mohankrishna.p@Altcognitosystems.com Show more Show less
Job Description The candidate will be responsible for implementing the place and route of design blocks including floorplanning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc. The candidate will also be responsible for block-level physical design closure in terms of timing, power, DRC/LVS, etc. Requirements 3-8years of experience in ASIC Physical Design Have good knowledge of the entire physical design process from floorplan to GDSII generation Good Exposure to Physical Verification Process Have hands-on experience in the latest sub-micron technologies below 10 nm Hands–on experience in leading PnR tools Synopsys ICC/ICC2 Experience in low power designs and handling congestion or timing critical tiles will be preferred Should be a quick learner and have good attention to detail Experience in ECO implementation preferred Scripting skills in Perl/Tcl/Python etc Must have good communication & problem-solving skills. Should be able to handle PnR tasks with minimal supervision Show more Show less
Company Description Altcognito systems is a Established service comkany in VLSI and working with Good clients. Role Description This is a full-time on-site role for a Physical Design Engineer located in Hyderabad. The Physical Design Engineer will be responsible for performing physical design tasks, including floorplanning, placement, clock tree synthesis, routing, and physical verification. Qualifications 7+years of experience in Physical Design (PNR, Floorplan, STA & Lowernodes) Experience in Logic Design and Circuit Design Excellent analytical and problem-solving skills Strong communication and teamwork abilities Familiarity with industry-standard EDA tools is a plus Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
Job Description The candidate will be responsible for implementing the place and route of design blocks including floorplanning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc. The candidate will also be responsible for block-level physical design closure in terms of timing, power, DRC/LVS, etc. Requirements 3-8years of experience in ASIC Physical Design Have good knowledge of the entire physical design process from floorplan to GDSII generation Good Exposure to Physical Verification Process Have hands-on experience in the latest sub-micron technologies below 10 nm Hands–on experience in leading PnR tools Synopsys ICC/ICC2 Experience in low power designs and handling congestion or timing critical tiles will be preferred Should be a quick learner and have good attention to detail Experience in ECO implementation preferred Scripting skills in Perl/Tcl/Python etc Must have good communication & problem-solving skills. Should be able to handle PnR tasks with minimal supervision
Job Title: Lead Design Verification Engineer Location: m Bangalore Job Type: Full-time Experience Level: 7+ years Department: Hardware Engineering / VLSI Design Job Summary: We are seeking a highly experienced Lead Design Verification Engineer to lead verification efforts for complex digital designs. The ideal candidate will drive testbench architecture, verification planning, and execution for ASIC/SoC or FPGA-based designs, ensuring first-time-right silicon or system functionality. You will work closely with RTL design, DV, and system engineering teams to deliver high-quality products. Key Responsibilities: Lead and drive the verification strategy, planning, and execution for IP, subsystem, or full-chip level. Define and implement constrained-random, directed, and coverage-driven verification methodologies (UVM/SystemVerilog preferred). Develop and maintain scalable and reusable testbench components. Mentor and guide junior verification engineers in testbench architecture, debugging, and coverage closure. Collaborate with RTL designers, architects, and firmware/software teams to understand design intent and develop test plans. Own and track functional coverage metrics and ensure 100% coverage goals are met. Drive regular reviews of verification status, risks, and issues with stakeholders. Support post-silicon validation teams with test vectors, debugging, and failure analysis. Required Qualifications: Bachelors or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 7+ years of industry experience in digital design verification. Strong expertise in SystemVerilog, UVM, and advanced verification methodologies. Experience in testbench architecture, test planning, and constrained-random stimulus generation. Solid understanding of digital design concepts, SoC/ASIC design flows, and bus protocols (e.g., AXI, AHB, PCIe, etc.). Hands-on experience with simulation tools (VCS, Questa, etc.) and coverage analysis tools. Excellent debugging and problem-solving skills using waveform viewers and assertion-based techniques. Familiarity with scripting languages such as Python, Perl, or TCL for automation. Strong communication and leadership skills with experience leading small to mid-sized teams. Preferred Qualifications: Experience in formal verification techniques. Experience with emulation, FPGA prototyping, or post-silicon bring-up. Exposure to power-aware or low-power verification (UPF/CPF). Knowledge of hardware security, safety, or compliance standards (ISO 26262, DO-254, etc.) is a plus. Familiarity with CI/CD flows and version control (Git, Jenkins, etc.). Why Join Us: Work on cutting-edge technologies and next-generation chip designs. Opportunity to lead high-impact projects and influence verification strategy. Collaborative and innovative work environment. Competitive salary, benefits, and career growth opportunities.