237 Cts Jobs

Mega Walk in Drive is Going For International Voice Process (Salary 5LPA- 6LPA) Hiring for USA Leading Healthcare & Travel Process (International Voice Process) Call & WhatsApp No: 9147047910 9147047911 9007152957 Interview Venue: HBR, DN2, Signet Tower Unit 804 8th Floor College More Sector 5, Saltlake Kolkata - 700091 We are looking for enthusiastic professionals for International Healtcare Process who possess flawless communication and expertise in customer centric skills. Interested experienced candidates can share their updated CV on the below WhatsApp number for booking interview slot. Eligibility: Under Graduates and Graduates with one year International Voice Experience Salary - 3.20 LPA- 5.40LPA Required Super Excellent communication Skiils in English 5 working days Flexible to work in Night shifts Ready to work from Office Perks and Benefits. Permanent and full time opportunity One way cab facility Incentives and allowances Promotion with IJP Health Insurance/ PF/ ESI/ Incentive Call & WhatsApp No: 9147047910 9007152957 6290365641 9831388551 Interview Venue: HBR, DN2, Signet Tower Unit 804 8th Floor College More Sector 5, Saltlake Kolkata - 700091

Mega Walk in Drive is Going For International Voice Process (Salary 5LPA- 6LPA) Hiring for USA Leading Healthcare & Travel Process (International Voice Process) Call & WhatsApp No: 9147047910 9147047911 9007152957 Interview Venue: HBR, DN2, Signet Tower Unit 804 8th Floor College More Sector 5, Saltlake Kolkata - 700091 We are looking for enthusiastic professionals for International Healtcare Process who possess flawless communication and expertise in customer centric skills. Interested experienced candidates can share their updated CV on the below WhatsApp number for booking interview slot. Eligibility: Under Graduates and Graduates with one year International Voice Experience Salary - 3.20 LPA- 5.40LPA Required Super Excellent communication Skiils in English 5 working days Flexible to work in Night shifts Ready to work from Office Perks and Benefits. Permanent and full time opportunity One way cab facility Incentives and allowances Promotion with IJP Health Insurance/ PF/ ESI/ Incentive Call & WhatsApp No: 9147047910 9007152957 6290365641 9831388551 Interview Venue: HBR, DN2, Signet Tower Unit 804 8th Floor College More Sector 5, Saltlake Kolkata - 700091

Job Specs : Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements for the design. Set up and configure STA tools ( PrimeTime, StarRC, Tempus, Innovus and QRC ) for the analysis, including library characterization, delay models, and clock definitions Perform static timing analysis to evaluate setup and hold times, clock-to-q delays, and other timing metrics. Ensure that the design meets timing requirements for various corners and operating conditions (e.g., process, voltage, temperature variations). Identify and analyze asynchronous signals crossing between different clock domains to ensure proper synchronization and to avoid metastability issues. Define and analyze multicycle paths and false paths to accurately capture the designs timing constraints. Collaborate with RTL and physical design teams to achieve timing closure by optimizing the design or constraints. Perform incremental and formal ECO (Engineering Change Order) analysis to address timing issues. Work with CTS engineers to ensure that the clock tree meets timing requirements and minimizes clock skew and jitter. Perform post-layout STA to account for parasitic capacitance and resistance effects introduced during the physical design phase. Identify and resolve timing violations and sign-off on the final timing closure. Analyze timing margins to account for variability and manufacturing process variations, ensuring robust operation. Prepare detailed timing analysis reports, including timing paths, violations, and suggestions for timing optimization. Collaborate closely with RTL designers, physical designers, DFT (Design for Test) engineers, and verification teams to resolve timing-related issues. Contribute to the development and improvement of STA methodologies and flows to enhance efficiency and accuracy.Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Vietnam are the preferred work locations Preferred resources with valid regional work permit.

About The Role Project Role : Software Development Lead Project Role Description : Develop and configure software systems either end-to-end or for a specific stage of product lifecycle. Apply knowledge of technologies, applications, methodologies, processes and tools to support a client, project or entity. Must have skills : Automotive ECU Software Good to have skills : NA Minimum 12 year(s) of experience is required Educational Qualification : Bachelors degree in Computer Science Electronics or related field Summary :We are seeking an experienced BSP Developer to architect and implement Android-based infotainment platforms, with a focus on Android 15 BSP customization. This role involves driver adaptation, kernel modifications, and system-level integration for automotive-grade infotainment systems. The ideal candidate will have deep expertise in embedded systems, Android Automotive OS, and compliance testing frameworks such as CTS, VTS, and STS. Roles & Responsibilities:1.Architecture & Development:Design and develop BSP components for Android-based infotainment platforms.2.Customization:Customize Android 15 BSP, including kernel and driver adaptations for automotive SOCs.3.System Services & HAL:Implement and optimize system services and HAL layers for infotainment features.4.Compliance Testing:Conduct CTS, VTS, and STS testing to ensure platform compatibility and stability.5.Debugging & Troubleshooting:Diagnose and resolve system-level issues across software and hardware interfaces.6.Collaboration:Work closely with Android porting, BSP, and integration teams across global locations.7.Documentation & Standards:Ensure alignment with Android Compatibility Definition Document (CDD) and maintain technical documentation. Professional & Technical Skills: 1.Years of experience in embedded systems and Android infotainment development.2.Strong expertise in Android Automotive OS and Android 15 BSP.3.Deep knowledge of Linux kernel customization and driver integration.4.Experience with Samsung Automotive SOCs and custom IVI platforms.5.Proficiency in implementing system services and HAL layers.6.Familiarity with Android architecture and CDD standards.7.Hands-on experience with CTS, VTS, and STS compliance testing.8.Strong debugging and problem-solving skills.9.Experience with GIT, Android build systems, and development tools.10.Exposure to infotainment hardware setups and cloud platforms.11.Experience working in Agile environments and global delivery models Additional Information:- The candidate should have minimum 14 years of experience in Automotive ECU Software.- This position is based at our Bengaluru office.- A Bachelors degree in Computer Science, Electronics or related field is required. Qualification Bachelors degree in Computer Science Electronics or related field

Excellent communication required. US Customer Service voice process. We are looking to hire candidates from Gurgaon and for Kolkata location Minimum 6 months of experience is required in International voice process. Customer Service Executive Customer Support Executive - Virtual Interview only Blended process (voice Process) 2 days rotational off. US or Night shift Work From Office Good communication required Immediate joining required Pls call Durga 9884244311 for more info. Thanks, Durga 9884244311

Hi, US Customer Support associate / Process associate / BPO/ US Shift We are hiring for customer care for US shift for US voice process Roles & Responsibilities:- Listen to customers concerns, issues and questions. Resolve customers concerns and answer customers questions to your best ability. Maintain a positive attitude and calmly respond to customers complaints. Open new customer accounts Refer issues and questions to managers if necessary Qualifications:- - Graduate Freshers Undergraduate with experience can apply - Excellent and fluent communication skills - Freshers to 4 year Experience in any domain Additional Information:- - International Voice Process - 24*7 Rotational shift - 5 days working - Location Chennai & Bangalore Immediate joining is required or short notice is required Pls call Lokesh 9176197272 for more info Thanks, Lokesh 9176197272

We have vacancy for international voice process with our Client for various location. Working days: 5 Days working, 2 rotational off Freshers or Experience: 1 year in Customer service (Voice/ Non-Voice) Salary upto 3.5 lakhs + Allowance + Incentives Roles and Responsibilities Ability to engage in communication and build a conversation around it Building relationships on Chat and Emails. Ability to handle pressure and meet deadlines. Ability to successfully work as a part of a team. Must be an immediate Joiner with Good communication skills. Immediate joining required. Good communication Pls call Santoshi 9176198282 for more info Thanks, Santoshi 9176198282

BPO / Call Center / Day Shift / Graduate / Customer Care Executive Domestic & International Voice Process Profile -CCE Voice Salary - 18k to 30k CTC Day Shift / US Shift Immediate Joiners No Placement Charges Required Candidate profile Min.12th pass Fresher & Experience English Must be Good Please call Divya 9514466618 for more info Thanks, Divya 9514466618

Physical Deisgn Lead Location: Bangalore / Hyderabad / Pune Experience - 8+ YoE In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl. Must have hands-on experience on Synopsys/Cadence tools. (Innovus, ICC2, Primetime, PT-PX, Calibre). Well versed with timing constraints, STA and timing closure. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl Well versed with timing constraints, STA and timing closure. Mandatory Skills: VLSI Physical Place and Route. Experience: 5-8 Years.

As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. **Key Responsibilities:** - 8-10 years hands-on experience of different PnR steps including Floorplanning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation and DRC closure - Well versed with high frequency design & advanced tech node implementations - In-depth understanding of PG-Grid optimization, including identification of high vs low current density paths & layer/via optimization, Adaptive PDN experience - In-depth knowledge of custom clock tree including H-tree, SPINE, Multi-point CTS, Clock metrics optimization through tuning of CTS implementation. - Well versed with tackling high placement density/congestion bottlenecks - In-depth knowledge of PnR tool knobs/recipes for PPA optimization - Experience in automation using Perl/Python and tcl - Good communication skills and ability & desire to work in a cross-site cross-functional team environment **Qualifications Required:** - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience - OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience - OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. Qualcomm also expects its employees to abide by all applicable policies and procedures, including security and other requirements regarding the protection of confidential information.,

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life's work , to amplify human creativity and intelligence. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! NVIDIA is seeking passionate, highly motivated, and creative design engineers to be part of a team working on industry-leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. What you'll be doing: In this position, you will expected to lead all block/chip level PD activities. PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification. Work in collaboration with design team for addressing design challenges. Help team members in debugging tool/design related issues. Constantly look for improvement in RTL2GDS flow to improve PPA. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets. What we need to see: BE/BTECH/MTECH, or equivalent experience. 1+ years of experience in Physical Design. Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure. Expertise on high frequency design methodologies. Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Working experience with tools like ICC2/Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation. Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred. Well versed with timing constraints, STA and timing closure. Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools. Ability to multi-task and flexibility to work in global environment. Good communication skills and strong motivation, Strong analytical & Problem solving skills. Proficiency using Perl, Tcl, Make scripting is preferred. Widely considered to be one of the technology world's most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family NVIDIA is committed to encouraging a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. #LI-Hybrid

Job Area :Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3 to 5 years hands-on experience of different PnR steps including Floorplanning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation and DRC closure Well versed with high frequency design & advanced tech node implementations In depth understanding of PG-Grid optimization, including identification of high vs low current density paths & layer/via optimization, Adaptive PDN experience In depth knowledge of custom clock tree including H-tree, SPINE, Multi-point CTS, Clock metrics optimization through tuning of CTS implementation. Well versed with tackling high placement density/congestion bottlenecks In depth knowledge of PnR tool knobs/recipes for PPA optimization Experience in automation using Perl/Python and tcl Good communication skills and ability & desire to work in a cross-site cross-functional team environment.

Job Area :Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Responsibilities: STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Work on automation scripts within STA/PD tools for methodology development. Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment Experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus Familiar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo. Education : B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI. Preferred Qualification/Skills 5 - 10 years of experience in STA/Timing Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling Hands-on experience with STA tools - Prime-time, Tempus Have experience in driving timing convergence at Chip-level and Hard-Macro level In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling, Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus) Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation. Proficient is scripting languages TCL, Perl, Awk Basic knowledge of device physic

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 12+ years hands-on experience of different PnR steps including Floorplanning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation and DRC closure Well versed with high frequency design & advanced tech node implementations In depth understanding of PG-Grid optimization, including identification of high vs low current density paths & layer/via optimization, Adaptive PDN experience In depth knowledge of custom clock tree including H-tree, SPINE, Multi-point CTS, Clock metrics optimization through tuning of CTS implementation. Well versed with tackling high placement density/congestion bottlenecks In depth knowledge of PnR tool knobs/recipes for PPA optimization Experience in automation using Perl/Python and tcl Good communication skills and ability & desire to work in a cross-site cross-functional team environment.

Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. PD JD: Thorough knowledge of the ASIC designs Place and Route flow and methodology. Hands-on experience in executing complete PD ownership from netlist to GDS2 including HM level PV, LEC, low-power checks and PDN, STA closure Hands-on experience in Voltage Islands and low power methodologies, flows and implementation. Strong background in debugging Congestion and CTS issues. Expertise in PnR tools (Innovus/Fusion compiler) and flow. Familiarity with Sign-off(PV/PDN/STA/FV/CLP/Scan-DRC(tk)) methodology and tools. Understand and implement improving existing methodologies and flows. Proficient in scripting languages (TCL,PERL,PYTHON). Self-starter and highly motivated To have working experience in global team environment. To be effectively communicate the status and issues of respective owned Tasks 4-10 yrs of experience in physical design including floorplanning, PNR, CTS and signoff checks

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. General Summary PNR implementation for Qualcomm Hexagon NPU Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux Perl/TCL fundamentals/scripting Principal Duties and responsibilities: Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications: 5+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm - A Must

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Overview: Experienced STA/Timing Engineer with 3-10 Years of hands-on experience on timing sign off/convergence for complex SOCs. Ability to start immediately on timing analysis/sign-off with PD/Methodology teams across multiple sites and different technology nodes. Job Description : STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Work on automation scripts within STA/PD tools for methodology development. Good Technical writing and Communication skills. Willing to work in cross-collaborative environment. Experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus Familiar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo. Education : B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI. Preferred Qualification/Skills Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling. Hands-on experience with STA tools - Prime-time, Tempus Have experience working on timing convergence at Chip-level and Hard-Macro level. In-depth knowledge crosstalk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling, Knowledge of ASIC back-end design flows, methods, and tools (ICC2, Innovus) Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation. Proficient is scripting languages TCL, Perl, Python Basic knowledge of device physics

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. 2+ years hands-on experience of different PnR steps including Floorplanning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation and DRC closure Well versed with high frequency design & advanced tech node implementations In depth understanding of PG-Grid optimization, including identification of high vs low current density paths & layer/via optimization, Adaptive PDN experience In depth knowledge of custom clock tree including H-tree, SPINE, Multi-point CTS, Clock metrics optimization through tuning of CTS implementation. Well versed with tackling high placement density/congestion bottlenecks In depth knowledge of PnR tool knobs/recipes for PPA optimization Experience in automation using Perl/Python and tcl Good communication skills and ability & desire to work in a cross-site cross-functional team environment.

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. 5+ years of experience in physical design is mandatory for this position Physical Implementation activities for high performance Cores for 16/14/7/5nm or lower technologies, which includes all or some of the below. Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), Low Power verification, PDN, Timing Closure and / or power optimization Exposure to PD implementation of PPA critical cores. Exposure to timing convergence of high frequency data-path intensive Cores and advanced STA concepts. Able to handle Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes. Understanding of clocking architecture. Tcl/Python/Perl Scripting aware for small automation Strong problem-solving skills , good communication skills and good team player Collaborate with design, DFT and PNR teams and support issue resolutions wrt constraints validation, verification, STA, Physical design, etc.

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Responsibilities: STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Work on automation scripts within STA/PD tools for methodology development. Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment Experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus Familiar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo. Education : B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI. Preferred Qualification/Skills 5 - 10 years of experience in STA/Timing (Mandatory) Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling Hands-on experience with STA tools - Prime-time, Tempus Have experience in driving timing convergence at Chip-level and Hard-Macro level In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling, Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus) Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation. Proficient is scripting languages TCL, Perl, Awk Basic knowledge of device physic

Qualcomm India Private Limited is at the forefront of technology innovation, breaking boundaries to enable next-generation experiences and driving digital transformation for a smarter, connected future. As a Hardware Engineer at Qualcomm, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to launch world-class products. Collaboration with cross-functional teams is key to developing solutions that meet performance requirements. To be considered for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field with at least 2 years of Hardware Engineering experience. Alternatively, a Master's degree with 1+ year of relevant experience or a PhD in a related field is also accepted. As an experienced STA/Timing Engineer with 3-10 years of hands-on experience, you will focus on timing sign-off and convergence for complex SOCs. Immediate involvement in timing analysis and sign-off with PD/Methodology teams across different sites and technology nodes is expected. Key responsibilities include: - STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs. - Timing analysis, validation, and debug across multiple PVT conditions using tools like PT/Tempus. - Running Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. - Evaluating timing methodologies/tools on different designs and technology nodes. - Developing automation scripts within STA/PD tools for methodology enhancement. - Proficiency in TCL/Perl/Python for design automation and familiarity with digital flow design implementation. - Knowledge of process technology enablement, including circuit simulations and Monte Carlo. Preferred qualifications and skills include: - Expertise in STA timing analysis, AOCV/POCV concepts, CTS, and managing timing constraints. - Hands-on experience with STA tools like Prime-time and Tempus at Chip-level and Hard-Macro level. - Understanding of crosstalk noise, Signal Integrity, Layout Parasitic Extraction, and ASIC back-end design flows. - Proficiency in scripting languages such as TCL, Perl, and Python. - Basic knowledge of device physics. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. For more information or accommodation requests, please contact disability-accommodations@qualcomm.com. Staffing and recruiting agencies are advised not to submit unsolicited profiles, applications, or resumes through Qualcomm's Careers Site. If you are ready to be part of a dynamic team pushing technological boundaries, apply now to join Qualcomm as a Hardware Engineer.,

Qualcomm India Private Limited is a leading technology innovator that is dedicated to pushing the boundaries of what's possible in order to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This includes working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. To be considered for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 3 years of Hardware Engineering experience. Alternatively, a Master's degree with 2+ years of experience or a PhD with 1+ year of experience is also acceptable. The ideal candidate will have 5 to 8 years of hands-on experience in different PnR steps including Floorplanning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation, and DRC closure. Furthermore, expertise in high frequency design, advanced tech node implementations, PG-Grid optimization, custom clock tree design, placement density/congestion management, and PnR tool optimization is required. Proficiency in automation using Perl/Python and tcl, as well as excellent communication skills and the ability to work effectively in a cross-functional team environment, are also essential. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. Reasonable accommodations are available for applicants who require assistance during the application/hiring process. It is expected that all employees at Qualcomm adhere to company policies and procedures, including those related to security and confidentiality. Staffing and recruiting agencies are advised that the Qualcomm Careers Site is intended for individuals seeking direct employment opportunities with Qualcomm and unsolicited submissions will not be considered. For further information about this role, please reach out to Qualcomm Careers for assistance.,

As a Senior Software Engineer specializing in SAP Basis at Marlabs Innovations Pvt Ltd in Bangalore, India, you will be an integral part of our Global Technical Team managing multiple SAP systems. With 5-8 years of experience and a degree in Computer Science, Information Systems, or a related field, you will bring your expertise to oversee all aspects of Application Life Cycle Management for systems like ECC, BW, XI/PI, and more. Your responsibilities will include providing L2/L3 level support, performing system upgrades and patches, optimizing system performance through monitoring and analysis, managing database administration for various platforms, maintaining system integrity, providing technical support for SAP issues, and creating and maintaining SAP Basis documentation. Your role will also involve collaborating with cross-functional teams, driving continuous improvement initiatives, supporting Lean Sigma programs, and adhering to company policies and industry standards. To succeed in this role, you must possess strong analytical and problem-solving skills, demonstrate the ability to work autonomously in a fast-paced environment, and have a self-motivated work ethic. Your capacity to meet SLA timelines, stay up to date with relevant SOPs, and manage multiple priorities with a sense of urgency will be crucial. Additionally, you should be willing to travel occasionally, work on-call as needed, and be flexible with shift timings. At Marlabs, we are dedicated to creating a diverse and inclusive workplace where all employees are valued and respected. As an equal opportunity employer, we consider all candidates based on their qualifications, without discrimination based on race, gender, age, or any other characteristic protected by law. Join us in driving innovation and success through collaboration, excellence, and continuous learning.,

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 5+ years hands-on experience of different PnR steps including Floorplanning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation and DRC closure Well versed with high frequency design & advanced tech node implementations In depth understanding of PG-Grid optimization, including identification of high vs low current density paths & layer/via optimization, Adaptive PDN experience In depth knowledge of custom clock tree including H-tree, SPINE, Multi-point CTS, Clock metrics optimization through tuning of CTS implementation. Well versed with tackling high placement density/congestion bottlenecks In depth knowledge of PnR tool knobs/recipes for PPA optimization Experience in automation using Perl/Python and tcl Good communication skills and ability & desire to work in a cross-site cross-functional team environment.

BPO / Call Center / Day Shift / Graduate / Customer Care Executive Domestic & International Voice Process Profile -CCE Voice Salary - 18k to 30k CTC Day Shift / US Shift Immediate Joiners No Placement Charges Required Candidate profile Min.12th pass Fresher & Experience English Must be Good Plesae call Bhavna 9884634937 for more info Thanks, Bhavna 9884634937