134 Cts Jobs

As a Physical Design Engineer with 2 to 8 years of experience, you should have a minimum of 2 years of experience in Physical Design. You must have hands-on experience in ICC2 and have worked on PnR, Floorplan, and CTS. Being self-motivated, possessing good communication skills, and being a team player are essential qualities for this role. The job location for this position is in Delhi/NCR.,

We have vacancy for international voice process with our Client for various location. Working days: 5 Days working, 2 rotational off Freshers or Experience: 1 year in Customer service (Voice/ Non-Voice) Salary upto 5 lakhs + Allowance + Incentives Roles and Responsibilities Ability to engage in communication and build a conversation around it Building relationships on Chat and Emails. Ability to handle pressure and meet deadlines. Ability to successfully work as a part of a team. Must be an immediate Joiner with Good communication skills. Immediate joining required. Good communication Pls call Nivetha 9884676582 for more info Thanks, Nivetha 9884676582

BPO / Call Center / Day Shift / Graduate / Customer Care Executive Domestic & International Voice Process Profile -CCE Voice Salary - 18k to 30k CTC Day Shift / US Shift Immediate Joiners No Placement Charges Required Candidate profile Min.12th pass Fresher & Experience English Must be Good Plesae call Durga 9884244311 for more info Thanks, Durga 9884244311

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems "which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl /Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Bachelor's/ Masters degree in Electrical /Electronic Engineering from reputed institution 2-10 years of experience in Physical Design/Implementation Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

You should be a PNR Lead with over 8 years of experience, based in Bangalore. Your role will involve handling Full chip PnR tasks such as timing, congestion, and CTS issues, with an understanding of IO ring, package support, and multi-voltage design. It is crucial to have a deep understanding of synthesis, place & route, CTS, timing convergence, IR/EM checks, and signoff DRC/LVS closure. Your responsibilities will include independently planning and executing all aspects of physical design, such as floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, and DFM. You must have experience participating in all design stages including floor planning, placement, CTS, routing, physical verification, and IREM. Furthermore, your expertise should cover timing closure methodologies, DRC, LVS, ERC, and PERC rule files for lower tech node layout verification. Experience in lower tech nodes (<7nm) is required, along with strong automation skills in PERL, TCL, and EDA tool-specific scripting. You should be capable of taking complete ownership of a Block/sub-system throughout the execution cycle and possess out-of-the-box thinking to meet tighter PPA requirements.,

Hi, US Customer Support associate / Process associate / BPO/ US Shift We are hiring for customer care for US shift for US voice process Hyderabad - Minimum 6 months of experience is required. Job description We are looking for process associate for International voice process who can interact with customers address their concerns, answer their questions and assist them with their needs. also who are able to join immediately Roles & Responsibilities:- Listen to customers concerns, issues and questions. Resolve customers concerns and answer customers questions to your best ability. Maintain a positive attitude and calmly respond to customers complaints. Open new customer accounts Refer issues and questions to managers if necessary Qualifications:- - Graduate Freshers Undergraduate with experience can apply - Excellent and fluent communication skills - Freshers to 4 year Experience in any domain Additional Information:- - International Voice Process - 24*7 Rotational shift - 5 days working - Location Chennai & Bangalore Immediate joining is required or short notice is required Pls call sangeeta 9176078282 for more info Thanks, sangeeta 9176078282

We are seeking a highly experienced Senior Physical Design Engineer with 8+ years of experience in block-level and full-chip physical implementation. The candidate should be proficient in physical design flows and methodologies for advanced technology nodes. Key Responsibilities: Drive physical implementation from RTL to GDSII (floorplanning, placement, CTS, routing) Perform timing analysis, congestion analysis, and physical verification (DRC/LVS) Optimize for performance, power, and area (PPA) Collaborate closely with RTL, STA, DFT, and package teams Own signoff checks (IR drop, EM, Antenna, Crosstalk, etc.) Support tape-out and silicon validation activities Requirements: 8+ years of experience in physical design implementation and signoff Strong hands-on experience with tools like ICC2, Innovus, Primetime, RedHawk, Calibre Solid understanding of timing closure, IR/EM analysis, and power optimization Experience with advanced nodes (7nm, 5nm, etc.) is a plus Good scripting skills (TCL, Perl, Python) for automation Strong communication and teamwork skills

As a Senior Physical Design Engineer, you will be responsible for leading the Netlist-to-GDSII implementation process on advanced submicron technology nodes. Your expertise in utilizing industry-standard EDA tools and your understanding of timing closure and physical verification will be crucial for this role. Your key responsibilities will include driving the entire Netlist-to-GDSII flow, which involves tasks such as floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. You will also be required to conduct Static Timing Analysis (STA) to ensure timing closure across all design corners, as well as execute power integrity and physical verification checks (LVS, DRC). Collaboration with cross-functional teams including RTL, STA, packaging, and DFT will be essential to successfully handle complex designs on 28nm and below technology nodes. To excel in this role, you must possess strong hands-on experience with tools such as Synopsys/Cadence Innovus, ICC2, Primetime, PT-PX, and Calibre, along with a solid understanding of Physical Design Methodologies including Floorplanning, Placement, CTS, Routing, and STA. Proficiency in timing constraints and closure, Tcl/Tk/Perl scripting, and working with submicron nodes (28nm and below) are also essential skills required for this position. While not mandatory, familiarity with Fusion Compiler, a broader understanding of signal and power integrity, as well as experience in workflow automation and tool scripting would be considered advantageous for this role. If you are excited about the prospect of taking on this challenging and rewarding opportunity, we encourage you to submit your resume to hemanth@neualto.com or spoorthy@neualto.com to express your interest.,

You are a Physical Design Engineer with 2-5 years of hands-on experience in different PnR steps including Floor planning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation, and DRC closure. You should be well versed with high frequency design & advanced tech node implementation, in-depth understanding of PG-Grid optimization, custom clock tree design, and tackling high placement density/congestion bottlenecks. Your expertise should include identifying high vs low current density paths, layer/via optimization, and Adaptive PDN experience. You must have knowledge of custom clock tree designs such as H-tree, SPINE, Multi-point CTS, Clock metrics optimization through tuning of CTS implementation. Familiarity with PnR tool knobs/recipes for PPA optimization is essential. Experience in automation using Perl/Python and tcl is required. Good communication skills are necessary as you will be working in a cross-site cross-functional team environment. The ideal candidate will have a BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or an equivalent field with a minimum of 3 years of relevant experience. This is a great opportunity to be part of a fast-paced team responsible for delivering high-performance designs for high performance SoCs in sub-10nm process for the mobile space.,

Job Requirements Key Responsibilities: Execute floorplanning, power planning, placement, CTS, routing, DRC/LVS, and timing closure for blocks/subsystems. Work on multi-voltage designs using UPF, level shifters, isolation cells, and retention strategies. Perform timing analysis and closure using PrimeTime and support IR/EM/Noise closure under guidance. Collaborate with DFT/RTL/STA teams to resolve integration and physical challenges. Run power optimization techniques at synthesis and post-route stage. Support subsystem-level integration and participate in debug and convergence discussions. Write scripts (Python, Tcl) for flow automation, data mining, and report generation. Required Skills: Hands-on experience with full RTL-to-GDS flow using Fusion Compiler, Innovus. Working knowledge of low power flows, UPF, VCLP, power intent checks. Familiarity with timing closure concepts, signal integrity, and power optimization. Good scripting skills in Python/Tcl/Perl for design automation. Enthusiastic team player with strong analytical and debugging skills. Work Experience Key Responsibilities: Execute floorplanning, power planning, placement, CTS, routing, DRC/LVS, and timing closure for blocks/subsystems. Work on multi-voltage designs using UPF, level shifters, isolation cells, and retention strategies. Perform timing analysis and closure using PrimeTime and support IR/EM/Noise closure under guidance. Collaborate with DFT/RTL/STA teams to resolve integration and physical challenges. Run power optimization techniques at synthesis and post-route stage. Support subsystem-level integration and participate in debug and convergence discussions. Write scripts (Python, Tcl) for flow automation, data mining, and report generation. Required Skills: Hands-on experience with full RTL-to-GDS flow using Fusion Compiler, Innovus. Working knowledge of low power flows, UPF, VCLP, power intent checks. Familiarity with timing closure concepts, signal integrity, and power optimization. Good scripting skills in Python/Tcl/Perl for design automation. Enthusiastic team player with strong analytical and debugging skills.

Hi, US Customer Support associate / Process associate / BPO/ US Shift We are hiring for customer care for US shift for US voice process Hyderabad - Minimum 6 months of experience is required. Job description We are looking for process associate for International voice process who can interact with customers address their concerns, answer their questions and assist them with their needs. also who are able to join immediately Roles & Responsibilities:- Listen to customers concerns, issues and questions. Resolve customers concerns and answer customers questions to your best ability. Maintain a positive attitude and calmly respond to customers complaints. Open new customer accounts Refer issues and questions to managers if necessary Qualifications:- - Graduate Freshers Undergraduate with experience can apply - Excellent and fluent communication skills - Freshers to 4 year Experience in any domain Additional Information:- - International Voice Process - 24*7 Rotational shift - 5 days working - Location Chennai & Bangalore Immediate joining is required or short notice is required Pls call sangeeta 9176078282 for more info Thanks, sangeeta 9176078282

Excellent communication required. US Customer Service voice process. We are looking to hire candidates from Gurgaon and for Kolkata location Minimum 6 months of experience is required in International voice process. Customer Service Executive Customer Support Executive - Virtual Interview only Blended process (voice Process) 2 days rotational off. US or Night shift Work From Office Good communication required Immediate joining required Pls call Bhavna 9884634937 for more info. Thanks, Bhavna 9884634937

Marlabs Innovations Pvt Ltd is seeking a Senior Software Engineer - SAP Basis with 5-8 years of experience. The ideal candidate should have a Bachelor's degree in Computer Science, Information Systems, or a related field, or equivalent experience. You should be able to work in a virtual environment, effectively prioritize tasks in a high-pressure setting, and demonstrate autonomy and self-motivation in a fast-paced and complex work environment. It is essential to have the ability to meet SLA timelines, stay updated with relevant SOPs, and possess an analytical mind with problem-solving skills. As a Senior Software Engineer - SAP Basis, you will be responsible for providing L2/L3 level support for multiple SAP systems like ECC, BW, XI/PI, SCM, SOLMAN, BOBJ, EP, GRC, HCM, and non-SAP components. Your role will involve overseeing all aspects of Application Life Cycle Management, database administration with a focus on ORACLE, MS SQL, HANA DB, as well as maintaining the integrity of SAP and non-SAP environments. You will also be required to provide technical support for SAP issues, perform system refreshes, client copies, server migrations, and create/maintain documentation related to SAP Basis operations. Moreover, you will need to liaise with cross-functional teams and business users to drive continuous improvement initiatives, support Lean Sigma programs, and ensure compliance with the company's safety and quality policies. The position may require 10% global travel, occasional on-call work, and a willingness to work outside regular shift timings. Marlabs Innovations Pvt Ltd is an equal opportunity employer committed to fostering a diverse and inclusive workplace based on qualifications rather than characteristics protected by law. If you meet the requirements and are looking to join a dynamic team focused on digital solutions and data-driven outcomes, we encourage you to apply for the Senior Software Engineer - SAP Basis position at Marlabs Innovations Pvt Ltd.,

The candidate we are looking for should be proficient in performance tuning, troubleshooting, and proactive maintenance with the goal of providing excellent system reliability, performance, maintaining system integrity, and maximizing uptime. As a part of the global technical team, you should be flexible to adapt to dynamic environments and motivated to drive daily operations, recommendations, and management of improvement initiatives across the landscape. Key responsibilities include providing SAP Basis L2/L3 level support as part of the Global Technical Team managing multiple SAP systems like ECC, BW, XI/PI, SCM, SOLMAN, BOBJ, EP, GRC, HCM along with non-SAP components like SEAL, TREX, IXOS, IDOS, and all aspects of Application Life Cycle Management. Hands-on experience in migrating SAP workloads from on-prem to Azure cloud and performing S4 Hana upgrades is essential. You will be responsible for identifying problem trends, evaluating performance statistics, and daily monitoring to optimize SAP systems. Proficiency in database administration with a focus on ORACLE, MS SQL, HANA DB, and underlying operating systems is required. Additionally, you should be proficient in SAP Printer/Spool administration, maintaining the integrity of SAP & Non-SAP environments, and creating & maintaining SAP Basis documentation. Adherence to SAP Basis on-call support, liaising with cross-functional teams and business users, and providing technical support for SAP issues are also part of the role. An analytical mind with a problem-solving aptitude is crucial for success in this position. The ideal candidate should have 7-10 years of related work experience and a Bachelor's degree in Computer Science, Information Systems, or a related field. Knowledge of Lean Sigma is preferred but not required. Ability to work in a virtual environment, effectively prioritize tasks in a high-pressure environment, work autonomously, and manage multiple priorities with a sense of urgency are essential skills. Compliance with company policies, safety, and quality standards is a must. You should be willing to travel up to 10%, including global travel, and be available for rotational on-call work. A proactive approach towards continuous learning, unlearning, and relearning is encouraged at YASH, which offers a career-oriented skilling model and a supportive team environment. Our workplace is based on principles of flexible work arrangements, free spirit, emotional positivity, agile self-determination, trust, transparency, open collaboration, support for the realization of business goals, stable employment, and an ethical corporate culture.,

SENIOR PHYSICAL DESIGN ENGINEER SmartSoC is looking for smart and enterprising Physical Designer Engineers to come to join us and get an opportunity to do some cutting-edge work and also work in a great environment where work is Always Fun and Exciting. This role will involve Physical design at the block and chip level of complex designs in the latest technologies. Desired Skills and Experience- 3 – 10 years relevant experience Excellent hands-on P&R skills with expert knowledge in ICC/Innovus Expert knowledge in all aspects of PD from Synthesis to GDSII, Strong background of Floor planning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing and Signal Integrity closure Experience at taping out multiple chips, strong experience at top level at latest technology nodes Job Category VLSI (Silicon engineering) Job Location IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia Singapore

Physical Design Engineer Experience 4-10 yrs Job Overview: Strong background of ASIC Physical DesignFloor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity.. Hands-on experience on technology nodes like 5nm,7nm, 14nm, 10nm. Good knowledge of EDA tools from Synopsys, Cadence and Mentor Hands-on experience in floor planning, placement optimizations, CTS and routing. Hands-on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC, VOLTAS) Job Category VLSI (Silicon engineering) Job Location IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida

You should have at least 3+ years of relevant experience leading SoC Physical design projects across multiple technology nodes, including 5nm for TSMC and other foundries. Your expertise should include hands-on Place and Route (P&R) skills with in-depth knowledge of ICC/Innovus. You must possess expert knowledge in all phases of Physical Design (PD) from Synthesis to GDSII, with a solid background in Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure. Experience in taping out multiple chips and strong familiarity with the top level at the latest technology nodes will be beneficial. Collaboration with CAD, Methodology & IP teams is a crucial aspect of PD implementation, necessitating regular sync-ups for deliveries. You should have significant knowledge and preferably hands-on experience in SoC Static Timing Analysis (STA), Power analysis, Physical Verification, and other sign-off processes. Strong problem-solving abilities, a proactive approach, hard work ethic, and excellent interpersonal skills are essential for this role. A Bachelor's Degree in Electrical, Electronics, or Computer Engineering is required. About Company: 7Rays Semiconductor Private Ltd. provides end-to-end custom SoC design solutions, encompassing SoC Architecture, RTL design, Design verification, DFT, Physical Design, and Analog design. Our focus is on serving top semiconductor and system companies to facilitate the design of their complex SoCs. We prioritize building effective partnerships with our clients to deliver high-quality, tailored solutions. With a dedicated engineering team and a proven history of successful project execution, we are dedicated to excellence and innovation in SoC Design, Development, and deployment of customer products.,

The Sr. Staff Physical Design Engineer position at Lattice Semiconductor in Pune, India offers a dynamic opportunity to join the HW design team focused on IP design and full chip integration. As part of a worldwide community of engineers and specialists, you will have the chance to contribute, learn, innovate, and grow within this fast-paced and ambitious organization. Key responsibilities for this role include implementing and leading the RTL to GDSII flow for complex designs, working on various aspects of physical design such as place & route, CTS, routing, floorplanning, powerplanning, timing, and physical signoff. The ideal candidate will have experience in physical design signoff checks, drive efficiency and quality in physical design flow and methodology, collaborate with internal and external teams, and possess scripting knowledge to enhance design efficiency. Additionally, the successful candidate will play a vital role in FPGA design efforts, drive physical design closure of key ASIC blocks & full chip, maintain design quality through quality checks and signoff, develop strong relationships with global teams, mentor colleagues, and may require occasional travel. Requirements for this role include a BS/MS/PhD in Electronics Engineering, Electrical Engineering, Computer Science or equivalent, along with 12+ years of experience in driving physical design activities for ASIC blocks and full chips. Candidates must have multiple tapeout experience and proficiency in industry-standard physical design tools. The ideal candidate should be an independent problem solver, capable of collaborating with diverse groups across different sites and time zones. Lattice Semiconductor values its employees as the cornerstone of its success and offers a comprehensive compensation and benefits program to attract and retain top talent in the industry. As an international developer of low-cost, low-power programmable design solutions, Lattice is committed to customer success and a culture of innovation and achievement. If you thrive in a results-oriented environment, seek individual success within a team-first organization, and are ready to contribute to a collaborative and innovative atmosphere, Lattice Semiconductor may be the perfect fit for you. Feel the energy at Lattice.,

You should have a strong understanding of CTS, DEM, APTRA application support along with knowledge of PPS concept. Your responsibilities will include providing Techo-Functional L3 support for CTS, DEM, APTRA applications. It is essential to have expertise in Oracle 19c with RAC setup, ability to prewrite and modify complex SQL queries, and proficiency in Unix, Java code, and configuration of Web Browsers such as JBoss, Apache Tomcat, and IIS. Participation in gathering business requirements, preparing BRS and SRS documents, and experience in VA and APPSEC points resolution will be advantageous. Familiarity with CBS (Finacle) is also a plus. The required skills for this role include proficiency in Oracle 19C for understanding and writing complex queries, Unix operating system, Java code (optional), and configuration of Web Browsers like JBoss, Apache Tomcat, and IIS. Experience in resolving VA and APPSEC points is also desired. Certification in RHEL is preferred. Educational qualifications should include B.E., B.Tech., B.C.A., or M.C.A. Project management experience will be beneficial for this role. This is a permanent position with an experienced level requirement. The job was posted on February 13, 2025.,

Excellent communication required. US Customer Service voice process. We are looking to hire candidates from Gurgaon and for Kolkata location Minimum 6 months of experience is required in International voice process. Customer Service Executive Customer Support Executive - Virtual Interview only Blended process (voice Process) 2 days rotational off. US or Night shift Work From Office Good communication required Immediate joining required Pls call Mamta 9176149292 for more info. Thanks, Mamta 9176149292

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications: Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux- Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 3+ years Hardware Engineering experience or related work experience. 3+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Knowledge in Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Good knowledge of Tcl/Perl Scripting Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3- 6yrs years of experience in Physical Design/Implementation Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Responsibilities: STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Work on automation scripts within STA/PD tools for methodology development. Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment Experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS ICC, Innovous , PT/Tempus Familiar with process technology enablementCircuit simulations using Hspice/FineSim, Monte Carlo. Education B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI. Preferred Qualification/Skills Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling Hands-on experience with STA tools - Prime-time, Tempus Have experience in driving timing convergence at Chip-level and Hard-Macro level In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling, Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus) Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation. Proficient is scripting languages- TCL, Perl, Awk Basic knowledge of device physics Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

You should possess in-depth knowledge and hands-on experience in Netlist2GDSII Implementation, including tasks such as Floorplanning, Power Grid Design, Placement, Clock Tree Synthesis (CTS), Routing, Static Timing Analysis (STA), Power Integrity Analysis, Physical Verification, and Chip finishing. It is essential to have experience with Physical Design Methodologies and sub-micron technology, particularly in 16nm and lower technology nodes. Moreover, you should have expertise in Analog and Mixed Signal Design and be familiar with handling designs with more than 5M instance count and operating at a frequency of 1.5GHz. Proficiency in programming languages such as Tcl, Tk, and Perl is required to automate the design process and enhance efficiency. Hands-on experience with PnR Suite from Cadence & Synopsys, specifically Innovus & ICC2, is a must. Additionally, you should have a strong background in Static Timing Analysis using tools like PrimeTime for SI analysis, EM/IR-Drop analysis with PT-PX and Redhawk, as well as Physical Verification using Calibre. Understanding the practical application of methodologies, Physical Design Tools, Flow Automation, and driving improvements in these areas is highly beneficial. Experience in complex SOC integration, Low Power and High-Speed Design, as well as proficiency in Advanced Physical Verification Techniques, are desirable skills for this role.,

Skills requried: • In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on Physical Design Methodologies and sub-micron technology of 16nm and lower technology nodes. - Should have experience in Analog and Mixed Signal Design • Should have experience in handling >5M instance count , 1.5GHz frequency designs . • Should have experience on programming in Tcl/Tk/Perl to automate design process and improve efficiency. • Must have hands-on experience on PnR Suite from Cadence & Synopsys (Innovus & ICC2) • Strong experience on Static Timing Analysis (PrimeTime - SI) , EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification (Calibre). • Understanding the practical application of methodologies and Physical Design Tools, Flow Automation, and Improvements. • Experience in complex SOC integration, Low Power and High-Speed Design and Advanced Physical Verification Techniques.