Wireless IP Design Engineer

As a member of Qualcomm India Private Limited's Wireless IP team, you will be responsible for designing and developing cutting-edge RTL for next-generation cellular and Wi-Fi modem IPs used in mobile, wearable, and IoT platforms. Your role will involve working on high-performance, low-power digital designs throughout the full VLSI development cycle, from architecture and micro-architecture to RTL implementation and SoC integration. By collaborating with global teams, you will have the opportunity to contribute to market-leading wireless solutions. Key Responsibilities: - Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog. - Develop micro-architecture specifications and deliver high-quality, synthesizable RTL. - Integrate complex subsystems into SoC environments and support design convergence. - Collaborate with system architects, verification, SoC, software, DFT, and physical design teams. - Apply low-power design techniques including clock gating, power gating, and multi-voltage domains. - Analyze and optimize for performance, area, and power. - Ensure protocol compliance and performance of interconnects, buses (AXI, AHB, APB), and bridges. - Conduct CDC and lint checks using tools like Spyglass and resolve waivers. - Participate in post-silicon debug and bring-up activities. Qualification Required: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Preferred Skills & Experience: - 2-15 years of experience in digital front-end ASIC/RTL design. - Strong expertise in Verilog/SystemVerilog RTL coding and micro-architecture development. - Familiarity with wireless protocols such as IEEE 802.11 (a/b/g/n/ac/ax/be), LTE, or 5G NR is highly desirable. - Solid understanding of bus protocols (AXI, AHB, APB) and bridge logic. - Experience with wireless modem IPs or similar high-performance digital blocks is a plus. - Familiarity with low-power design methodologies and CDC handling. - Hands-on experience with tools like Spyglass, 0-in, Design Compiler, PrimeTime, and simulation environments. - Exposure to post-silicon debug and SoC integration challenges. - Strong documentation and communication skills. - Self-motivated with a collaborative mindset and ability to work with minimal supervision.,