560 Rtl Design Jobs

Job description About The Role As technology manager and director you would be expected to manage a team of full stack development including logic designers, micro architects, and/or verification engineers engineers responsible for developing PCIe, CXL, UXI, UCIe controllers or similar high complexity IP & subsystem development targeted for Data centers and AI business group & is reused in other Intel BUs including clients and NEX too . Responsibilities includes 1. Overall Program Execution , Stake holder management and deliver high quality first time PRQable IP solutions to demanding products in DC and AI domains including custom Silicon & IP requirements.2. You would be expected to manage team of high performing engineer and oversee end to end IP development including logic RTL design, architecture and microarchitecture and Pre-silicon simulation activities. 3. You would also be required to coordinate with FW , Emulation , SoC and Post Silicon teams. 4. You would also be responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results. 5. Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment. Qualifications Bachelor of Engineering in Electronics engineering with minimum 14-20+ years of experience/Master of Engineering with 12-18+ years of relevant experience in Digital design , UVM based verification methodologies and end to end SoC development cycle. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies'spanning software, processors, storage, I/O, and networking solutions'that fuel cloud, communications, enterprise, and government data centers around the world. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Job description Job Description Responsibilities may be quite diverse of a technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually for the summer or for short periods during breaks from school. Qualifications Masters students in EC/EE preferred, with Digital Design courses in curriculum. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

We are seeking a highly skilled Microarchitect and RTL Design Engineer to design and develop microarchitectures for highly configurable IPs, ensuring optimal performance, power, and area. You will collaborate with software and verification teams on various aspects of the design lifecycle, from defining configuration requirements to debugging and coverage. This role requires extensive hands-on experience in microarchitecture and RTL development, proficiency in Verilog/SystemVerilog, and an in-depth understanding of on-chip interconnects and NoCs. Roles and Responsibilities: Design and develop microarchitectures for a set of highly configurable IPs. Perform microarchitecture and RTL coding , ensuring optimal performance, power, and area. Collaborate with software teams to define configuration requirements, verification collaterals, etc. Work with verification teams on assertions, test plans, debug, coverage, etc. Qualifications and Preferred Skills: 8+ years and current hands-on experience in microarchitecture and RTL development . Proficiency in Verilog, System Verilog . Familiarity with industry-standard EDA tools and methodologies . Experience with large high-speed, pipelined, stateful designs, and low power designs . In-depth understanding of on-chip interconnects and NoCs (Networks-on-Chip) . Experience within Arm ACE/CHI or similar coherency protocols. Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects, and NoCs. Familiarity with RAS designs, QoS in fabrics, PCIe/IO is a plus. Experience with modern programming languages like Python is a plus. Excellent problem-solving skills and attention to detail. Strong communication and collaboration skills. QUALIFICATION: BS, MS in Electrical Engineering, Computer Engineering, or Computer Science.

As a RTL Design Engineer for DDR Memory Controller IP development team at Cadence, your primary responsibility will be to design and support the RTL of the DDR Memory Controller solution. You will be working with the existing RTL, adding new features, and ensuring that all leading DDR memory protocols, including DDR4/LPDDR4, are supported. Your tasks will also involve ensuring customer configurations are clean as part of verification regressions, providing customer support, and ensuring the design meets LINT and CDC design guidelines. To qualify for this position, you should have a BE/B.Tech/ME/M.Tech degree in Electrical/Electronics/VLSI and proven experience as a design and verification engineer, with a significant focus on RTL design and development. Proficiency in RTL Design using Verilog is essential, and familiarity with System Verilog and experience in using/debugging in a UVM based environment are required. AXI3/4 experience is preferred, and prior experience with DDR Memory controller and protocols is highly advantageous. Additionally, having prior experience in RTL design and implementation of complex protocols and working in IP development teams will be beneficial for this role. At Cadence, we are committed to making an impact on the world of technology by hiring and developing leaders and innovators like you. Join us in our mission to solve challenges that others can't and be part of a team that is dedicated to work that matters.,

About Newton School Come be part of a rocket ship thats creating a massive impact in the world of education! On one side you have over a million college graduates every year with barely 5% employability rates and on the other side, there are thousands of companies struggling to find talent. Newton School aims to bridge this massive gap through its personalized learning platform. We are building an online university and solving the deep problem of the employability of graduates.We have a strong core team consisting of alumni from IITs and IIM, having several years of industry experience in companies like Unacademy, Inmobi, Ola, and Microsoft - among others. On this mission, we are backed by some of the most respected investors around the world, - RTP Global, Nexus Venture Partners, and a slew of angel investors including CREDs Kunal Shah, Flipkarts Kalyan Krishnamoorthy, Unacademy and Razorpay founders, Udaans Sujeet Kumar among others. About the Role: We are looking for VLSI engineers with a strong foundation in digital systems and computer architecture to take on an academic teaching role. This full-time position is ideal for engineers with hands-on experience in RTL design, processor components, or SoC architecture who are excited to teach how computers are built from logic gates to microarchitectures. You will lead classroom instruction, mentor student projects, and help shape curriculum at the intersection of digital logic, hardware systems, and architectural design. Key Responsibilities Teach Computer Architecture by drawing from real-world VLSI design experience covering instruction sets, pipelining, memory systems, and microprocessor implementation. Guide students through lab simulations and RTL projects that explore how architectural concepts are implemented in hardware (e.g., datapaths, control units, cache design). Design and evaluate lab work, assessments, and hands-on student projects that simulate industry applications. Mentor and support students in their academic and professional development journeys. Continuously update course content to reflect current industry trends and technologies. Contribute to curriculum development, academic research, and internal learning initiatives. Host technical workshops, design challenges, and guest sessions to extend classroom learning. Collaborate with fellow faculty, industry mentors, and curriculum designers to enrich learning outcomes Must-Have Skills & Qualifications B.Tech / M.Tech / Ph.D. in Computer Engineering, Electronics, Electrical, or a related field. Experience working on processor subsystems, SoC integration, RTL for custom compute blocks, or related architecture-level VLSI work. Strong technical command over topics such as: ? Computer Architecture: Instruction sets, microprocessors, memory hierarchy, pipelining, cache systems. ? VLSI Design: CMOS circuits, RTL design, ASIC/FPGA flow, timing analysis, layout. Proficiency in tools such as Cadence, ModelSim, Synopsys, Xilinx, Mentor Graphics, etc. Working knowledge of HDL languages (Verilog/VHDL) and scripting (Tcl, Shell, Python). Excellent communication and classroom delivery skills. Demonstrated interest in teaching and mentoring students. Good-to-Have Skills: Prior experience as a faculty member or technical trainer. Familiarity with RISC-V, ARM-based processors, SoC Design, or low-power systems Exposure to DFT, verification methodologies, and EDA flows. Contributions to open-source, academic publications, or online technical content. Comfort with digital tools, LMS platforms, and collaborative teaching formats. Show more Show less

You will be responsible for executing small to mid-size customer projects in various fields of VLSI Frontend Backend or Analog design with minimal supervision. As an individual contributor, you will work on tasks related to RTL Design/Module and provide support to junior engineers in Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. Your successful and on-time completion of assigned tasks will contribute to the quality delivery approved by the project lead/manager. Your outcomes will be measured based on the quality of deliverables verified by the Lead/Manager, timely delivery as per relevant metrics, reduction in cycle time and cost through innovative approaches, number of trainings attended, and the number of new projects handled. You are expected to ensure the quality of deliverables by facilitating clean delivery of designs and modules for easy integration at the top level, meeting functional specifications and design guidelines without any deviation, and documenting tasks and work performed. Timely delivery is crucial, meeting project timelines as requested and supporting the team lead in intermediate task delivery. Teamwork plays a significant role, requiring your participation in supporting team members/lead when needed and performing additional tasks in case any team member is unavailable. Embracing innovation and creativity, you should look to automate repeated tasks to save design cycle time, participate in technical discussions, and contribute to training forums. Your skills should include expertise in languages and programming such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, Makefile, and Spice, among others. Proficiency in EDA Tools like Cadence, Synopsys, Mentor tool sets, and technical knowledge in IP Spec Architecture Design, Micro Architecture, Bus Protocols, Physical Design, Circuit Design, Analog Layout, Synthesis, DFT, Floorplan, Clocks, and more is required. Familiarity with CMOS FinFet, FDSOI, technology, strong communication, analytical reasoning, problem-solving skills, and the ability to learn new skills are essential for successful project execution. Your knowledge should span across Frontend/Backend/Analog Design, project experience in RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, Analog Layout, understanding of design flow, methodologies, technical specifications, and the ability to execute assigned tasks effectively based on client/manager requirements. Having a command over digital logic design concepts, experience in large IP block design, knowledge of Synopsys/Cadence/Mentor simulation tools, Perl/TCL scripting, RTL logic synthesis, and basic SOC architecture will be advantageous for this role. Your attention to detail, technical skills, and ability to deliver tasks on time with quality are crucial aspects in contributing to the success of projects at UST.,

As a Senior Design/Verification - Subsystems Lead at Synopsys, you will be part of the Digital IP Subsystem team that has experienced significant growth. We are seeking talented engineers to join us in Bangalore/Hyderabad, India and be a part of our exciting journey in the SysMoore era. **Design Lead:** In the role of an RTL Design lead, you will experience the thrill of achieving bug-free RTL from requirements or specifications. Your expertise in driving the design effort for complex IP/Subsystem/SoC blocks, with a track record of multiple tape-outs, will be invaluable in delivering high-quality results. **Verification Lead:** As a Verification lead, you will enjoy the challenge of identifying and rectifying bugs to ensure the design intent is realized. Your role is critical in ensuring the flawless operation of chips, such as those on space telescopes capturing stunning images of galaxies. Your experience in leading multiple tape-outs and closing verifications of complex IP/Subsystem/SoC blocks will be instrumental in our success. **Design role:** In the position of a Senior RTL Subsystems Designer Lead with over 8 years of experience, you will be responsible for driving the Subsystem life cycle from requirements to final release phases. This includes crafting functional specifications, defining micro-architectures, coding RTL using best practices, conducting RTL quality checks, collaborating with Verification and implementation teams, and overseeing project completion. Proficiency in standard protocols like PCIe, DDR, UFS, USB, AMBA, as well as hands-on experience in low power design and understanding of DFT requirements and architecture are essential. Your ability to work effectively with cross-functional teams will be crucial in delivering successful projects. **Verification role:** In the role of a Senior Verification lead with over 8 years of experience, you will lead the complete Verification cycle by crafting test plans, architecting verification environments, developing test infrastructure, and executing plans to closure with coverage. Proficiency in Functional Verification of standard protocols like PCIe, DDR, UFS, USB, AMBA, as well as power-aware Verification with UPF, is required. Hands-on experience in Gate Level Verification is a valuable addition. Your collaboration with cross-functional teams will be key to driving projects to completion.,

You will be responsible for joining OnSemi's growing team in Bengaluru, India as a Sr. Principal Digital Design Engineer focused on New Product Development in Power Management. Your primary responsibilities will include working on the development of various Power Management products for consumer, industrial, and automotive applications such as DC-DC PMIC/POL, multiphase controllers, drivers, converters, LED drivers, SiC drivers, switches, and efuses. Your key responsibilities will involve collaborating with different product lines for RTL implementation of power convertor controller designs, working on digital design architecture, RTL, low power design, synthesis, and timing analysis. You will also interface with the Physical Design team for the power management chips using state-of-the-art RTL2GDS flows. As part of a large engineering team, you will collaborate effectively with design architects, digital verification, project management, and digital and analog design teams across various global locations. You will be involved in micro-architecture to RTL implementation, supporting system-level bring-up on pre-silicon platforms, and owning the technical outcome of Power Management ICs. Furthermore, you will be responsible for understanding project goals, executing with realistic schedules, reporting progress status, and supporting post-silicon validation activities. You will also lead and support customer issues, production issues, FW and system development, and failure analysis. Onsemi is a company driving disruptive innovations to create a better future, focusing on automotive and industrial end-markets. With a highly differentiated product portfolio, Onsemi aims to solve complex challenges and lead the way in creating a safer, cleaner, and smarter world. To qualify for this role, you should have a BS in Electrical Engineering or related field with 12 years of experience, or an MS with 10 years of experience in Digital Design, Architecture, and ASIC/Mixed signal chip developments. The ideal candidate will possess a thorough understanding of the end-to-end digital design flow, RTL design, CDC, ASIC synthesis, timing analysis, P&R, UPF, system Verilog, Verilog, TCL, and Perl/Python/XML programming languages.,

You will be part of the Intel Core Design Team driving Intel's latest CPUs in the world's leading process technologies. As a Pre-Silicon Verification Engineer, you will develop pre-Silicon functional verification tests to ensure that the system meets design requirements. Your responsibilities will include creating test plans for RTL validation, defining and running system simulation models, and implementing corrective measures for failing RTL tests. You will also analyze results to modify test benches and tests to improve validation plans. As a Pre-Silicon Verification Lead/Architect, you will lead and guide a team to develop complex pre-Silicon verification environments, verification components, and coverage plans. You will drive strategic initiatives related to tools, methodologies, and quality to reduce the overall cycle time of validation projects. Working closely with hardware architects and logic designers, you will influence SoC and system design to ensure product success. Additionally, you will provide technical leadership, manage resources, and drive engineering activities to meet schedules, standards, and cost. To qualify for this role, you must possess a master's degree in Electronics or Computer Engineering with at least 4 years of experience or a Bachelor's Degree with at least 10 years of experience in Pre-Silicon Verification Environment. Preferred qualifications include experience with RTL design, Verilog, System Verilog based verification techniques, CPU architecture/Processor Verification, Perl/Python, Linux OS, SVTB UVM, or Specman (e). You should be a team player with excellent self-motivation, communication, problem-solving, and teamwork skills. The Client Computing Group (CCG) at Intel is responsible for driving business strategy and product development for PC products and platforms. As part of this group, you will contribute to delivering purposeful computing experiences that unlock people's potential. This role is an Experienced Hire position based in India, Bangalore, and eligible for a hybrid work model that allows splitting time between on-site and off-site work.,

You are a highly experienced ASIC RTL Design Architect responsible for leading the design and verification of cutting-edge SoCs and high-speed digital IPs. With over 10 years of experience in ASIC/FPGA design, your expertise lies in RTL using Verilog/SystemVerilog, Lint, CDC, and Spyglass-based design verification methodologies. Your main responsibilities include leading RTL design and micro-architecture for high-performance ASIC SoCs, ensuring compliance with Lint, CDC, and SDC constraints using Spyglass or equivalent tools, driving design optimization and timing closure, as well as collaborating with cross-functional teams such as Design Verification, DFT, Physical Design, and Software teams. You will also be involved in developing and reviewing architecture specifications, coding guidelines, and best practices, as well as performing synthesis, timing analysis, and static verification using tools like STA, LEC, and Formal Verification. Key requirements for this role include a minimum of 10 years of experience in ASIC RTL design and architecture, expertise in Verilog/SystemVerilog for RTL design, strong knowledge of Spyglass Lint/CDC and static verification methodologies, experience in SoC micro-architecture, high-speed interfaces, and power optimization. Additionally, you should have a solid understanding of synthesis, STA, timing closure, backend constraints, experience with EDA tools like Synopsys, Cadence, Mentor Graphics, and familiarity with UVM-based verification and scripting languages such as TCL, Python, or Perl. Preferred qualifications include an M.Tech/MS/PhD in Electrical Engineering, Computer Engineering, or related field, experience in chip tape-out and production silicon, and an understanding of hardware security, reliability, and safety standards. If you are looking to be part of a team that is shaping the future of high-performance computing, apply now and join us in building innovative solutions together.,

You should have a strong understanding of design power intent at the RTL level and UPF. You should be able to translate power intent into UPF after consulting with the RTL designers. Your responsibilities will include running, debugging, and resolving Static Power Check (VCLP) related issues independently before RTL is handed off to PD. Your tasks will involve UPF generation (yaml creation, running upfgen to create the UPF) and UPF maintenance. As RTL changes, UPF may need adjustments and re-verification. You should also be proficient in running VCLP and integrating it with the top level as well as with the P&R flows. We are looking for a UPF expert with a strong background in low power design. We require UPF expertise as a primary skill, not as a secondary one. It is acceptable to have one back end and one front end with PNR, guided by one consultant. The responsibilities include RTL UPF coding, LP validation, level shifter strategy, and potentially handling UPF within the PNR flows. If the candidate is not familiar with PNR flows, we can fill that gap with a back end UPF person.,

Eridu AI India Private Limited, a wholly owned subsidiary of Eridu Corporation, Saratoga, California, USA, is seeking highly motivated and talented professionals for its R&D center in Bengaluru. Eridu AI is a Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. The company introduces innovative solutions across semiconductors, software, and systems to enhance AI data center performance, increase GPU utilization, and reduce capex and power consumption. Led by a team of experienced Silicon Valley executives and engineers, Eridu AI's solution has been widely recognized by hyperscalers. We are currently looking for an RTL Design Director to lead our Networking IC team in Bengaluru. As a part of the Design Group, you will play a crucial role in defining, specifying, architecting, executing, and productizing cutting-edge Networking devices. This position offers a unique opportunity to shape the future of AI Networking and work on real-world problems. Responsibilities: - Lead the offshore RTL team and provide technical guidance. - Collaborate with Chip and System Architects to translate architecture requirements into microarchitecture and design implementation. - Conduct RTL coding, code reviews, and debugging. - Document microarchitecture and RTL subsystems. - Define development flows to enhance efficiency and quality. - Coordinate with other teams for successful RTL implementation. - Utilize domain experience in Ethernet, PCIe, and protocols for informed design decisions. Qualifications: - MS/BS degree with a minimum of 15+ years of experience. - Demonstrated success in tape-outs and productization, preferably in networking devices. - Ability to translate architecture-level descriptions into implementable designs with clear documentation. - Proficiency in addressing clock/reset/power domain challenges and safe design practices. - Experience in optimizing hardware for product performance. - Strong knowledge of industry tools and best practices for RTL development. - Understanding of networking protocols and ASIC design flow. - Familiarity with DFT and physical implementation requirements. Join us at Eridu AI to be a part of a world-class team working on groundbreaking technology that shapes the future of AI infrastructure. Your work will directly contribute to transforming data center capabilities and developing next-generation AI networking solutions. The starting base salary will be determined based on relevant skills, experience, qualifications, and market trends. For more information, visit our website at eridu.ai.,

This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; - Grade Specific Focus on Electrical, Electronics and Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers.

Challenging and Interesting work on building and enhancing Indias only completely open-source RISC-V based SHAKTI processors. Learn everything about the entire flow from spec to silicon. Work on state-of-the-art research topics and engineering efforts. Exposure to engage with foreign universities and support in preparation to pursue higher studies in India/Abroad. Exposure to engage with leading industry partners thereby improving your career trajectory and exposure. International Publications can also be achieved as part of tenure, boosting your research potential for higher studies. Required Skill Set Must have basic expertise in at least one of: verilog, vhdl, bluespec system verilog and/or chisel. Must have knowledge: digital design, pipelining Basic computer architecture knowledge, include one or more of : in-order cores, out-of-order cores, processors, caches, SoC development, memory architecture, etc. Good to have experience with FPGAs , performance modelling, workload analysis/benchmarking, python scripting, knowledge of peripheral and communication IPs

Job Titles: Senior Staff ASIC RTL Design Engineer Bangalore location We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a passionate and highly skilled digital design engineer with a strong background in ASIC RTL design You thrive on technical challenges, enjoy collaborating with global teams, and are motivated by seeing your designs come to life in real-world products With over8 years of hands-on experience in architecting, implementing, and verifying complex digital systems, you are adept at translating functional specifications into efficient, robust RTL Your experience spans data path and control path designs, and you are comfortable working with industry-standard protocols such as Ethernet, DDR, PCIe, USB, and AMBA You possess deep expertise in synthesizable Verilog/SystemVerilog, design flows, and EDA tools You are equally at home mentoring junior engineers as you are diving deep into code or debugging complex issues Your ability to balance area, latency, and throughput trade-offs sets you apart, and your attention to detail ensures high-quality, reliable IP cores You communicate effectively with both technical and non-technical stakeholders and are comfortable engaging with customers to clarify requirements and ensure successful delivery You value diversity, inclusion, and continuous learning, and you bring a collaborative spirit to every project If youre ready to lead, innovate, and make a tangible impact in the world of high-performance silicon design, Synopsys is the place for you, What Youll Be Doing: Architecting, designing, and implementing state-of-the-art RTL for high-performance synthesizable IP cores within the DesignWare family, Translating complex functional and standard specifications into detailed architecture and micro-architecture documents for medium to high complexity blocks, Owning the entire digital design lifecycle, including RTL coding, synthesis, CDC analysis, debugging, and test development, Collaborating with global, multi-site teams of expert engineers to drive technical excellence and innovation, Interacting with customers to understand and refine specification requirements and providing technical guidance as needed, Mentoring and technically leading junior designers, fostering growth and sharing best practices within the team, Participating in design reviews, quality process improvements, and ensuring adherence to industry-leading verification and design methodologies, The Impact You Will Have: Delivering robust, high-quality IP cores that power next-generation commercial, enterprise, and automotive applications worldwide, Driving innovation in digital ASIC design, enabling faster, more efficient, and reliable silicon solutions for Synopsys customers, Contributing to the advancement of industry standards and protocols through technical leadership and deep domain expertise, Enhancing team performance through mentorship, knowledge sharing, and technical guidance, Strengthening Synopsysreputation as a leader in chip design by consistently delivering on complex customer requirements, Accelerating product development cycles by streamlining design processes and championing best-in-class methodologies, What Youll Need: Bachelors or Masters degree in EE, EC, or VLSI with8+ years of relevant industry experience in digital ASIC RTL design, Expertise in data path and algorithmic block design ( e-g , Reed Solomon FEC, BCH codes, MAC SEC engines) and architecture trade-offs, Proficiency in synthesizable Verilog/SystemVerilog RTL coding, simulation, and EDA tools, Hands-on experience with design flows including Lint, CDC, synthesis, static timing analysis, and formal checking, Strong knowledge of industry-standard protocols (Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA AXI/AMBA2), Experience with high-speed design (>600MHz), P&R aware synthesis, and tools like Fusion Compiler is a significant plus, Familiarity with revision control systems ( e-g , Perforce) and scripting languages (Perl/Shell), Prior experience as a technical lead or mentor within a design team is highly desirable, Who You Are: A collaborative team player who thrives in a global, distributed environment, An effective communicator, adept at conveying complex technical ideas to diverse stakeholders, A proactive problem-solver with strong analytical skills and high initiative, Detail-oriented, quality-focused, and committed to delivering excellence, Passionate about mentoring and enabling the growth of others, Dedicated to diversity, inclusion, and fostering an open, respectful workplace, The Team Youll Be A Part Of: Youll be an integral member of the DesignWare IP Design R&D team at Synopsys Bangalore, collaborating with some of the brightest minds in the industry The team is focused on developing cutting-edge synthesizable IP cores that are deployed in a wide range of commercial, enterprise, and automotive applications Working in a multi-site, global environment, youll have opportunities to engage with cross-functional teams, contribute to technical excellence, and drive innovation in digital design, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process, Show

Cradlepoint is establishing a new Silicon R&D center in Bangalore, and we are looking for a Senior Designer - ASIC IP to join our pioneering team. You will be instrumental in developing the IPs that power the digital ASICs for tomorrow's mobile standards, contributing directly to the advancement of 5G and 6G technologies. This role offers the opportunity to work with cutting-edge tools and methodologies within a collaborative and innovative global R&D environment. What We Offer: Creative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. You'll have the opportunity to explore advanced design technologies alongside skilled experts. Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. What You Will Do: Key Responsibilities Develop ASIC IP blocks and subsystems , contributing to the advancement of 5G and 6G communication technology. Take full ownership of a design , whether at the block or subsystem level. Generate comprehensive documentation throughout the design lifecycle. Perform digital design and conduct all RTL sign-off checks . Continuously enhance and optimize design methodologies and processes . Collaborate with IP Architects to break down requirements and create detailed IP architecture and design specifications. Work closely with verification engineers to review and refine verification plans. Build competence in the technical domain. Engage in cross-team collaboration to ensure successful project delivery. Required Qualifications: Education: Bachelor's degree in electrical or computer engineering. Industry Experience: Proven industry experience in ASIC design. Strong Experience in/with: Understanding of ASIC technology, design environments, and methodologies . SystemVerilog . RTL static sign-off tools such as SpyGlass. Scripting languages like TCL, Python, or similar. SystemVerilog Assertions . The Skills You Bring: Additional Requirements Experience with Cadence and Synopsys front-end and middle-end design suites . Team-oriented , prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality . Strong focus on meeting project deadlines and deliverables . Proficient in English , with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Expertise in low-power design , including specifying power intent using UPF or similar standards. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), and issue-tracking (e.g., Jira). Experience designing one or more of the following hardware domains: AMBA-based designs especially AXI and CHI. ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols . Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.).

At Cadence, we are dedicated to hiring and nurturing leaders and innovators who are eager to leave a mark on the technology industry. With over 30 years of expertise in computational software, Cadence stands as a pivotal figure in electronic design. Our Intelligent System Design approach helps us provide software, hardware, and IP solutions that bring design ideas to life. Our clientele comprises the most groundbreaking companies globally, creating exceptional electronic products across various sectors such as consumer electronics, hyperscale computing, 5G communications, automotive, aerospace, industrial, and healthcare. The Cadence work environment offers a multitude of benefits: - A chance to engage with cutting-edge technology and a culture that fosters creativity, innovation, and impact-making. - Employee-centric policies that prioritize physical and mental well-being, career growth, learning opportunities, and acknowledging achievements based on individual needs. - The "One Cadence One Team" ethos that encourages collaboration within and among teams to ensure customer satisfaction. - A range of learning and development avenues tailored to cater to employees" specific interests and requirements. - Collaborating with a diverse team of enthusiastic, committed, and skilled individuals who consistently go the extra mile for customers, communities, and each other. Job Summary: We seek a professional with over 14 years of experience possessing the following skill set: - Proficiency in RTL design basics utilizing HDLs like VHDL/Verilog/System Verilog. - Comprehensive understanding of AMD (Xilinx) Ultrascale, Versal FPGAs architecture, and experience with Vivado for FPGA place and route. - Competence in defining constraints for FPGAs and conducting Static Timing Analysis. - Familiarity with FPGA prototyping or emulation is advantageous. - Eagerness to learn and explore new technologies, showcasing strong analytical and problem-solving abilities. - Effective written and verbal communication skills, a quick learner, and a team-oriented individual. At Cadence, we are committed to impactful work. Join us in unraveling challenges that others find insurmountable.,

Qualcomm India Private Limited is seeking a Hardware Engineer with expertise in complex high-performance RTL design, particularly on DSP or processor based sub-systems. You should be proficient in hardware design using Verilog, System Verilog, or VHDL and have knowledge of on-chip bus interface protocols like AXI, APB, and AHB. Experience in model development (SystemC, or C++), RTL to gates synthesis (Synopsys DCG or Cadence Genus), design rule and CDC checking (SVA assertions, Spyglass, 0-in), and working on high-performance low power RTL design is essential. Familiarity with scripting languages such as PERL, Python, TCL, C, etc., is also required. As a Hardware Engineer at Qualcomm, your responsibilities will include developing micro-architecture, designing and documenting specific ASIC modules, and sub-systems. You will own the RTL, ensuring its development, assessment, and refinement to meet power, performance, area, and timing goals. Troubleshooting architecture, design, or verification issues using sound ASIC engineering practices, and leveraging various design tools to enhance design quality will be part of your role. Additionally, you will collaborate with the design verification team to execute the functional verification strategy and contribute innovative ideas for IP core and process flow enhancements. The ideal candidate should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field with at least 2 years of Hardware Engineering experience. Alternatively, a Master's degree with 1+ years of relevant experience or a PhD in a related field will also be considered. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. Reasonable accommodations can be requested by emailing disability-accommodations@qualcomm.com or calling Qualcomm's toll-free number. The company expects all employees to adhere to applicable policies and procedures, including those related to security and protection of confidential information. Please note that Qualcomm's Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies are not authorized to use the site for submissions. Unsolicited resumes or applications from agencies will not be accepted. For further information about this role, reach out to Qualcomm Careers directly.,

Qualcomm India Private Limited is looking for a Hardware Engineer to join their Engineering Group. As a Qualcomm Hardware Engineer, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems. Your responsibilities will include working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge, world-class products. Collaboration with cross-functional teams will be essential to meet performance requirements and develop innovative solutions. To be considered for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 3 years of Hardware Engineering experience. Alternatively, a Master's degree with 2+ years of experience or a PhD with 1+ year of experience will also be considered. You should have 2-6 years of experience in Synthesis, Constraints, and interface timing Challenges, along with a strong domain knowledge in RTL Design, implementation, and Timing analysis. Experience with RTL coding using Verilog/VHDL/System Verilog, micro-architecture & designing cores and ASICs, and familiarity with Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc., will be highly beneficial. Exposure in scripting languages such as Pearl/Python/TCL and strong debugging capabilities are also required for this role. As a Qualcomm Hardware Engineer, you will collaborate closely with cross-functional teams to research, design, and implement performance, constraints, and power management strategies for the product roadmap. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. If you require an accommodation during the application/hiring process, you can reach out to disability-accommodations@qualcomm.com. The company expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. If you are a proactive team player with the ability to independently debug and solve issues, and meet the qualifications mentioned above, we encourage you to apply for this exciting opportunity at Qualcomm India Private Limited.,

As a Silicon Design Engineer at AMD, you will collaborate with formal experts and designers to verify formal properties and ensure convergence in the projects you work on. Your role will involve driving formal verification for the block, writing formal properties and assertions to verify the design, coordinating with RTL engineers to implement logic design for improved clock gating, and verifying various aspects of the design. Additionally, you will be responsible for writing tests, sequences, and testbench components in SystemVerilog and UVM, along with formal methods, to achieve thorough verification of the design. You will also play a crucial role in monitoring verification quality metrics such as pass rates, code coverage, and functional coverage. The ideal candidate for this position is someone with a strong passion for modern, complex processor architecture, digital design, and verification. You should possess excellent communication skills, be a team player, and have a knack for analytical thinking and problem-solving. A willingness to learn and tackle challenges head-on is essential for success in this role. To excel in this role, you should have project-level experience with design concepts and RTL implementation, familiarity with formal tools and functional verification tools such as VCS, Cadence, and Mentor Graphics, and a solid understanding of computer organization and architecture. A Bachelor's or Master's degree in computer engineering or Electrical Engineering is required to be considered for this position. At AMD, we are committed to transforming lives with our cutting-edge technology and innovative products. Join us in our mission to build products that enhance next-generation computing experiences across various industries. If you are passionate about pushing the limits of innovation and solving complex challenges, while embodying our core values of directness, humility, collaboration, and inclusivity, we invite you to be a part of our team and together, we advance.,

You are a highly experienced RTL Design Engineer with 12-20 years of experience, specializing in PCIe IP development. Based in Noida/Bangalore, you will be responsible for designing and supporting the RTL of Cadence's PCIe IP solution. Your role will involve working with existing RTL, adding new features, ensuring customer configurations are clean, supporting customers, and ensuring design compliance with LINT and CDC guidelines. To qualify for this position, you must hold a BE/BTech/ME/MTech degree in Electrical/Electronics/VLSI and have extensive experience as a design and verification engineer, with a focus on RTL design using Verilog. Additionally, you should have experience with System Verilog, UVM-based environments, AXI3/4/5, and preferably PCIe. Previous experience in RTL design of complex protocols and IP development teams is highly advantageous. As a member of the Cadence High-Speed SerDes PHY IP Front end Design team, you will be responsible for defining microarchitecture, leading ASIC design, collaborating with cross-functional teams, mentoring junior members, and fostering a high-performance team culture. Requirements for this role include a Bachelor's degree in Electronics Engineering with at least 7 years of experience, a Master's degree with 5 years, or a Ph.D. with 2 years in Digital Design. You should have hands-on experience in micro-architecting digital blocks, RTL implementation in Verilog/SV, SDC definition, STA, Lint Checks, CDC, and Synthesis. Knowledge of protocols such as Ethernet, USB, PCIe, MIPI(DPHY), and HDMI/Display is desired, along with the ability to work closely with Analog design teams and develop high-speed critical digital circuits and signal processing blocks.,

About the Company: QpiAI is a world leader in Quantum and AI technologies, dedicated to building the most powerful Quantum computers in India. Job Description: As a Quantum Error Correction Research Lead at QpiAI, you will be spearheading research on Quantum error correction specifically tailored for QpiAI Qubits. This role requires you to engage in groundbreaking research in Quantum Error corrections, contributing to the advancement of Quantum computing technology. Job Requirements: - The ideal candidate should hold a PhD or Postdoc in Quantum error correction and Quantum theory. - Demonstrated track record of multiple publications on Quantum Error Correction (QEC). - Proficient in Surface codes and Quantum LDPC with a strong working knowledge. - Ability to collaborate effectively with the Quantum hardware team to implement Quantum error correction codes on FPGA. - Familiarity with various types of error correctable qubits. - Proficiency in providing simulation models of errors and error correction codes using Quantum modeling. - Collaborate with RTL design engineers to implement QEC decoders on FPGA. - Develop a roadmap for Fault-tolerant error-corrected Quantum computers in collaboration with peer Principal scientists. Join QpiAI in pushing the boundaries of Quantum computing through innovative Quantum error correction research and make a significant impact on the future of technology.,

The Opportunity We&aposre looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrows future by accelerating the critical data communication at the heart of our digital world from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. Alphawave Semi is expanding its team in PCIe IP design and development! We are looking for talented RTL Design Engineers to contribute to enhance and develop our IP. This is an incredible opportunity to be part of the PCIe and CXL development cycle, from specification to design. As an RTL Design Engineer, you will work in IP design and integration. You will be responsible for microarchitecture, RTL coding, create microarchitecture documents, Lint and Synthesis cycle and Timing closure. You will work with verification team on achieving test plan, the code & functional coverage. What You&aposll Do Deliver standards-compliant PCIe IP block. Will work on Micro-architect and document the design. Develop RTL design using Verilog and/or System Verilog. Work closely with the verification team in reviewing test suite/plans. Issue and track bug reports from launch to closure. Will refine IP development process with advancing tools/scripting. Work with our external customers or internal engineers to deliver designs for use. Collaborate with the team. You will be reporting to Principal Engineer of the Design team. What You&aposll Need B.E/M.Tech with 8+ years of experience in IP, ASIC or FPGA development. Knowledge and experience in any serial protocols and AMBA (AHB, AXI and CXS) protocol. Experience working on PCIe/CXL protocol is advantageous. Solid experience with Verilog, and System Verilog. Experience with FPGA development cycle is desirable. Experience with Lint, CDC, Synthesis, Timing closure, FPGA validation, Power analysis and LEC tools. Experience in ASIC tape-outs is a plus. Good experience with debugging tools and solid debugging skills. Experience with Unix/Linux Shell scripting and/or Perl, TCL, Python and C/C++ programming. Strong communication skills. "We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process. Show more Show less

Job Summary: Seeking an experienced FPGA developer to join our team and work on the design and development of complex FPGA-based systems. The ideal candidate will have a strong background in FPGA design, verification, and implementation, as well as experience working with hardware and software engineers to integrate FPGA designs into larger systems.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. About The Role As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Additional About The Role Additional About The Role Job Role * Work with multiple SOC Design teams to rollout robust Logic Synthesis, UPF synthesis, QoR optimization and netlist Signoff flows* Provide implementation flows support and issue debugging services to SOC design teams across various site* Develop and maintain 3rd party tool integration and product enhancement routines * Should lead implementation flow development effort independently by working closely with design team and EDA vendors * Should drive new tool evaluation, methodology refinement for PPA optimization Skill Set * Proficiency in Python/Tcl * Familiar with Synthesis tools (Fusion Compiler/Genus), * Fair knowledge in LEC, LP signoff tools* Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking* Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus* Should be sincere, dedicated and willing to take up new challenges Experience 13+ years of experience in RTL,UPF & Physical aware Synthesis for cutting edge technology nodes, logic equivalence checking, Scripting and Netlist Timing Signoff Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.