776 Asic Jobs

You are in search of an experienced senior verification engineer with over 10 years of expertise in ASIC/SOC/IP/block level functional verification utilizing system verilog/UVM. The perfect candidate for this role should possess a comprehensive understanding of UVM, advanced UVM, and system verilog. Your main responsibilities will include developing a detailed test plan, constructing a complete test-bench, and creating a robust verification environment that comprises interface agents and scoreboard in UVM. Additionally, you should have in-depth knowledge of at least one industry-standard protocol such as Ethernet, PCIe, DDR, USB. Strong debugging skills are essential to promptly address test-bench issues and failures. As part of this role, you will be accountable for verification closure by focusing on coverage and managing bug reports. Proficiency in utilizing industry-standard verification tools like Questa, VCS, or ModelSim is required. Experience with scripting languages like python, perl, or TCL for automation tasks is also beneficial. Furthermore, you will be responsible for managing a team of 6 to 7 Engineers and engaging with customers to provide task updates. Experience in collaborating with Japanese customers is a prerequisite for this position. Proficiency in the Japanese language is a mandatory skill. If you meet these qualifications and are enthusiastic about taking on these responsibilities, we encourage you to apply for this challenging and rewarding role.,

About Newton School Come be part of a rocket ship thats creating a massive impact in the world of education! On one side you have over a million college graduates every year with barely 5% employability rates and on the other side, there are thousands of companies struggling to find talent. Newton School aims to bridge this massive gap through its personalized learning platform. We are building an online university and solving the deep problem of the employability of graduates.We have a strong core team consisting of alumni from IITs and IIM, having several years of industry experience in companies like Unacademy, Inmobi, Ola, and Microsoft - among others. On this mission, we are backed by some of the most respected investors around the world, - RTP Global, Nexus Venture Partners, and a slew of angel investors including CREDs Kunal Shah, Flipkarts Kalyan Krishnamoorthy, Unacademy and Razorpay founders, Udaans Sujeet Kumar among others. About the Role: We are looking for VLSI engineers with a strong foundation in digital systems and computer architecture to take on an academic teaching role. This full-time position is ideal for engineers with hands-on experience in RTL design, processor components, or SoC architecture who are excited to teach how computers are built from logic gates to microarchitectures. You will lead classroom instruction, mentor student projects, and help shape curriculum at the intersection of digital logic, hardware systems, and architectural design. Key Responsibilities Teach Computer Architecture by drawing from real-world VLSI design experience covering instruction sets, pipelining, memory systems, and microprocessor implementation. Guide students through lab simulations and RTL projects that explore how architectural concepts are implemented in hardware (e.g., datapaths, control units, cache design). Design and evaluate lab work, assessments, and hands-on student projects that simulate industry applications. Mentor and support students in their academic and professional development journeys. Continuously update course content to reflect current industry trends and technologies. Contribute to curriculum development, academic research, and internal learning initiatives. Host technical workshops, design challenges, and guest sessions to extend classroom learning. Collaborate with fellow faculty, industry mentors, and curriculum designers to enrich learning outcomes Must-Have Skills & Qualifications B.Tech / M.Tech / Ph.D. in Computer Engineering, Electronics, Electrical, or a related field. Experience working on processor subsystems, SoC integration, RTL for custom compute blocks, or related architecture-level VLSI work. Strong technical command over topics such as: ? Computer Architecture: Instruction sets, microprocessors, memory hierarchy, pipelining, cache systems. ? VLSI Design: CMOS circuits, RTL design, ASIC/FPGA flow, timing analysis, layout. Proficiency in tools such as Cadence, ModelSim, Synopsys, Xilinx, Mentor Graphics, etc. Working knowledge of HDL languages (Verilog/VHDL) and scripting (Tcl, Shell, Python). Excellent communication and classroom delivery skills. Demonstrated interest in teaching and mentoring students. Good-to-Have Skills: Prior experience as a faculty member or technical trainer. Familiarity with RISC-V, ARM-based processors, SoC Design, or low-power systems Exposure to DFT, verification methodologies, and EDA flows. Contributions to open-source, academic publications, or online technical content. Comfort with digital tools, LMS platforms, and collaborative teaching formats. Show more Show less

NVIDIA is at the forefront of innovation, continually reinventing itself to tackle the challenges of the modern world. The invention of the GPU by NVIDIA has not only driven the growth of the PC gaming market but has also redefined computer graphics and revolutionized parallel computing. In today's era of booming artificial intelligence research, there is a crucial need for highly scalable and massively parallel computation power, an area where NVIDIA GPUs excel. At NVIDIA, we are committed to amplifying human creativity and intelligence through our constant evolution and adaptation to new opportunities that are uniquely challenging and impactful. As part of our team, you will be immersed in a diverse and supportive environment that encourages everyone to strive for excellence and make a significant impact on the world. Currently, we are seeking motivated and innovative ASIC / Hardware Engineers to join us in architecting, designing, and verifying the next generation of GPUs, CPUs, and SoCs. These cutting-edge technologies are aimed at accelerating the performance of various applications such as Data Center, Machine Learning, Autonomous Driving, Ray Tracing, and more. As a part of our hardware engineering groups, you will work on high-performance GPU/SOC/CPU projects involving Memory subsystems, Graphic Processing Units, NOC-based Interconnect Fabric, High-speed IOs, and more. Your responsibilities will include: - Working on hardware models at different levels of abstraction to identify performance bottlenecks. - Collaborating with architecture and design teams to analyze architecture trade-offs related to performance, area, and power consumption. - Developing and testing workloads and test suites targeting different applications running on our products. - Making architectural trade-offs based on various requirements and driving the verification and validation processes. - Creating verification environments using UVM methodology and driving functional coverage verification closure. - Enhancing timing analysis workflows and assisting in chip-level integration and floor planning. - Designing state-of-the-art test access mechanisms and DFT methodologies for our products. - Collaborating with cross-functional teams to drive innovation and improve DFT methods. To be successful in this role, you should have: - A BTech/MTech degree with at least 2 years of experience in micro-architecture and RTL development. - Strong digital design fundamentals and familiarity with ASIC design flows. - Experience in GPU/CPU/SOC performance verification and analysis, IP/SOC design, micro-architecture, and other relevant skills. - Excellent debugging, analytical, and interpersonal skills, along with the ability to work effectively in a team. If you are passionate about technology and seeking a challenging yet rewarding opportunity, NVIDIA offers competitive salaries, comprehensive benefits, and a stimulating work environment with some of the brightest minds in the industry. Join us in our mission to shape the future of technology and make a meaningful contribution to the world.,

You will be joining a dynamic team at Micron Technology, a world leader in memory and storage solutions, as a System Architect, Hardware Engineer, or Applications Engineer. In this role, you will collaborate with System Level Architects to design and define block diagrams, schematics, and electrical requirements for cutting-edge memory packaging projects. Your deep understanding of hardware design, package design, and system architecture will be crucial as you work closely with cross-functional teams. Key Responsibilities: - Collaborate with System Level Architects to design and define block diagrams, schematics, and electrical requirements. - Develop and implement hardware solutions that meet package specifications and requirements. - Conduct detailed analysis and verification of system-in-package interfaces for correct performance and reliability. - Work closely with firmware & product engineers for seamless integration of system-in-package product solutions. - Provide technical guidance and support to junior engineers and team members. - Stay updated on industry trends and hardware technology advancements to ensure competitive and innovative solutions. - Prepare and present technical documentation and reports to stakeholders. Qualifications: - Master's degree in Electrical Engineering, Computer Engineering, or related field with 8-10 years of experience, or a PhD with 6-8 years of experience. - Proven experience in hardware design and development, including block diagrams, schematics, and electrical requirements. - Strong understanding of system architecture and collaboration with System Level Architects. - Experience with ASIC and processor architectures applicable to mNAND and SSD ASICs. - Proficiency in hardware design tools and software. - Excellent problem-solving skills and attention to detail. - Strong communication and interpersonal skills. - Ability to work effectively in a fast-paced and dynamic environment. - Familiarity with NAND flash memory technology and SSD controller design. - Proficiency in EDA schematic and simulation tools. - Experience with logic verification tools. Preferred Skills: - Experience with advanced hardware technologies and methodologies. - Knowledge of industry standards and best practices in hardware design. - Familiarity with software development and integration. Benefits: - Competitive salary and benefits package. - Opportunity to work on innovative and challenging projects. - Collaborative and supportive work environment. - Professional development and growth opportunities. Micron Technology, Inc. is dedicated to transforming how the world uses information, enriching life for all through innovative memory and storage solutions. Micron delivers high-performance DRAM, NAND, and NOR memory and storage products, driving advances in artificial intelligence and 5G applications. Visit micron.com/careers for more information. For assistance with the application process or reasonable accommodations, contact hrsupport_india@micron.com. Micron strictly prohibits the use of child labor and complies with all labor standards and regulations.,

You are a highly experienced ASIC RTL Design Architect responsible for leading the design and verification of cutting-edge SoCs and high-speed digital IPs. With over 10 years of experience in ASIC/FPGA design, your expertise lies in RTL using Verilog/SystemVerilog, Lint, CDC, and Spyglass-based design verification methodologies. Your main responsibilities include leading RTL design and micro-architecture for high-performance ASIC SoCs, ensuring compliance with Lint, CDC, and SDC constraints using Spyglass or equivalent tools, driving design optimization and timing closure, as well as collaborating with cross-functional teams such as Design Verification, DFT, Physical Design, and Software teams. You will also be involved in developing and reviewing architecture specifications, coding guidelines, and best practices, as well as performing synthesis, timing analysis, and static verification using tools like STA, LEC, and Formal Verification. Key requirements for this role include a minimum of 10 years of experience in ASIC RTL design and architecture, expertise in Verilog/SystemVerilog for RTL design, strong knowledge of Spyglass Lint/CDC and static verification methodologies, experience in SoC micro-architecture, high-speed interfaces, and power optimization. Additionally, you should have a solid understanding of synthesis, STA, timing closure, backend constraints, experience with EDA tools like Synopsys, Cadence, Mentor Graphics, and familiarity with UVM-based verification and scripting languages such as TCL, Python, or Perl. Preferred qualifications include an M.Tech/MS/PhD in Electrical Engineering, Computer Engineering, or related field, experience in chip tape-out and production silicon, and an understanding of hardware security, reliability, and safety standards. If you are looking to be part of a team that is shaping the future of high-performance computing, apply now and join us in building innovative solutions together.,

HCL Technologies is a next-generation global technology company that helps enterprises reimagine their businesses for the digital age. With a strong foundation built on four decades of innovation, a world-renowned management philosophy, and a relentless focus on customer relationships, we pride ourselves on our culture of invention and risk-taking. HCL is committed to diversity, social responsibility, sustainability, and education initiatives, exemplified by our worldwide network of R&D facilities and co-innovation labs. With over 187,000+ Ideapreneurs across 50 countries, we deliver holistic services across industry verticals to leading enterprises, including 250 of the Fortune 500 and 650 of the Global 2000. Enterprises today are at a critical juncture where digital technologies such as analytics, cloud, IoT, and automation are key to success. To help enterprises leverage these technologies for their business objectives, HCL offers an integrated portfolio of products and services through three business units: IT and Business Services (ITBS), Engineering and R&D Services (ERS), and Products and Platforms (P&P). As a Technology Manager at HCL Technologies in Ha Noi or Ho Chi Minh (Vietnam), your responsibilities will include managing technology in projects, providing technical guidance or solutions, developing and guiding team members to enhance their technical capabilities, preparing status reports to minimize exposure and risks on projects, ensuring process compliance, and participating in technical discussions or reviews. **Responsibilities:** - Manage technology in projects and provide technical guidance or solutions - Develop and guide team members to enhance their technical capabilities - Prepare and submit status reports to minimize exposure and risks on projects - Ensure process compliance in the assigned module and participate in technical discussions or reviews **Requirements:** - 5+ years of experience - Bachelors/Masters degree in Electronics/Electrical Engineering with 5+ years of experience in verification - Good understanding of ASIC/SoC life cycle - Experience in OVM/UVM methodologies using SV - Experience with Full chip test plan development/modification - Experience with Testbench development/modification, Test case development, coding, execution, bug analysis, Regressions, coverage analysis, Verification closure - Experience in prevalent standards & Protocols viz. PCIe Gen3/4/5/USB3/DDR4/5, /Ethernet/CSI2/I3C/AMBA - Experience with Gate level simulations - Experience in scripting - Participation in multiple ASIC/SoC verifications till tape out stage - Good command of English. Opportunity to work onsite in Japan **Benefits:** - 18 paid leaves per year (including 12 annual leaves + 6 personal leaves) - Insurance plan based on full salary + 13th salary + Performance Bonus - 100% full salary in probation period - Medical Benefit for Employee and Family - Fast-paced, flexible, and multinational working environment - Opportunity to travel onsite (in 49 countries) - Internal Training (Technical & Functional). Scope of English Training - Working hours: 8:30 AM-6:00 PM, Mondays to Fridays,

About Us: Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, and spec to the product. With 3200+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. Tessolve s design services include solutions on advanced process nodes with a healthy eco-system relationship with EDA, IP, and foundries. Our front-end design strengths integrated with the knowledge from the backend flow, allows Tessolve to catch design flaws ahead in the cycle, thus reducing expensive re-design costs, and risks. We actively invest in the R&D center of excellence initiatives such as 5G, mmWave, Silicon photonics, HSIO, HBM/HPI, system-level test, and others. Tessolve also offers end-to-end product design services in the embedded domain from concept to manufacturing under an ODM model with application expertise in Avionics, Automotive, Industrial and Medical segments. Tessolve s Embedded Engineering services enable customers a faster time-to-market through deep domain expertise, innovative ideas, diverse embedded hardware & software services, and built-in infrastructure with world-class lab facilities. Tessolve s clientele includes Tier 1 clients across multiple market segments, 9 of the top 10 semiconductor companies, start-ups, and government entities. We have a global presence over 12 countries with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose. Job Location : Pune What youll do Role involves validation & coordinatingQA activities for the WiFi testing. Develop, review and modify test plans based on new feature requirement. Writingand developing testing procedures. Failure debugging and interaction withdevelopment team for logical conclusion of the issues. Test results analysis, report preparation and documentation showing correctiveactions for the issues. Work with different teams (development, SAE etc) toanalyse and debug field issues. Understanding of design docs and specificationsfor new feature development. Have scripting knowledge to automate the newfeatures. Work on customer use case execution and collecting data for customerevaluation during design win process. Who you are BE/B.Tech/ ME/ M.Tech - Wireless Communication, Electronics &Communication, Computer Science Experience 03-5 yrs Good knowledge of Wi-Fi protocols and standards like 802.11a/b/g/n/ac/ax/e/w Good working knowledge on WLAN security like WPA2/WPA3. Enterprise securitywith different EAP types Good working knowledge on analysis tools like Omnipeek, Wireshark. Traffictools like iperf and chariot. Tools and utilities like supplicant, hostapd,RADIUS Servers Good debugging skills and hands on with tools like TCPdump, logcat etc Good working experience with different operating systems like Linux, RTOS,Windows and Android. Experience in test plan writing, executing and finding functional/performancerelated bugs Experience in test bed Creation/Management, Baseline Test setup. Good understanding of Analog & Digital modulation and networking concepts. Good knowledge on scripting languages like python, TCL, perl. Strong written and verbal communications. Experience in documentation forcorrective actions and analysis of issues. Knowledge on Regulatory & Wi-Fi Alliance certification will be additionalasset. Tessolve Semiconductor Private Limited, as well as its affiliates and subsidiaries ( Tessolve ) does not require job applicants to make any payments at any stage of the hiring process. Any request for payment in exchange for a job opportunity at Tessolve is fraudulent and should be ignored. . Tessolve is not responsible for any losses incurred due to such fraudulent activities

About Us: Tessolve offers a unique combination of pre-silicon and post-siliconexpertise to provide an efficient turnkey solution for silicon bring-up, andspec to the product. With 3200+ employees worldwide, Tessolve provides aone-stop-shop solution with full-fledged hardware and software capabilities,including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution, from design to packagedparts. Tessolve s design services include solutions on advanced process nodeswith a healthy eco-system relationship with EDA, IP, and foundries. Ourfront-end design strengths integrated with the knowledge from the backend flow,allows Tessolve to catch design flaws ahead in the cycle, thus reducingexpensive re-design costs, and risks. We actively invest in the R&D centerof excellence initiatives such as 5G, mmWave, Silicon photonics, HSIO, HBM/HPI,system-level test, and others. Tessolve also offers end-to-end product designservices in the embedded domain from concept to manufacturing under an ODMmodel with application expertise in Avionics, Automotive, Industrial andMedical segments. Tessolve s Embedded Engineering services enable customers afaster time-to-market through deep domain expertise, innovative ideas, diverseembedded hardware & software services, and built-in infrastructure withworld-class lab facilities. Tessolve s clientele includes Tier 1 clients across multiple marketsegments, 9 of the top 10 semiconductor companies, start-ups, and governmententities. We have a global presence over 12 countries with office locations inthe United States, India, Singapore, Malaysia, Germany, United Kingdom, Canada,UK, Japan, Taiwan, Philippines, and Test Labs in India, Singapore, Malaysia,Austin, San Jose. For more details, visit www.tessolve.com . Job Overview Strong background in machine learning fundamentals, including deeplearning,large language models, and recommender systems. Strong backgroundin validation, defect and software development life cycle Strong knowledgeon ubuntu / yocto linux Experience workingwith opensource frameworks such as PyTorch, TensorFlow, and ONNX-Runtime. Experience inprofiling ML workloads Prior experiencein executing validation plans for AI/ML compute stacks such as HIP, CUDA,OpenCL, OpenVINO, ONNX Runtime and TensorFlow/PyTorch integrations. Prior experiencein validating end-to-end AI pipelines, for e.g. model conversion (e.g., PyTorch ONNX), Inference runtimes (e.g, ONNX Runtime, TensorRT, ROCm/HIP),compilers/toolchains (e.g. TVM, Vitis AI, XDNA, XLA), kernel execution, memorytransfer and inference results Strong backgroundin python programming. Excellentproblem-solving skills and willingness to think outside the box. Experience withproduction software quality assurance practices, methodologies , and procedures Strong ownershipof deliverables, Excellent communication skills and experience working withglobal teams Job Location :Electronic -City, Phase II, Bangalore. What you ll do Strongbackground in machine learning fundamentals, including deep learning,largelanguage models, and recommender systems. Strongbackground in validation, defect and software development life cycle Strongknowledge on ubuntu / yocto linux Experienceworking with opensource frameworks such as PyTorch, TensorFlow, andONNX-Runtime. Experiencein profiling ML workloads Priorexperience in executing validation plans for AI/ML compute stacks such as HIP,CUDA, OpenCL , OpenVINO, ONNX Runtime and TensorFlow/PyTorch integrations. Whoyou are Prior experience in validating end-to-endAI pipelines, for e.g. model conversion (e.g., PyTorch ONNX), Inferenceruntimes (e.g, ONNX Runtime, TensorRT, ROCm/HIP), compilers/toolchains (e.g.TVM, Vitis AI, XDNA, XLA), kernel execution, memory transfer and inferenceresults Strongbackground in python programming. Excellentproblem-solving skills and willingness to think outside the box. Experiencewith production software quality assurance practices, methodologies, and procedures Strongownership of deliverables, Excellent communication skills and experienceworking with global teams Tessolve Semiconductor Private Limited, as well as its affiliates and subsidiaries( Tessolve ) does not require job applicants to make any payments at anystage of the hiring process. Any request for payment in exchange for a jobopportunity at Tessolve is fraudulent and should be ignored. . Tessolve is notresponsible for any losses incurred due to such fraudulent activities

About Us: Tessolve offers a unique combination of pre-silicon and post-siliconexpertise to provide an efficient turnkey solution for silicon bring-up, andspec to the product. With 3200+ employees worldwide, Tessolve provides aone-stop-shop solution with full-fledged hardware and software capabilities,including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution, from design to packagedparts. Tessolve s design services include solutions on advanced process nodeswith a healthy eco-system relationship with EDA, IP, and foundries. Ourfront-end design strengths integrated with the knowledge from the backend flow,allows Tessolve to catch design flaws ahead in the cycle, thus reducingexpensive re-design costs, and risks. We actively invest in the R&D centerof excellence initiatives such as 5G, mmWave, Silicon photonics, HSIO, HBM/HPI,system-level test, and others. Tessolve also offers end-to-end product designservices in the embedded domain from concept to manufacturing under an ODMmodel with application expertise in Avionics, Automotive, Industrial andMedical segments. Tessolve s Embedded Engineering services enable customers afaster time-to-market through deep domain expertise, innovative ideas, diverseembedded hardware & software services, and built-in infrastructure withworld-class lab facilities. Tessolve s clientele includes Tier 1 clients across multiple marketsegments, 9 of the top 10 semiconductor companies, start-ups, and governmententities. We have a global presence over 12 countries with office locations inthe United States, India, Singapore, Malaysia, Germany, United Kingdom, Canada,UK, Japan, Taiwan, Philippines, and Test Labs in India, Singapore, Malaysia,Austin, San Jose. For more details, visit www.tessolve.com . Job Overview : Devops Engineer - 5+ Years Job Location : Hyderabad Ongoing maintenance of CI/CD env, proactively track breakage & provide fixes Enable automation of Firmware builds and testing across different platforms Drive improvements to builds, testing, automation scripts. Mandatory: Jenkins, Github, exposure to build infra on Linux (cmake, Makefiles, gcc etc.), familiarity with building and testing embedded software, shell scripting, excellent problem-solving skills. Preferred: Github Actions, Groovy script, programming/flashing image on HW devices, python, familiarity with QEMU, CodeQL, experience with containers/dockers, AI auto-fix and AI code review. Tessolve Semiconductor Private Limited, as well as its affiliates and subsidiaries( Tessolve ) does not require job applicants to make any payments at anystage of the hiring process. Any request for payment in exchange for a jobopportunity at Tessolve is fraudulent and should be ignored. . Tessolve is notresponsible for any losses incurred due to such fraudulent activities

This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; - Grade Specific Focus on Electrical, Electronics and Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers.

Job Titles: Senior Staff ASIC RTL Design Engineer Bangalore location We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a passionate and highly skilled digital design engineer with a strong background in ASIC RTL design You thrive on technical challenges, enjoy collaborating with global teams, and are motivated by seeing your designs come to life in real-world products With over8 years of hands-on experience in architecting, implementing, and verifying complex digital systems, you are adept at translating functional specifications into efficient, robust RTL Your experience spans data path and control path designs, and you are comfortable working with industry-standard protocols such as Ethernet, DDR, PCIe, USB, and AMBA You possess deep expertise in synthesizable Verilog/SystemVerilog, design flows, and EDA tools You are equally at home mentoring junior engineers as you are diving deep into code or debugging complex issues Your ability to balance area, latency, and throughput trade-offs sets you apart, and your attention to detail ensures high-quality, reliable IP cores You communicate effectively with both technical and non-technical stakeholders and are comfortable engaging with customers to clarify requirements and ensure successful delivery You value diversity, inclusion, and continuous learning, and you bring a collaborative spirit to every project If youre ready to lead, innovate, and make a tangible impact in the world of high-performance silicon design, Synopsys is the place for you, What Youll Be Doing: Architecting, designing, and implementing state-of-the-art RTL for high-performance synthesizable IP cores within the DesignWare family, Translating complex functional and standard specifications into detailed architecture and micro-architecture documents for medium to high complexity blocks, Owning the entire digital design lifecycle, including RTL coding, synthesis, CDC analysis, debugging, and test development, Collaborating with global, multi-site teams of expert engineers to drive technical excellence and innovation, Interacting with customers to understand and refine specification requirements and providing technical guidance as needed, Mentoring and technically leading junior designers, fostering growth and sharing best practices within the team, Participating in design reviews, quality process improvements, and ensuring adherence to industry-leading verification and design methodologies, The Impact You Will Have: Delivering robust, high-quality IP cores that power next-generation commercial, enterprise, and automotive applications worldwide, Driving innovation in digital ASIC design, enabling faster, more efficient, and reliable silicon solutions for Synopsys customers, Contributing to the advancement of industry standards and protocols through technical leadership and deep domain expertise, Enhancing team performance through mentorship, knowledge sharing, and technical guidance, Strengthening Synopsysreputation as a leader in chip design by consistently delivering on complex customer requirements, Accelerating product development cycles by streamlining design processes and championing best-in-class methodologies, What Youll Need: Bachelors or Masters degree in EE, EC, or VLSI with8+ years of relevant industry experience in digital ASIC RTL design, Expertise in data path and algorithmic block design ( e-g , Reed Solomon FEC, BCH codes, MAC SEC engines) and architecture trade-offs, Proficiency in synthesizable Verilog/SystemVerilog RTL coding, simulation, and EDA tools, Hands-on experience with design flows including Lint, CDC, synthesis, static timing analysis, and formal checking, Strong knowledge of industry-standard protocols (Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA AXI/AMBA2), Experience with high-speed design (>600MHz), P&R aware synthesis, and tools like Fusion Compiler is a significant plus, Familiarity with revision control systems ( e-g , Perforce) and scripting languages (Perl/Shell), Prior experience as a technical lead or mentor within a design team is highly desirable, Who You Are: A collaborative team player who thrives in a global, distributed environment, An effective communicator, adept at conveying complex technical ideas to diverse stakeholders, A proactive problem-solver with strong analytical skills and high initiative, Detail-oriented, quality-focused, and committed to delivering excellence, Passionate about mentoring and enabling the growth of others, Dedicated to diversity, inclusion, and fostering an open, respectful workplace, The Team Youll Be A Part Of: Youll be an integral member of the DesignWare IP Design R&D team at Synopsys Bangalore, collaborating with some of the brightest minds in the industry The team is focused on developing cutting-edge synthesizable IP cores that are deployed in a wide range of commercial, enterprise, and automotive applications Working in a multi-site, global environment, youll have opportunities to engage with cross-functional teams, contribute to technical excellence, and drive innovation in digital design, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process, Show

Description The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and re-imagined user experience through Echo and Alexa We want you to help us build on the success of our first generation of ML accelerator at edge, Work hard Have fun Make history, We are seeking a seasoned and strategic Sr DFT Engineer to Lead end-to-end Design-for-Test (DFT) planning, execution, and silicon readiness for complex SoCs This role demands deep technical expertise, hands-on ownership, and proven leadership in taking chips from design to volume production, As a Senior DFT Engineer, you will be both the technical owner and hands-on driver of the DFT strategy and execution across complex, high-performance SoCs This role requires deep technical expertise, the ability to architect scalable and robust DFT solutions, and the discipline to personally engage in implementation and debug You will work alongside world-class design, validation, and test teams to ensure first-pass silicon success and scalable production test readiness Ideal for a seasoned leader, this role combines strategic ownership with direct execution, driving full lifecycle accountability from early DFT architecture planning to high-volume silicon bring-up and yield ramp, Lead development & implementation of DFT architecture including system level DFT for a full chip Write and guide others in writing design flow and project documentation, Own DFT planning, milestone tracking, and cross-functional checklist reviews, Oversee design, insertion, and verification of DFT logic and components into full SoC and subsystem RTL netlists, Review and sign-off SoC level DFT mode timing closure using static timing analysis Drive the sign-off on a generation of high-quality test and debug patterns for high coverage on silicon Keep informed on and introduce new technology into Design-for-Test process as appropriate, Education BASIC QUALIFICATIONS BS/BE or MS/ME in Electrical Engineering, Computer Engineering, or related field, Experience 15+ years in SoC/ASIC DFT, including 3+ years Leading DFT, Proven DFT experience leading multiple SoCs/ASICs (end-to-end) from architecture to high-volume production, DFT Architecture Expertise Proven capability in architecting and implementing DFT strategies at both subsystem and top-level, including: Scan architecture, compression, and ATPG implementation for high fault coverage and test quality, MBIST, BISR, and BIHR flows, including advanced shared-bus memory BIST integration, IEEE 1149 x (Boundary Scan), IEEE 1500, and IEEE 1687 (IJTAG) test architectures, DFT-Aware STA closure, including constraint generation and timing convergence strategies for shift and capture paths, RTL and gate-level debug, including mismatch triage and simulation correlation, Insertion and Validation of EFUSE & OTP controllers and related structures during DFT implementation, Tool Proficiency Deep hands-on experience with Tessent / Industry Std EDA tools, including: IJTAG ICL extraction and PDL modeling, DFT logic insertion, pattern generation, and diagnostics, Design Background Experience in writing verilog/system verilog RTL related to DFT logic design, ATE Test Readiness Lead DFT-to-ATE handoff, including: Drive generation and sign-off of high-quality test and debug patterns to meet DFT coverage targets, Pattern validation, format conversion, and debugging across wafer sort and final test, Collaboration with PE/Test teams for silicon correlation and production test optimization, yield improvements, Silicon Debug Drive post-silicon validation, failure triage, and yield learning using SCAN diagnosis and MBIST repair signature analysis, Automation Skills Ability to build and maintain scalable DFT automation flows using Python, Tcl, or Perl, Collaboration Proven success driving cross-functional teams involving RTL, physical design, validation, PE, and manufacturing, Execution Excellence Known for being proactive, detail-oriented, and independently accountable for tapeout and post-silicon success, Leadership PREFERRED QUALIFICATIONS Led multi-site/global DFT teams, mentoring engineers and managing design reviews, Drove design-for-test planning in collaboration with customers or design services partners, Technical Depth Strong understanding of DFT-Aware yield improvement and FA, including DPPM reduction strategies, Ability to correlate pre-silicon vs ATE pattern behavior and debug marginality/escape issues, Exposure to Design-for-Debug (DfD) features like trace buffers, signature capture, and observability enhancement, Our inclusive culture empowers Amazonians to deliver the best results for our customers If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, amazon jobs / content / en / how-we-hire / accommodations for more information If the country/region youre applying in isnt listed, please contact your Recruiting Partner, Company ADCI BLR 14 SEZ Job ID: A3037331 Show

Job Summary: Seeking an experienced FPGA developer to join our team and work on the design and development of complex FPGA-based systems. The ideal candidate will have a strong background in FPGA design, verification, and implementation, as well as experience working with hardware and software engineers to integrate FPGA designs into larger systems.

Gatan, Inc. is the worlds leading manufacturer of instrumentation and software used to enhance and extend the operation and performance of electron microscopes. Gatan products, which are fully compatible with nearly all electron microscope models and include the EDAX portfolio, cover the entire range of the research process from specimen preparation and manipulation to imaging and analysis. We are currently seeking an experienced Senior Design Verification Engineer for our imaging and analytical products who will be responsible for verification of designs and developing verification environments for high performance embedded systems. This individual will be working closely with the Software and Hardware groups in United States. Some common hours with the US teams in California and Pennsylvania are required. This position will be based out of our Bangalore, India office. The primary function of this role will be as a design verification engineer, developing verification environments, test cases, producing regression reports and managing release of firmware. MINIMUM REQUIREMENTS: Experience in system and hardware modeling and verification Experience with simulation and verification in a Linux environment ASIC or FPGA verification at chip and system level Reviewing architecture specifications Experience in specifying and developing verification infrastructure, test bench design and verifying complex hardware, software and performance modeling Experience with modern simulators and debuggers, e.g. Questa, Vivado, Quartus etc. Expertise in C/C++, System Verilog, Python, UVM etc. Develop test cases, coverage reports and regressions Strong analytical problem-solving skills and attention to detail Excellent organizational, written and verbal communication skills DESIRABLE SKILL AND EXPERIENCE: Knowledge of image sensor data processing a plus Experience with image processing or CPU/GPU validation a plus EDUCATION & EXPERIENCE: BS in Electrical Engineering, Computer Science or Computer Engineering from a four-year college or university, MS degree is a plus 10+ years of hardware development and verification experience

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. About The Role As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Additional About The Role Additional About The Role Job Role * Work with multiple SOC Design teams to rollout robust Logic Synthesis, UPF synthesis, QoR optimization and netlist Signoff flows* Provide implementation flows support and issue debugging services to SOC design teams across various site* Develop and maintain 3rd party tool integration and product enhancement routines * Should lead implementation flow development effort independently by working closely with design team and EDA vendors * Should drive new tool evaluation, methodology refinement for PPA optimization Skill Set * Proficiency in Python/Tcl * Familiar with Synthesis tools (Fusion Compiler/Genus), * Fair knowledge in LEC, LP signoff tools* Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking* Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus* Should be sincere, dedicated and willing to take up new challenges Experience 13+ years of experience in RTL,UPF & Physical aware Synthesis for cutting edge technology nodes, logic equivalence checking, Scripting and Netlist Timing Signoff Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Job Responsibilities Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 4+ years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Minimum 4+ years of experience in PD Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Responsibilities Defining chip and macro level power domains System Level Power Modeling Mixed signal power analysis Power Island/Power Gating/Power Isolation Structural Low power design of level shifter and isolation cell topology and associated rules Architectural analysis and development of digital power optimization logic/circuits/SW Work with Power Management IC developers for power grid planning Creating detailed architecture and implementation documents Education Requirements RequiredBachelor's, Computer Engineering and/or Electrical Engineering PreferredMaster's, Computer Engineering and/or Electrical Engineering Work with cross-functional teams on SoC Power and architecture for mobile SoC ASICs. Skills/Experience At least 4-12 years of experience are required in the following areas Low power intent concepts and languages (UPF or CPF) Power estimation and reduction tools (PowerArtist/PTPX,Calypto) Power dissipation and power savings techniques- Dynamic clock and voltage scaling Power analysis (Leakage and dynamic) and thermal impacts Power Software features for power optimization Voltage regulators including Buck and Low Drop out ASIC Power grids and PCB Power Distribution Networks Additional skills in the following areas are a plus: Mobile Baseband application processors chipset and power grid understanding UPF-based synthesis and implementation using Design Compiler Structural low power verification tools like CLP or MVRC Outstanding written and verbal communication skills Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Bachelors /Masters degree in Engineering Relevant experience of 6+yrs in any of the mentioned domain - Verification/ Emulation/ Validation Verification: Strong knowledge of digital design and SOC architecture. Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C Experience in HDL such as Verilog Knowledge of ARM/DSP CPU architecture, High Speed Peripherals like USB2/3, PCIE or Audio/Multimedia Familiarity with Power-aware Verification, GLS, Test vector generation is a plus Exposure to Version managers like Clearcase/perforce FPGA Emulation : Familiarity with Verilog/Vhdl and General Digital Logic Design concepts Knowledge of system-level architecture including buses like ARM processor bringup, AXI/AHB, bridges, memory controllers such as DDR/Nand. Knowledge of peripheral emulation like PCIE/USB is a plus. Strong working knowledge of UNIX environment and scripting languages such as Perl or shell Working knowledge XILINX Virtex FPGA architecture and experience with ISE tool flow Pre/Post silicon Validation: ARM based System-On-Chip Pre-Silicon emulation and Post-Silicon ASIC Validation experience related to board bring up and debug. Perform system level validation and debug Debug experience with Lauterbach Trace32 environment. Test equipment like Logic analyzer, Oscilloscope and Protocol analyzers. Embedded software development of low level hardware drivers in C language. Working experience related to one or more of the following is required. ARM/DSP Processors/USB/PCIE, Ethernet Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Where IP Design Technical Lead/ Staff ASIC RTL Design Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12276 Remote Eligible No Date Posted 24/07/2025 Job Title: IP Design Technical Lead/ Staff ASIC RTL Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and forward-thinking digital design expert with a strong foundation in ASIC RTL design and a proven track record of delivering complex, high-performance IP cores. With a Bachelor s or Master s degree in EE, EC, or VLSI and over four years of relevant industry experience, you thrive in dynamic, multi-site environments and excel at translating functional specifications into robust, scalable architectures. You re adept at working with advanced protocols such as Ethernet, DDR, PCIe, and USB, and have hands-on experience in data path and control path design, including Reed Solomon FEC, BCH codes, and MAC SEC engines. Your expertise extends to synthesizable Verilog/SystemVerilog coding, timing closure, CDC analysis, and P&R-aware synthesis, complemented by a keen understanding of design trade-offs in area, latency, and throughput. You are comfortable leveraging version control systems like Perforce and scripting languages such as Perl or Shell to automate and streamline workflows. As a natural leader, you are ready to mentor and technically guide a team of designers, fostering a collaborative and inclusive culture. Communication comes easily to you, and you re known for your proactive problem-solving skills, attention to detail, and unwavering commitment to design quality. You re seeking an opportunity to take ownership of challenging projects, contribute to cutting-edge innovation, and grow alongside a team of world-class engineering professionals. What You ll Be Doing: Architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications. Translating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features. Leading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks. Collaborating with global teams and engaging directly with customers to understand and refine specification requirements. Driving technical excellence in design processes, including linting, static timing analysis, formal checking, and P&R-aware synthesis using tools such as Fusion Compiler. Mentoring and technically leading a team of designers, providing guidance on best practices and innovative design methodologies. Utilizing version control systems and scripting to manage design flows and automate repetitive tasks for improved efficiency. The Impact You Will Have: Enable Synopsys to deliver industry-leading, high-performance IP cores that power next-generation technologies. Contribute to the successful execution of complex, global projects that set new standards in chip design and verification. Accelerate time-to-market for customers in commercial, enterprise, and automotive sectors by delivering robust, reliable IP solutions. Elevate the technical capabilities of your team through mentorship and leadership, cultivating a culture of continuous learning and innovation. Drive improvements in design quality, efficiency, and scalability through process optimization and automation. Directly influence product architecture and feature enhancements, ensuring alignment with customer needs and emerging industry trends. What You ll Need: Bachelor s or Master s degree in Electrical Engineering, Electronics, VLSI, or related field. 4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects. Deep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines. Proficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis. Familiarity with high-speed design (>600MHz), P&R-aware synthesis, and EDA tools such as Fusion Compiler. Experience with version control systems (e.g., Perforce) and scripting languages (Perl, Shell) for design automation. Knowledge of industry protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA (AMBA2, AXI). Exposure to quality processes in IP design and verification is an advantage. Prior experience as a technical lead or mentor is highly desirable. Who You Are: Innovative thinker with a solutions-oriented mindset and a passion for technology. Excellent communicator who thrives in collaborative, multicultural, and multi-site environments. Natural leader with mentoring abilities, fostering inclusion and diversity within the team. Detail-oriented professional with strong analytical and problem-solving skills. Self-motivated, adaptable, and eager to drive technical excellence and process improvements. Committed to continuous learning and staying ahead of industry trends. The Team You ll Be A Part Of: You will join the R&D Solutions Group at our Bangalore Design Center, as part of the DesignWare IP Design team. This diverse and innovative group is dedicated to architecting, developing, and delivering cutting-edge IP cores that enable Synopsys global customers to achieve their design goals. The team thrives on collaboration, technical excellence, and shared success, working in a supportive environment that values creativity, knowledge sharing, and continuous growth. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: General Summary: Qualcomm is the world's leading developer of next generation of always on Display technologies and is committed to building a world-class organization that will lead the industry. Be part of the team developing next generation Display subsystems and Display peripherals. The ASIC Systems Architect is responsible for system architecture definition activities supporting a sophisticated multimedia Low Power Display subsystem catering to various market segments like mobile, XR, compute, IOT, Wearables and automotive products. Candidates will be responsible for all aspects of the ASIC hardware architecture definition/validation including the following: Owning end to end system architecture Capturing detailed technology requirements working closely with product, hardware and software engineering teams for deriving subsystem hardware specification. Engage with all stakeholders and collaborate with cross functional teams to define robust architecture Defining architecture validation plans and reviewing development results Optimization and debug via modelling, system simulation and testing across key criteria including power and performance. Collaborating, reviewing and enabling design and system teams to execute independently from the specifications Engage and provide support from Concept to Commercialization, Post-silicon commercialization support and customer engineering documentation Defining and patenting novel architectures that drive industry leadership. Job Function: Oversees hardware architecture for ASIC systems development for a variety of products. Determines architecture design, and validation via system simulation. Defines module interfaces/formats for simulation. Ability to analyze and solve complex problems through various mechanisms. Ability to optimize architecture for Area, Performance and power efficiency. Evaluates all aspects of the HW architecture flow from high-level development to validation and review. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. Uses System tools, such as, MathWorks MATLAB, SIMULINK, VISIO and other toolboxes. Uses language such as HDL, C/C++, System C, Perl, Python. Provides technical expertise for next generation initiatives. Leverages experience in image processing, SoC hardware and computer architecture concepts to develop proposals to address system Display requirements using processor, memory, bus and low-power design techniques. Uses expertise in low-power design methodology, optimization and validation using various CAD tools and design techniques to optimize system power. Leverages experience in digital system performance analysis and systems modelling to ensure performance goals met. Leverages Verilog/VHDL and digital hardware design tools such as Synopsys/Cadence/Mentor ASIC design and simulation tool sets, power analysis and simulation, scripting languages (Python, Perl, TCL, C, etc.) to optimize system. Effectively utilizes advanced problem solving and ASIC engineering practices to resolve complex architecture, design, or verification problems. Writes technical documentation and provides technical expertise for design or project reviews and project meetings. Acts as a tech lead on small to large projects and owns team deliverables of the project Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum Qualifications: Bachelor's degree in, Electronics/Computer Science Engineering, or related field and 7+ years of ASIC design, verification, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, or related work experience. OR PhD in Science, Engineering, or related field. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Synthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation. Development of signoff quality constraints and the development of power intent constraints. May also include running RTL Lint, CLP, MEMBIST, DFT DRC etc. TCL script development in addition to running/analyzing/debugging designs. Hands on with Synopsys DCG/Genus/Fusion Compiler. Hands on with Synopsys Prime Time including constraint development for complex blocks with multiple clock domains. Hands on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development Experience with either RTL development or Physical Design is also a plus 6+ years experience Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 10-15 years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience Education Requirements RequiredBachelor's, Electrical Engineering or equivalent experiencePreferredMaster's, Electrical Engineering or equivalent experience Keywords Innovus, FC, UPF, STA, Formal Verification, Genus, Primetime, Tempus, SOD Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: 3 to 15 years of work experience in ASIC/SoC Design Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Experience creating padring and working with the chip level floorplan team is an added advantage. Excellent oral and written communications skills Proactive, creative, curious, motivated to learn and contribute with good collaboration skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: About The Role Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in. You will be joining a successful engineering team whose deliveries can be found in billions of mobile, compute and IoT products worldwide. Based out of Qualcomm's Bangalore office, this role offers a position in Low Power controller IP cores and subsystem digital design targeted for variety of industry leading Snapdragon SoCs for mobile, compute, IoT and Automotive markets. Key Responsibilities Micro-architecture and RTL design for Cores / subsystems. Work in close coordination with Systems, Verification, SoC, SW, PD & DFT teams for design convergence. Enable SW teams to use HW blocks. Qualify designs using static tool checks including Lint, CDC, LEC and CLP. Synthesis, LEC and Netlist CLP Report status and communicate progress against expectations. Preferred Qualifications 4 to 10 years of strong experience in digital front end design (RTL design) for ASICs Expertise in RTL coding in Verilog/SV/VHDL of complex designs with multiple clock domains and multiple power domains Familiar with UPF and power domain crossing Experience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI Experience in low power design methodology and clock domain crossing designs Experience in Spyglass Lint/CDC checks and waiver creation Experience in formal verification with Cadence LEC Understanding of full RTL to GDS flow to interact with DFT and PD teams Expertise in Perl/TCL/Python language Experienced in database management flows with Clearcase/Clearquest. Expertise in post-Si debug is a plus Excellent oral and written communications skills to ensure effective interaction with Engineering Management and team members. Team player, self-motivated, should be able to work with minimal supervision. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: Qualcomm is looking for talented and enthusiastic engineers with strong interests in OS, kernel and computer architecture. The Qualcomm Hypervisor team is world-leading, enabling virtualization across multiple chipset products for mobile, automotive, compute and IoT. The team is responsible for the hypervisor software layers that plays a key role in platform security and performance. Qualcomm is industry leading in its adoption of virtualization technology in its Snapdragon mobile products. The team has built hypervisor and SMMU expertise and continues to develop innovative features, enhancements, and use-cases. As a software engineer at Qualcomm, you will help develop SMMU, hypervisor and related software for the latest cutting-edge Application processors, which is embedded in a wide range of chipset products and used by many OEMs in millions of devices. The role will include interfacing with large software stacks such as Bootloaders, Linux and TrustZone- which provides the opportunity to interact with teams around the world. -- Responsibilities We are looking for a highly motivated engineer and team player who is passionate to learn new technologies and write low level firmware that drives hardware and SoC. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. 2+ years of work experience with Programming Language such as C, C++, Java, Python, etc. Your responsibilities may include: Design, development and integration of SoC firmware features, diagnostics and test capabilities for QCT boot platforms. Strong coordination and collaboration across wide range of technical areas to include software, hardware, ASIC, integration, architecture, and emulation teams. Paying attention to the details during all phases of firmware design, development, integration, testing and release - Work with Emulation, HW design teams, as necessary, in verifying and debugging firmware, driver and resolving platform issues Efficient and secure (ie. cognizant of not exposing security exploits) coding plus driving code review of firmware logic updates with all required stakeholders On time execution of defined tasks and deliverables, driving dependencies with other teams to closure Triage of software issues, defect investigation and problem resolution. Technical documentation including APIs, manuals, and user guides.- Skills and Experience We are looking for engineers from a range of backgrounds and experience, including graduates and experienced kernel and systems developers Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 8+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Software Engineering or related work experience. Preferred Qualifications: Strong understanding or experience with C. An understanding of computer architecture, operating systems, and kernels. Linux, kernel, bootloader or OS development experience. ARM CPU architecture knowledge. IOMMU and ARM SMMU knowledge Hypervisors and virtualization. Experience with multi-processing or multi-threading, concurrency, and synchronization. Writing device drivers and interfacing hardware. Experience with secure coding. Use of debugging tools such as GDB, Lauterbach Trace32 and understanding assembly. Real-time OS. Toolchains and systems libraries (libc etc). Python, shell scripting and Linux based development environment. Good communication and presentation skills. Test development and test automation. Contributing to open-source projects. Demonstrated independent software design, good analytic and problem-solving skills. Any automotive and functional safety experience may also be relevant. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.