Over 10 years of digital IP verification, advanced knowledge of ASIC/SOC Design flow and state of the art verification flow Proficient with Verilog, System Verilog and UVM. · Good in UVM concepts and SystemVerilog language. (SVA, UVM scoreboard) · Good in defining and developing UVM based verification frameworks, testbenches, processes and flows. · Good in working in Linux and Windows environments. · Familiarity with power aware simulation and firmware/hardware co-verification is a plus. · Familiarity with industry standard high-speed protocols such as USB, PCIE, UFS, SATA, Ethernet is a plus. · Familiarity with industry standard interconnects such as AMBA (AXI, APB, AHB) is a plus. Show more Show less

Over 8 years of digital IP verification, advanced knowledge of ASIC/SOC Design flow and state of the art verification flow Proficient with Verilog, System Verilog and UVM. · Good in UVM concepts and SystemVerilog language. (SVA, UVM scoreboard) · Good in defining and developing UVM based verification frameworks, testbenches, processes and flows. · Good in working in Linux and Windows environments. · Familiarity with power aware simulation and firmware/hardware co-verification is a plus. · Familiarity with industry standard high-speed protocols such as USB, PCIE, UFS, SATA, Ethernet is a plus. · Familiarity with industry standard interconnects such as AMBA (AXI, APB, AHB) is a plus. Show more Show less

Over 5 years of digital IP verification, advanced knowledge of ASIC/SOC Design flow and state of the art verification flow Proficient with Verilog, System Verilog and UVM. · Good in UVM concepts and SystemVerilog language. (SVA, UVM scoreboard) · Good in defining and developing UVM based verification frameworks, testbenches, processes and flows. · Good in working in Linux and Windows environments. · Familiarity with power aware simulation and firmware/hardware co-verification is a plus. · Familiarity with industry standard high-speed protocols such as USB, PCIE, UFS, SATA, Ethernet is a plus. · Familiarity with industry standard interconnects such as AMBA (AXI, APB, AHB) is a plus. Show more Show less

Summary: Over 8 years of experience in digital IP verification with a strong understanding of ASIC/SoC design and state-of-the-art verification methodologies. Proficient in Verilog , SystemVerilog , and UVM , with solid expertise in developing and maintaining UVM-based verification frameworks, testbenches, and processes. Strong grasp of UVM concepts, including SystemVerilog Assertions (SVA) and scoreboard architecture . Familiar with industry-standard high-speed protocols such as USB , PCIe , UFS , SATA , and Ethernet . Well-versed with standard interconnects like AMBA (AXI, APB, AHB) . Show more Show less

Job Summary: We are looking for a highly experienced RTL Design Lead to drive the architecture, micro-architecture, and RTL development of digital IP/SoC blocks. The ideal candidate should have a solid background in RTL design using Verilog/SystemVerilog, along with experience in leading teams and interfacing with verification, DFT, and physical design teams. Key Responsibilities: Lead RTL design activities for complex IPs or SoC sub-systems. Work closely with architects to translate high-level specifications into micro-architecture and RTL. Drive design reviews, coding standards, and technical quality. Define and implement RTL design methodologies and flows. Collaborate with verification, DFT, synthesis, and backend teams to ensure successful integration and tapeout. Guide and mentor junior designers in the team. Support silicon bring-up and debug as needed. Required Skills: Proven track record of delivering IP or SoC designs from spec to GDSII. Experience in micro-architecture development , pipelining, and clock-domain crossing. Good understanding of ASIC design flow , including synthesis, STA, and linting. Hands-on experience with AMBA protocols (AXI/APB/AHB) and other standard interfaces. Strong debugging and problem-solving skills. Familiarity with low-power design techniques is a plus. Preferred Skills: Exposure to high-speed protocols (PCIe, USB, Ethernet, etc.). Familiarity with scripting languages (Python, Perl, TCL) to automate design tasks. Experience with tools like Synopsys DC, Spyglass, Verdi, VCS, etc. Prior experience in leading and mentoring a small team. Educational Qualification: Bachelor’s or Master’s degree in Electronics/Electrical Engineering or related field. Show more Show less

About the Role Skills: Strong in IP / SoC-level verification Responsibilities Proficient in testbench and testcase development (SystemVerilog/UVM preferred) Clear understanding of verification plans, coverage metrics, and debugging Experience: 5+ years in Design Verification Required Skills Strong in IP / SoC-level verification Proficient in testbench and testcase development (SystemVerilog/UVM preferred) Clear understanding of verification plans, coverage metrics, and debugging Availability: Immediate to within 4 weeks Show more Show less

Job Description: We are seeking a Physical Design Lead with strong expertise in RTL-to-GDSII flow for advanced technology nodes (7nm and below). The role involves leading SoC/IP physical implementation, driving PPA goals, and ensuring successful tapeouts. You will manage a team, interface with cross-functional groups, and own block/top-level execution. Key Skills: Floorplanning, Placement, CTS, Routing, Signoff STA, IR/EM, Power & Physical Verification EDA tools: Innovus, PrimeTime, Calibre, etc. Scripting (TCL/Perl/Python), UPF, ECOs Strong leadership & communication skills

We’re Hiring – SoC & GLS Verification Engineers! 📍 Location: Bangalore / Hyderabad 🧠 Experience: 5–10 Years Join our growing team at BITSILICA and work on cutting-edge SoC designs! 🔧 Skills We’re Looking For: ✔️ SoC & GLS Verification ✔️ SystemVerilog, UVM, C ✔️ AMBA protocols (AXI, AHB, APB) ✔️ DSP module verification (Nice to have) 📩 Send your resume to: Viswanadha.reddy@bitsilica.com

BITSILICA is currently seeking experienced professionals for a position with the following specifications: Experience: 3 to 7 years. Location: Hyderabad. Skills Required: - Strong programming skills in C/C++. - Minimum 3 years of experience in Multimedia (Audio, Video, Camera, Display, Graphics). - Proficient in Multithreading and thorough understanding of Linux internals. - Expertise in Linux kernel device driver concepts. - Sound knowledge of Embedded software development and skilled in Debugging. If you meet the above requirements and are interested in this opportunity, kindly share your updated resume with vaishnavi.mettugari@bitsilica.com.,

As a skilled professional in Standard Cell Library Development, you will leverage your hands-on experience and expertise to contribute effectively to the characterization processes. Your solid understanding of CMOS and FinFET technologies will be key in ensuring the success of the projects at hand. Additionally, exposure to Verilog modeling will be advantageous in this role, although it is not mandatory. Your role will require strong debugging and problem-solving skills specifically related to cell design, SPICE simulation, and characterization. This will enable you to address challenges effectively and ensure the quality of the developed libraries. Proficiency in EDA tools is essential for this position. Experience with tools such as Cadence Virtuoso, Calibre, HSPICE, and other industry-standard simulation and characterization tools will be beneficial in carrying out your responsibilities efficiently. Overall, your role will be crucial in contributing to the development of Standard Cell Libraries, and your expertise will play a vital part in the success of the projects.,