290 Cdc Jobs

Expertise in ASIC RTL Design Expertise in ASIC IP Design Expertise in CDC and Lint tools Expertise in design and simulation tools Expertise in Video processing algorithms / interfaces Expertise in CXL / PCIe Protocol, 5G, Datacenter

THE ROLE Trintechs Senior Database Administrator role affords a motivated and qualified candidate to work within the database team as part of a globally-distributed team of Site Reliability Engineers responsible for SaaS applications in a 24x7 production environments across the globe. The Senior Database Administrator will report to the Senior Manager of Cloud/SaaS and work with the database team. In addition, working with the Enterprise Architecture team in the overall Chief Technology Officers organization. WHO YOU ARE Bachelors Degree in Computer Science, Information Systems, or a related field. Will consider an equivalent combination of education and work experience. Excellent written, oral, presentation, and interpersonal communication skills. 5+ years of experience managing Microsoft SQL Server technologies across the full SDLC. 5+ years of experience supporting databases in 24x7 production environments. Experience designing, building and managing database environments to meet RTOs/RPOs and Business continuity/disaster recovery (BC/DR) requirements via clustering, virtualization, log shipping, etc. Experience with CDC configuration and log/data retirement Proficient in T-SQL and/or PL/SQL. PowerShell and/or shell scripting experience. Experience with SQL Server clustering, replication, and Always On Availability Groups. Experience with third-party database monitoring tools desired (e.g., SentryOne, Idera, Qwest, Redgate, etc.) it is a plus. Experience working in consulting or other high-growth, fast-paced agile environments where technology is leveraged as an asset to drive culture, quality, and velocity. Prior experience in organizations leveraging agile and/or ITIL/ITSM methodologies it is a plus. Able to adhere to technical standards that augment security and infrastructure architecture. Ability to strongly influence peers and technical staff within the team.

About The Role Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Amazon Web Services (AWS) Good to have skills : NA Minimum 7.5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your typical day will involve collaborating with various teams to ensure project milestones are met, facilitating discussions to address challenges, and guiding your team through the development process. You will also engage in strategic planning to align application development with organizational goals, ensuring that the solutions provided are effective and efficient. Your role will require you to stay updated with industry trends and best practices to drive innovation within your team and the broader organization. Roles & Responsibilities:- Expected to be an SME.- Collaborate and manage the team to perform.- Responsible for team decisions.- Engage with multiple teams and contribute on key decisions.- Provide solutions to problems for their immediate team and across multiple teams.- Mentor junior team members to enhance their skills and knowledge.- Facilitate regular team meetings to discuss progress and address any roadblocks. Professional & Technical Skills: - Must To Have Skills: Proficiency in Amazon Web Services (AWS).- Must have experience in AWS with CDC.- Good to have experience in Blu Age.- Strong understanding of cloud architecture and deployment strategies.- Experience with application development and integration in cloud environments.- Familiarity with DevOps practices and tools for continuous integration and delivery.- Ability to troubleshoot and optimize cloud-based applications. Additional Information:- The candidate should have minimum 7.5 years of experience in Amazon Web Services (AWS).- This position is based at our Gurugram office.- A 15 years full time education is required. Qualification 15 years full time education

As a Data Engineering Senior Associate at Microsoft, Fabric, Azure (Databricks & ADF), PySpark, your role will involve: - Requirement gathering and analysis - Designing and implementing data pipelines using Microsoft Fabric & Databricks - Extracting, transforming, and loading (ETL) data from various sources into Azure Data Lake Storage - Implementing data security and governance measures - Monitoring and optimizing data pipelines for performance and efficiency - Troubleshooting and resolving data engineering issues - Providing optimized solutions for any problem related to data engineering - Working with a variety of sources like Relational DB, API, File System, Realtime streams, CDC, etc. - Demonstrating strong knowledge on Databricks, Delta tables Qualifications Required: - 4-10 years of experience in Data Engineering or related roles - Hands-on experience in Microsoft Fabric and Azure Databricks - Proficiency in PySpark for data processing and scripting - Strong command over Python & SQL for writing complex queries, performance tuning, etc. - Experience working with Azure Data Lake Storage and Data Warehouse concepts (e.g., dimensional modeling, star/snowflake schemas) - Hands-on experience in performance tuning & optimization on Databricks & MS Fabric - Understanding CI/CD practices in a data engineering context - Excellent problem-solving and communication skills - Exposure to BI tools like Power BI, Tableau, or Looker Additional Details: - Experienced in Azure DevOps is a plus - Familiarity with data security and compliance in the cloud - Experience with different databases like Synapse, SQL DB, Snowflake etc.,

As an experienced ASIC RTL Design Engineer at MarvyLogic, you will be responsible for designing cutting-edge solutions that impact various industries. Your role will involve working with multiple clock and power domains, integrating and validating MIPI cores, debugging, and implementing CSI/DSI controllers. Your expertise in Verilog/System Verilog will be crucial in creating micro-architecture specifications, reviewing vendor IP integration guidelines, and running integrity check tools to ensure compliance with coding standards. Additionally, you will play a key role in the design verification and physical implementation processes to meet performance goals. **Key Responsibilities:** - Utilize your 10+ years of ASIC RTL Design experience to develop innovative solutions - Demonstrate proficiency in Verilog/System Verilog and experience with multiple clock and power domains - Integrate and validate CSI/DSI/DPHY/CPHY/other MIPI cores, including controllers and SerDes - Debug CSI/DSI issues and design and implement CSI/DSI controllers - Create block-level micro-architecture specifications outlining interfaces, timing behavior, and design tradeoffs - Review vendor IP integration guidelines and ensure compliance throughout the design flow - Run integrity check tools such as Lint/CDC/DFT/LEC/UPF to meet coding and implementation guidelines - Participate in design verification and physical implementation processes to achieve area, power, and performance goals **Qualifications Required:** - 10+ years of ASIC RTL Design experience - Graduate Degree in Electrical/Electronics Engineering (Post Graduate degree is a plus) - Experience with CSI/DSI debug and FPGA netlist releases - Familiarity with ASIC product life cycle (requirements, design, implementation, test, and post-silicon validation) - Strong communication skills and ability to collaborate with multi-site teams At MarvyLogic, we foster a culture that values passion for technology solutions and individual growth. Working with us will provide you with exposure to diverse industries and emerging technologies, helping you evolve both professionally and personally towards a more fulfilling life.,

AccioJob is conducting an Offline Hiring Drive with a Leading Financial Services Company Roles: Data Analyst Intern : https://go.acciojob.com/nwHgTb Data Analyst (Min Experience: 1 year) : https://go.acciojob.com/A5cxKZ 1. Intern Role: Data Analytics Intern (2025 & 2026 Graduates) Skills Required: SQL, Python, Data Pipelining Stipend: 20K 40K per month Duration: 6 months Internship PPO Opportunity: 12 20 LPA Location: Hyderabad Eligibility: B.E/B.Tech/MCA/M.Tech | Graduation Year: 2025 & 2026 | Branches: CS/IT/Electronics/Data Science & AI 2. Full-Time Role: Data Analytics Engineer (2022, 2023, 2024 Graduates with minimum 1 year corporate experience) Skills Required: CDC, Spark, Parquet Data Format CTC: 12 25 LPA Location: Hyderabad Eligibility: B.E/B.Tech/MCA/M.Tech | Graduation Year: 2022, 2023, 2024 | Minimum 1 year corporate experience Evaluation Process (for all roles) Round 1: Assessment at Hyderabad Skill Centre Round 2: 2 Technical Interviews (Face-to-Face, Company Side) Important Notes Candidates should be available for face-to-face interviews in Hyderabad if required Immediate joiners only

About the Opportunity Job TypeApplication 31 July 2025 TitlePrincipal Data Engineer (Associate Director) DepartmentISS LocationBangalore Reports ToHead of Data Platform - ISS Grade 7 Department Description ISS Data Engineering Chapter is an engineering group comprised of three sub-chapters - Data Engineers, Data Platform and Data Visualisation that supports the ISS Department. Fidelity is embarking on several strategic programmes of work that will create a data platform to support the next evolutionary stage of our Investment Process.These programmes span across asset classes and include Portfolio and Risk Management, Fundamental and Quantitative Research and Trading. Purpose of your role This role sits within the ISS Data Platform Team. The Data Platform team is responsible for building and maintaining the platform that enables the ISS business to operate. This role is appropriate for a Lead Data Engineer capable of taking ownership and a delivering a subsection of the wider data platform. Key Responsibilities Design, develop and maintain scalable data pipelines and architectures to support data ingestion, integration and analytics.Be accountable for technical delivery and take ownership of solutions.Lead a team of senior and junior developers providing mentorship and guidance.Collaborate with enterprise architects, business analysts and stakeholders to understand data requirements, validate designs and communicate progress.Drive technical innovation within the department to increase code reusability, code quality and developer productivity.Challenge the status quo by bringing the very latest data engineering practices and techniques. Essential Skills and Experience Core Technical Skills Expert in leveraging cloud-based data platform (Snowflake, Databricks) capabilities to create an enterprise lake house.Advanced expertise with AWS ecosystem and experience in using a variety of core AWS data services like Lambda, EMR, MSK, Glue, S3.Experience designing event-based or streaming data architectures using Kafka.Advanced expertise in Python and SQL. Open to expertise in Java/Scala but require enterprise experience of Python.Expert in designing, building and using CI/CD pipelines to deploy infrastructure (Terraform) and pipelines with test automation.Data Security & Performance Optimization:Experience implementing data access controls to meet regulatory requirements.Experience using both RDBMS (Oracle, Postgres, MSSQL) and NOSQL (Dynamo, OpenSearch, Redis) offerings.Experience implementing CDC ingestion.Experience using orchestration tools (Airflow, Control-M, etc..) Bonus technical Skills: Strong experience in containerisation and experience deploying applications to Kubernetes.Strong experience in API development using Python based frameworks like FastAPI. Key Soft Skills: Problem-Solving:Leadership experience in problem-solving and technical decision-making.Communication:Strong in strategic communication and stakeholder engagement.Project Management:Experienced in overseeing project lifecycles working with Project Managers to manage resources. Feel rewarded For starters, well offer you a comprehensive benefits package. Well value your wellbeing and support your development. And well be as flexible as we can about where and when you work finding a balance that works for all of us. Its all part of our commitment to making you feel motivated by the work you do and happy to be part of our team. For more about our work, our approach to dynamic working and how you could build your future here, visit careers.fidelityinternational.com.

Responsibilities: As a Logic design lead in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL ... Good understanding of HW / SW co design / accelerators to enhance system level performance. Collaborate with the Chip development, Unit Verification, Physical design, testgen, millcode teams to develop the feature. Pre-Silicon: Signoff the Design that meets all the functional, area and timing goals. Post Silicon: Validate the hardware functionality Required Professional and Technical Expertise: Minimum 8 20 + years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core. Experience with VLSI Design in VHDL / Verilog logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. Requirements : Masters in VLSI with demonstrated experience in the micro archite As a Logic design lead in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Good understanding of HW / SW co design / accelerators to enhance system level performance. Collaborate with the Chip development, Unit Verification, Physical design, testgen, millcode teams to develop the feature. Pre-Silicon: Signoff the Design that meets all the functional, area and timing goals. Post Silicon: Validate the hardware functionality cture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Required technical and professional expertise Minimum 8 20 + years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core. Experience with VLSI Design in VHDL / Verilog logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. Preferred technical and professional experience Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance.

8+Yrs Exp.Android device platform, Proficient In Kotlin Language knowledge of design patterns like MVP, MMVM, RxJava, and others knowledge of Android SDK, NDK, Android Studio, Gradle, and Lint

Inviting applications for the role of Principal Consultant-Data Engineer Responsibilities Strong DWH experience. Strong in one of the query languages like MS SQL, PL/SQL etc. Good understanding of best practices of cloud database technologies. Experience in Snowflake and/or dbt would be preferred while is not mandatory. Experience in CICD tools like GitHub etc. Understanding of batch orchestration tools like Apache Airflow , Control-m etc. Experience range Experience of any kind of data migration project is nice to have. Python is nice to have but DWH skills are must have . Qualifications we seek in you! Minimum Qualifications Bachelor%27s degree in computer science, information technology, or a related field. IT experience with a major focus on data warehouse/database-related projects Preferred Qualifications/ Skills You have experience in data warehousing, data modeling, and the building of data engineering pipelines. You are well versed in data engineering methods, such as ETL and ELT techniques through scripting and/or tooling. You are good at analyzing performance bottlenecks and providing enhancement recommendations you have a passion for customer service and a desire to learn and grow as a professional and a technologist. Strong analytical skills related to working with structured, semi-structured, and unstructured datasets. Collaborating with product owners to identify requirements, define desired and deliver trusted results. Building processes supporting data transformation, data structures, metadata, dependency, and workload management. In this role, SQL is heavily focused. An ideal candidate must have hands-on experience with SQL database design. Plus, Python . Demonstrably deep understanding of SQL (level: advanced) and analytical data warehouses ( Snowflake preferred). Demonstrated ability to write new code i.e., well-documented and stored in a version control system (we use GitHub & Bitbucket ) Extremely talented in applying SCD, CDC, and DQ/DV framework. Familiar with JIRA & Confluence . Must have exposure to technologies such as dbt , Apache airflow, and Snowflake . Desire to continually keep up with advancements in data engineering practices. Knowledge of AWS cloud, and Python is a plus. Must have exposure to technologies such as dbt , Apache Airflow, and Snowflake. Experience in other data platforms: Oracle, SQL Server, MDM, etc Expertise in writing SQL and database objects - Stored procedures, functions, and views. Hands-on experience in ETL/ELT and data security, SQL performance optimization and job orchestration tools and technologies e.g., dbt , APIs, Apache Airflow, etc. Experience in data modeling and relational database design Well-versed in applying SCD, CDC, and DQ/DV framework. Demonstrate ability to write new code i.e., well-documented and stored in a version control system (we use GitHub & Bitbucket) Good to have experience with Cloud Platforms such as AWS, Azure, GCP and Snowflake Good to have strong programming/ scripting skills (Python, PowerShell, etc.) Experience working with agile methodologies (Scrum, Kanban) and Meta Scrum with cross-functional teams (Product Owners, Scrum Master, Architects, and data SMEs) Excellent written, and oral communication and presentation skills to present architecture, features, and solution recommendations Global functional product portfolio technical leaders (Finance, HR, Marketing, Legal, Risk, IT), product owners, functional area teams across levels Global Data Product Portfolio Management & teams (Enterprise Data Model, Data Catalog, Master Data Management)

Required Skills Experience in Logic design / RTL coding is a must. Experience is SoC design and integration for complex SoCs is a must. Experience in Verilog/System-Verilog is a must. Experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint and CDC. Experience in Synthesis / Understanding of timing concepts is a plus. Experience in ECO fixes and formal verification. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture. Excellent oral and written communications skills. Proactive, creative, curious, motivated to learn and contribute with good collaboration skills

Responsibilities: * Ensure data accuracy through quality control processes. * Design, develop & maintain AWS data solutions using Informatica tools. Primary Skill Informatica Data quality( IDQ), CDC, AXON, Data Governanace skill

About The Role About The Role Should be good in Integration of SOC & RTL coding. Should be aware of SOC flow like Spyglass-Lint/Synthesis (DC)/CDC. Should be aware of scripting language. Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP. Should have good understanding of SoC flows. Primary Skills: VHDL, Verilog,Micro-architecture, R TL coding,CDC, Lint, Synthesis, STA,IP development , SoC integration,VCLP,scripting -Perl,Python,Shell, and Tcl. Secondary Skills: Synopsis/Cadence tool flow,ARM Coretex,DMA, DDR, SPI, I2C, UART,AHB/AXI/APB,Ethernet, USB, PCIe,Mipi CSI/DSI, LPDDR. Education B.E/B.Tech/ Any Engineering.

We are seeking a highly experienced Chief Mainframe Infra DB2 LUW professional to lead and manage support and operations of DB2 LUW, QREP, and CDC solutions in a banking environment. The role demands strong technical expertise in database administration, performance tuning, disaster recovery, and ITIL-compliant incident, change, and problem management. The successful candidate will drive operational excellence and adopt best practices to optimize performance and reduce technical debt. Key Responsibilities: Manage support and operations of DB2 LUW, QREP, and CDC database solutions implemented within the bank. Handle Incident, Change, and Problem Management for DB2 LUW, QREP, and CDC environments as per ITIL framework. Proactively monitor database performance and capacity trends, initiating improvements as needed. Apply and automate fix packs, cumulative updates, and hotfixes to ensure systems remain up-to-date. Perform regular health checks, monitoring, backup, space management, and maintenance activities. Follow up on CIRATS (Compliance, Issue, Risk) related to database systems. Manage user access and BAU (Business As Usual) database activities. Setup and maintain data replication services (QREP, CDC) ensuring data consistency and availability. Plan and execute disaster recovery and business continuity processes, including backup and point-in-time recovery. Perform database performance tuning and troubleshooting to optimize system responsiveness. Participate in a 24x7 on-call support rotation for DB2 LUW, QREP, and CDC portfolios and related applications. Provide best-in-class solutions to meet evolving business needs. Identify opportunities and lead initiatives to implement best technical practices to reduce technical debt and operational costs. Manage physical database infrastructure including storage management, access procedures, security, monitoring, and tuning. Analyze system storage capacity and recommend improvements for efficiency and scalability. Assist in designing and implementing the physical framework of databases. Support Operational DBAs with database tuning and performance optimization when required. Required Skills and Experience: Extensive experience managing DB2 LUW environments with strong operational and support background. Proven expertise with QREP (Query Replication) and CDC (Change Data Capture) technologies. Strong knowledge of ITIL processes for Incident, Change, and Problem Management. Experience in database performance tuning, capacity planning, and disaster recovery . Hands-on experience applying patches, fix packs, and automating update processes. Familiarity with backup/recovery strategies , including point-in-time recovery. Knowledge of data replication setup and maintenance . Excellent troubleshooting and root cause analysis skills. Ability to work in a 24x7 on-call rotation environment. Strong leadership and collaboration skills to work with multiple stakeholders and teams. Preferred Qualifications: Bachelor’s or Master’s degree in Computer Science, Information Technology, or related field. Certifications in DB2, ITIL, or relevant database technologies. Experience in banking or financial services domain is a plus.

Job Area :Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Responsibilities Front-End implementation of MSIP (Temp/Voltage/Security Sensors, Controllers) designs RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules. Work with functional verification team on test-plan development and debug. Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD STA. UPF writing, power aware equivalence checks and low power checks. DFT insertion and ATPG analysis for optimal SAF, TDF coverage. Provide support to SoC integration and chip level pre/post-silicon debug. Skills & Experience MTech/BTech in EE/CS with hardware engineering experience of 3+ years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.),synthesis/DFT/FV/STA. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globeand possess good communication skills.

Job Area :Engineering Group, Engineering Group > Hardware Engineering General Summary: Minimum 4 to 8 years of work experience in ASIC RTL Design, Synthesis, STA & FV Experience in Logic design/micro-architecture/RTL coding is a must. Must have hands on experience with design and integration of complex multi clock domain blocks Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, clocking/reset/debug architecture Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Work closely with the Design verification and validation teams for pre/post Silicon debug Hands on experience in Low power design is preferable Experience in Synthesis / Understanding of timing concepts for ASIC is must Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area :Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience inVerilog/System-Verilogis a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Experience creating padring and working with the chip level floorplan team is an added advantage. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

General Summary: Experience : 2 to 20 years Qualcomm's Bangalore WLAN PHY (Baseband) team is seeking VLSI Digital Design Engineers to lead IP development for the latest WiFi standards. Our WLAN PHY team, comprised of highly passionate and seasoned domain experts, prides itself on years of experience in taking WLAN PHY designs from concept to silicon independently. WLAN PHY team is responsible for delivering the end-to-end Tx/Rx DSP chains all the way from antenna samples post ADC to raw bits for upper layers and on the reverse path from raw bits to DAC. The team specializes in working with challenges of practical high-speed wireless communication systems and finding innovative solutions to counter them. The team works extensively on typical signal processing functions like filters, matrix transformations (e.g.: QR, Cholesky decomposition), channel estimation, equalization (MMSE, MRC, ML), decoders/encoders (e.g.: LDPC, Viterbi) , demodulators, FFT etc. on a day-to-day basis, and contributes to the development/ enhancement/ evaluation of signal processing algorithms to cater to new requirements. We are looking for someone as passionate as us and takes pride in their work. WiFi's ubiquity in modern times is undeniable, and the IEEE 802.11 Working Group is continually developing new standards to satisfy the growing demand for high throughput and low-latency real-time applications, such as VR and AR. Qualcomm is at the forefront of the WiFi revolution, aiming to become the global leader in WiFi chip solutions. The WLAN PHY team in Bangalore is instrumental in realizing this vision. Requirements: Looking for a candidate with 1 to 3 years of hands-on experience in micro-architecting and developing complex IPs. Expertise in digital design, VLSI concepts, and experience in creating power/area-efficient IPs across multiple clock domains are essential. Proficiency in RTL coding and familiarity with RTL QA flows such as PLDRC, CDC, and CLP (optional) is expected. Candidates should be capable of proposing design alternatives to meet area/power/performance specifications and presenting these options for review. Experience in leading, guiding, or managing junior team members is advantageous. Repeated success in taking IP designs from requirements to silicon is required. While not mandatory, having developed IPs for wireless technologies (WLAN, LTE, NR, BT, UWB, etc.) or past HLS experience would be beneficial. Skills: Must have: Proficient in Verilog RTL coding, uArch, CDC check, PLDRC, Timing constraints, Python/Perl. Experience in design/debugging complex data-path/control-path IPs. Good communication, analytical & leadership skills. Good to have: System Verilog, Visio, Knowledge of signal processing concepts/algorithms and Wi-Fi standards (802.11a/b/g/n/ac/ax), experience with HLS. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Summary We are seeking an experienced GLS Lead to drive gate level simulation activities, including power-aware GLS, formal verification, and MCP verification. The ideal candidate will lead a team of engineers, ensuring timely delivery of all verification projects and maintaining high quality standards. Key Responsibilities Lead and manage the GLS team, providing technical direction and mentorship. Plan, execute, and oversee gate level simulation (GLS) flows for complex SoC designs. Drive power-aware GLS and ensure coverage of low power verification scenarios. Oversee formal verification and MCP verification activities, ensuring completeness and correctness. Collaborate with design, DV, and other cross-functional teams to resolve issues and optimize verification strategies. Ensure all projects meet established timelines and quality benchmarks. Develop and maintain verification plans, schedules, and status reports. Continuously improve GLS methodologies and best practices. Provide regular updates to management and stakeholders. Required Qualifications Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 8+ years of experience in gate level simulation, power-aware verification, and formal verification. Proven experience leading verification teams and managing multiple projects. Strong understanding of SoC design, verification flows, and EDA tools (e.g., VCS, Questa, Verdi). Hands-on experience with UPF/CPF for power-aware verification. Excellent problem-solving, communication, and leadership skills. Preferred Qualifications Experience with MCP verification methodologies. Familiarity with scripting languages (Perl, Python, TCL). Prior experience in graphics or multimedia SoC verification. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

General Summary: 3 to 15 years of work experience in ASIC/SoC Design Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience inVerilog/System-Verilogis a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Experience creating padring and working with the chip level floorplan team is an added advantage. Excellent oral and written communications skills Proactive, creative, curious, motivated to learn and contribute with good collaboration skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

General Summary: Job Function : Camera Design Lead/Staff Candidate will be responsible for design/developing next generation SoCs sub systems for mobile phone camera . Candidate will be working on ASIC based on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI development cycle like architecture, micro architecture, Synthesis/PD interaction and design convergence. Skills/Experience 5-10 years with Masters (6 to 10 years with Bachelors) Solid experience in digital front end design for ASICsSolid Expertise in RTL microarchitecture and design coding in Verilog/SV for complex designs with multiple clock and power domainsExpertise with various bus protocols like AHB, AXI and NOC designs Experience in low power design methodology and clock domain crossing designsUnderstanding of full RTL to GDS flow to interact with DFT and PD teams Experience in Tools like Spyglass Lint/CDC checks and waiver creationExperience in formal verification with Cadence LEC Experience in mobile Multimedia/Camera design is a plus DSP /ISP knowledge is a plus. Working knowledge of timing closure is a plusExpertise in Perl, TCL language is a plusExpertise in post-Si debug is a plus Good documentation skillsAbility to create unit level test plan General Should possess good communication skills to ensure effective interaction with Engineering Management and mentor group members. Should be self-motivated and good team working attitude and need to function with little direct guidance or supervision Responsibilities Digital design and development (RTL) working in close collaboration with Multi-site leadsDeveloping the micro architecture and implementing the design using Verilog/SV. Integrate and deliver complex subsystem to SoCDesign and implement defined tasks independently. Work in close coordination with Systems, Verification, SoC team , SW team, PD & DFT teams to get the goals completed.Analyze reports/waivers or run various tools : Spyglass, 0-in, DC-Compiler, Prime time, synthesis, simulation etc Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

General Summary: Responsibilities will include to be strong designer who is able to work independent on one of the peripheral IPs come up with design and microarchitecture solutions guide/mentor juniors engage with external teams to drive/resolve cross team dependencies. Take complete responsibility of one or more project and drive that independently. Being able to make schedule estimates is a plus. People management experience is a plus Skills & Requirements needed 3-6 years of work experience in ASIC IP cores design Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering Knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB/PCIE/Ethernet preferred. Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Strong experience in micro architecting RTL design from high level design specification. Excellent problem solving skills, strong communication and team work skills are mandatory. Self-driven, needs to work with minimum supervision. Experience in System Verilog, Verilog, C/C++, Perl and Python is a plus Ability to lead a small design team. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

You have an exciting opportunity with Tessolve Semiconductor in Bangalore for the roles of RTL Design Engineer and Design Verification Engineer. For the position of RTL ASIC Engineer, you should have at least 7 years of work experience in ASIC/IP Design with expertise in Logic design and RTL design. Your responsibilities will involve IP design and integration, along with proficiency in tools such as Lint and CDC for ASIC development. Knowledge of Synthesis and understanding of timing concepts would be advantageous. Additionally, familiarity with AMBA protocols like AXI, AHB, APB, and SoC clocking/reset architecture is preferred. As a Design Verification Engineer, you are required to have 5 to 20 years of experience. You should be well-versed in IP verification using SV/UVM, SOC Verification using C/SV, and Third Party VIP Integration. Your expertise in Interconnect Protocols such as AHB, AXI, APB, SOC Interfaces like GPIO, SPI, I2C, UART, High-Speed Serial Interfaces including PCIe Gen 3/4, USB, MIPI, and Memory Interfaces like DDR or HBM I/O will be crucial. Proficiency in Coverage Closure (Code, Functional, Toggle) and tools like Synopsys VCS or Cadence Incsive is essential. Experience in Technical Documentation, Foundry Porting, and Technology Library Conversion related to Verification will be advantageous. If you meet the requirements and are interested in these positions, please share your updated CV with Gayatri Kushe at gayatri.kushe@tessolve.com or contact at 6361542656. Thank you for considering this opportunity with Tessolve Semiconductor.,

As a member of our team, you will play a key role in developing custom silicon solutions that drive the future of Google's direct-to-consumer products. You will be at the forefront of innovation, contributing to products that are cherished by millions globally. Your expertise will be instrumental in shaping the next wave of hardware experiences, delivering exceptional performance, efficiency, and integration. In your role within the platform IP team, you will be involved in designing foundation and chassis IPs for Pixel SoCs, including components such as NoC, Clock, Debug, IPC, MMU, and other peripherals. Collaboration with cross-functional teams such as architecture, software, verification, power, timing, and synthesis will be essential as you specify and deliver RTL solutions. Your problem-solving skills will be put to the test as you tackle technical challenges using innovative micro-architecture and low-power design methodologies, assessing design alternatives based on complexity, performance, and power considerations. Google's overarching mission is to organize the world's information and make it universally accessible and useful. Our team leverages the synergies between Google AI, Software, and Hardware to create exceptionally beneficial user experiences. Through our research, design, and development efforts, we strive to enhance computing speed, seamlessness, and power. Ultimately, our goal is to enhance people's lives through technology. Your responsibilities will include defining microarchitecture specifics such as interface protocols, block diagrams, data flow, and pipelines. You will engage in RTL development using SystemVerilog, conducting and debugging functional and performance simulations. Additionally, you will be responsible for performing RTL quality checks, including Lint, CDC, Synthesis, and UPF checks. Participation in synthesis, timing/power estimation, and FPGA/silicon bring-up processes will also be part of your role. Effective communication and collaboration with diverse, geographically dispersed teams will be essential for success in this position.,

Qualcomm India Private Limited is seeking a Hardware Engineer to join their Engineering Group, specifically focusing on Hardware Engineering. As a Hardware Engineer at Qualcomm, you will be at the forefront of technology innovation, contributing to the development of cutting-edge products that drive digital transformation and create a smarter, connected future. Your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other hardware components to ensure the successful launch of world-class products. To qualify for this role, you must have a Bachelor's degree, Master's degree, or PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field, along with several years of experience in Hardware Engineering. You should possess a strong background in RTL Design and Hardware Engineering, with expertise in RTL design tools such as Verilog, VHDL, and System Verilog. Additionally, familiarity with synthesis, formal verification, scripting languages (Pearl/Python/TCL), and debugging capabilities at simulation and Silicon environments is required. As a Hardware Engineer at Qualcomm, you will work collaboratively with cross-functional teams to research, design, and implement performance and power management strategies for product development. Your responsibilities will also involve designing low power/power management controller IP blocks, collaborating with technology/circuit design and verification/physical design teams, and integrating low power solutions into wireless SoC chips. Qualcomm is an equal opportunity employer and is committed to providing accommodations for individuals with disabilities throughout the application and hiring process. If you require accommodations, you can reach out to Qualcomm via email at disability-accommodations@qualcomm.com or by phone. Additionally, Qualcomm expects its employees to adhere to all applicable policies and procedures, including the protection of confidential information. Please note that Qualcomm does not accept unsolicited resumes or applications from staffing and recruiting agencies. If you have any inquiries about this Hardware Engineer role, you can contact Qualcomm Careers for more information.,