143 Cdc Jobs

Good hands on in Solution Manager 7.2 Implementation & Support Should have Configured SLD, LMDB, Managed System setup, Template Maintenance, Alerting & Monitoring Expertise in SAP Focused Insights, Focused Build and Focused Run Must have SAP CHARM end to end setup/configuration hands on skill set. Should have Configured Early Watch Alert (EWA), Data Volume Management (DVM), Business Process Monitoring (BPM), Job Monitoring & CDC (Cross Database Comparison) Very good knowledge on Transport imports and Release management activities using CHARM Must have worked on Solution Documentation Should have worked on creating dashboards using FI, UxMon etc. Should have worked on Test suite Management, Project and Process Management Expert knowledge in SolMan Integration with 3rd Paty tools Must be aware to connect ABAP, NON-ABP and HANA system with SolMan Good understanding and experience in customizing ITSM and CHARM based on customer needs Should have configured PO, BO, DS and Web dispatcher monitoring Must have worked on DAA installation and connecting to SolMan Should have hands on in complete setup of Agent on Fly concept for high availability systems Should have worked on SolMan upgrade. Must have to work independently by understanding the new customer requirements Good Communication skills.

Good hands on in Solution Manager 7.2 Implementation & Support Should have Configured SLD, LMDB, Managed System setup, Template Maintenance, Alerting & Monitoring Expertise in SAP Focused Insights, Focused Build and Focused Run Must have SAP CHARM end to end setup/configuration hands on skill set. Should have Configured Early Watch Alert (EWA), Data Volume Management (DVM), Business Process Monitoring (BPM), Job Monitoring & CDC (Cross Database Comparison) Very good knowledge on Transport imports and Release management activities using CHARM Must have worked on Solution Documentation Should have worked on creating dashboards using FI, UxMon etc. Should have worked on Test suite Management, Project and Process Management Expert knowledge in SolMan Integration with 3rd Paty tools Must be aware to connect ABAP, NON-ABP and HANA system with SolMan Good understanding and experience in customizing ITSM and CHARM based on customer needs Should have configured PO, BO, DS and Web dispatcher monitoring Must have worked on DAA installation and connecting to SolMan Should have hands on in complete setup of Agent on Fly concept for high availability systems Should have worked on SolMan upgrade. Must have to work independently by understanding the new customer requirements Good Communication skills.

Good hands on in Solution Manager 7.2 Implementation & Support Should have Configured SLD, LMDB, Managed System setup, Template Maintenance, Alerting & Monitoring Expertise in SAP Focused Insights, Focused Build and Focused Run Must have SAP CHARM end to end setup/configuration hands on skill set. Should have Configured Early Watch Alert (EWA), Data Volume Management (DVM), Business Process Monitoring (BPM), Job Monitoring & CDC (Cross Database Comparison) Very good knowledge on Transport imports and Release management activities using CHARM Must have worked on Solution Documentation Should have worked on creating dashboards using FI, UxMon etc. Should have worked on Test suite Management, Project and Process Management Expert knowledge in SolMan Integration with 3rd Paty tools Must be aware to connect ABAP, NON-ABP and HANA system with SolMan Good understanding and experience in customizing ITSM and CHARM based on customer needs Should have configured PO, BO, DS and Web dispatcher monitoring Must have worked on DAA installation and connecting to SolMan Should have hands on in complete setup of Agent on Fly concept for high availability systems Should have worked on SolMan upgrade. Must have to work independently by understanding the new customer requirements Good Communication skills.

Good hands on in Solution Manager 7.2 Implementation & Support Should have Configured SLD, LMDB, Managed System setup, Template Maintenance, Alerting & Monitoring Expertise in SAP Focused Insights, Focused Build and Focused Run Must have SAP CHARM end to end setup/configuration hands on skill set. Should have Configured Early Watch Alert (EWA), Data Volume Management (DVM), Business Process Monitoring (BPM), Job Monitoring & CDC (Cross Database Comparison) Very good knowledge on Transport imports and Release management activities using CHARM Must have worked on Solution Documentation Should have worked on creating dashboards using FI, UxMon etc. Should have worked on Test suite Management, Project and Process Management Expert knowledge in SolMan Integration with 3rd Paty tools Must be aware to connect ABAP, NON-ABP and HANA system with SolMan Good understanding and experience in customizing ITSM and CHARM based on customer needs Should have configured PO, BO, DS and Web dispatcher monitoring Must have worked on DAA installation and connecting to SolMan Should have hands on in complete setup of Agent on Fly concept for high availability systems Should have worked on SolMan upgrade. Must have to work independently by understanding the new customer requirements Good Communication skills.

Job Details: : Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design. Participates in the definition of architecture and microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Works with IP providers to integrate and validate IPs at the SoC level. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: A bachelors degree in electrical/computer engineering, Computer Science or related field with 6+ years of experience (or) a masters degree with 4+ years of experience. Preferred Qualification: Relevant experience with skills in SoC flows, RTL integration and Globals (Clocking, Boot/Reset/Fabrics, DfD, Fuse, etc). Experience in subsystem design and HSIO protocols such as PCIe, UCIe is a plus. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Create and support innovative Design Methodologies by leveraging feedback from our EDA and Digital IP teams. Integrate Methodologies into the development infrastructures of the Digital IP teams and demonstrate successful results. Support and maintain our regression infrastructure to manage changes and revise methodologies regularly. Test a range of Digital IPs through our Methodologies centered around Synopsys EDA tools. Collaborate with various teams to improve methodologies, enhancing both team and customer experiences. Develop and manage infrastructures, processes, methodologies, and checklists for the SG Digital IP Controllers. The Impact You Will Have: Enhance the efficiency and effectiveness of Digital IP development processes. Ensure high-quality and robust Digital IP products through rigorous methodology testing. Improve customer satisfaction by delivering superior Digital IP solutions. Drive innovation in design methodologies, contributing to Synopsys leadership in the industry. Facilitate seamless integration of methodologies into development infrastructures, optimizing workflows. Support the continuous improvement of regression infrastructures, ensuring up-to-date methodologies. What You'll Need: Bachelor's or Master's degree in electronics or electrical engineering or equivalent from reputed universities. 6-10 years of relevant experience in ASIC/SoC/IP Methodology. Proficiency in Synopsys implementation and infrastructure tools (coreConsultant, coreAssembler, SpyGlass/VC-SpyGlass, Fusion Compiler/Design Compiler, Prime Time, Formality, TestMax Manager, TCM, Verdi, VCS). Familiarity with multi-clock designs and understanding of Clock-Domain-Crossing principles. Proficiency in scripting languages (TCL, Perl, Python).

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: 15+ years of experience in SoC design Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. 12+ years of experience with a Bachelor's/ Masters degree in Electrical/ Electronics engineering

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: 12+ years of experience in SoC design Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. 12+ years of experience with a Bachelor's/ Masters degree in Electrical/ Electronics engineering

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm Chennai is looking for a VLSI engineers who is passionate in to work with cross-functional engineering teams . In this position, the engineer will be involved in all stages of the design and development cycles Strong knowledge of digital design and SOC architecture. Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C Experience in HDL such as Verilog Knowledge of ARM/DSP CPU architecture, High Speed Peripherals like USB2/3, PCIE or Audio/Multimedia Familiarity with Power-aware Verification, GLS, Test vector generation is a plus Exposure to Version managers like Clearcase/perforce Scripting language like Perl, Tcl or Python Analytical and Debugging skills 2-4 yrs experience Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Bachelors / Masters degree in electrical or electronics engineering with 2 - 4 yrs of experience is preferred

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Experience creating padring and working with the chip level floorplan team is an added advantage. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: 3 to 15 years of work experience in ASIC/SoC Design Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Experience creating padring and working with the chip level floorplan team is an added advantage. Excellent oral and written communications skills Proactive, creative, curious, motivated to learn and contribute with good collaboration skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 3+ years experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications 2-9 years of experience in SoC design Educational 2+ years of experience with a Bachelors/ Masters degree in Electrical engineering

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Minimum 4 to 8 years of work experience in ASIC RTL Design, Synthesis, STA & FVExperience in Logic design/micro-architecture/RTL coding is a must.Must have hands on experience with design and integration of complex multi clock domain blocksExperience in Verilog/System-Verilog is a must.Should have knowledge of AMBA protocols - AXI, AHB, APB, clocking/reset/debug architectureHands on experience in Multi Clock designs, Asynchronous interface is a must.Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.Work closely with the Design verification and validation teams for pre/post Silicon debugHands on experience in Low power design is preferableExperience in Synthesis / Understanding of timing concepts for ASIC is must Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must . Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must . Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required . Hands on experience in Multi Clock designs, Asynchronous interface is a must . Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3-6 yrs of experience

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum of 5+ years experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Skills & Experience MTech/BTech in EE/CS with 7+ years of ASIC design experience. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA Good understanding of DDR families (LP/PC) and generations (DDR2/3/4/5/6) is added advantage. Understanding of protocols like AHB/AXI/ACE/CHI is desirable. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globe and possess good communication skills. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Hands on experience in Low power SoC design is required. Responsibilities Mirco architecture & RTL development and its validation for linting, clock-domain crossing and DFT rules. Work with functional verification team on test-plan development and waveform debugs at core, sub-system, SoCs levels. Hands on experience in constraint development and timing closure. UPF writing, power aware equivalence checks and low power checks. Support performance debugs and address performance bottle necks. Provide support to sub-system, SoC integration and chip level debug. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum of 5+ years experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: Job Function/General Responsibilities Modeling and Minimizing SOC power for Games/ML/UI/Image-processing Graphics workloads Silicon power measurement and modeling CPU, memory and other SOC components of SOC for Graphics workloads Experience in GPU DCVS algorithm is a plus Knowledge of Windows OS is a plus. Critical "Must Have" skills/experience for role Bachelor's degree or equivalent in Electrical or Computer Engineering, Computer Science, or related field. 15+ years Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 8+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 7+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 6+ years of Systems Engineering or related work experience. Preferred skills/experience for role: Master's Degree or PhD in Electrical or Computer Engineering, Computer Science, or related field. 2+ years relevant GPU experience (either external or internal). 2+ years of work experience in a role requiring interaction with senior leadership (e.g., Director level and above). 1+ years in a technical leadership role with or without direct reports (only applies to positions with direct reports Education Text Bachelor's degree in Computer Science, Electrical Engineering, Information Systems, or related field. Keywords Power, SOC, DCVS, DVFS

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm's Bangalore WLAN PHY (Baseband) team is seeking VLSI Digital Design Engineers to lead IP development for the latest WiFi standards. Our WLAN PHY team, comprised of highly passionate and seasoned domain experts, prides itself on years of experience in taking WLAN PHY designs from concept to silicon independently. WLAN PHY team is responsible for delivering the end-to-end Tx/Rx DSP chains- all the way from antenna samples post ADC to raw bits for upper layers and on the reverse path from raw bits to DAC. The team specializes in working with challenges of practical high-speed wireless communication systems and finding innovative solutions to counter them. The team works extensively on typical signal processing functions like filters, matrix transformations (e.g.QR, Cholesky decomposition), channel estimation, equalization (MMSE, MRC, ML), decoders/encoders (e.g.LDPC, Viterbi) , demodulators, FFT etc. on a day-to-day basis, and contributes to the development/ enhancement/ evaluation of signal processing algorithms to cater to new requirements. We are looking for someone as passionate as us and takes pride in their work. WiFi's ubiquity in modern times is undeniable, and the IEEE 802.11 Working Group is continually developing new standards to satisfy the growing demand for high throughput and low-latency real-time applications, such as VR and AR. Qualcomm is at the forefront of the WiFi revolution, aiming to become the global leader in WiFi chip solutions. The WLAN PHY team in Bangalore is instrumental in realizing this vision. : Looking for a candidate with 1 to 3 years of hands-on experience in micro-architecting and developing complex IPs. Expertise in digital design, VLSI concepts, and experience in creating power/area-efficient IPs across multiple clock domains are essential. Proficiency in RTL coding and familiarity with RTL QA flows such as PLDRC, CDC, and CLP (optional) is expected. Candidates should be capable of proposing design alternatives to meet area/power/performance specifications and presenting these options for review. Experience in leading, guiding, or managing junior team members is advantageous. Repeated success in taking IP designs from requirements to silicon is required. While not mandatory, having developed IPs for wireless technologies (WLAN, LTE, NR, BT, UWB, etc.) or past HLS experience would be beneficial. Skills: Must have: Proficient in Verilog RTL coding, uArch, CDC check, PLDRC, Timing constraints, Python/Perl. Experience in design/debugging complex data-path/control-path IPs. Good communication, analytical & leadership skills. Good to have: System Verilog, Visio, Knowledge of signal processing concepts/algorithms and Wi-Fi standards (802.11a/b/g/n/ac/ax), experience with HLS. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Experience in micro architecture and requirements/implementation for automotive designs (focused on functional safety) and their Safety Analysis work products like concept FMEDA, DFA, DFMEA, FTA, FMEDA, etc. including FuSa compliant IP development and third-party IP compliance/deliverables/DIA. Responsibilities shall include the following Developing a system level safety concepts and requirements for ADAS and IVI use cases with customer implementations in mind and to integrate Qualcomms hardware in leading Automotive OEM and Tier 1 safety critical systems. Work in collaboration with 3rd party, Customer, and Automotive Stack suppliers, Hardware component suppliers (PMIC, DRAM, Sensor, etc) to ensure all aligned customer system level requirements are met Work with IP and SoC teams on the implementation of Technical Safety Concepts (TSCs) on Qualcomms Snapdragon automotive hardware. Work with various technology teams on architectural features that would enable targeted safety levels (ASIL B to ASIL D, depending upon the technology team and system level requirements) to meet customer targets Conducting safety analyses, both quantitative and qualitative, fault campaigns on automotive hardware designs and identify areas of improvement. Responsibilities will include leading functional safety related activities for SoC development and ensure ISO 26262 compliance with respect to SoC architecture, development processes and work products. Work closely with SoC Design and IP teams, Software team, Quality teams, the functional safety manager(s) as well as customers to ensure the functional safety process is executed and documented. Working with vendors and partners to ensure functional safety requirements are fulfilled by the components that they provide Work with internal and external functional safety assessors to ensure compliance with ISO 26262 Create functional safety collateral for customers viz. Functional Safety Manual, Safety Analyses Reports, dedicated application notes etc. Supporting customer assessments of our safety features and recommending HW and SW based solutions that meet overall system targets. Working closely with customers and supporting them on various functional safety related aspects Minimum Qualifications Bachelors degree in engineering, Information Systems, Computer Science, or related field. 8+ years Systems Engineering, SoC Integration, Verification, or related work experience. Collaborative work experience with good communication skills involving customers, vendors, and internal development teams. Structured problem-solving capability and ability to work with teams on root cause analyses. Preferred Qualifications 5+ years Automotive experience and familiarity with Safety work products, experience with Functional Safety Hardware and/or Software development in semiconductor industry meeting IS0 26262/ IEC 61508 standards. Prior automotive experience in ADAS and self-driving systems preferred. System level Functional safety analysis experience on Hardware/Software components integration preferred SoC/IP integration or verification with good understanding of SoC Architecture and IP design experience preferred Management Tools and establishing traceability for functional safety requirements e.g. DOORS, etc. Familiarity with Failure Modes and Effect Analysis (FMEA) and Fault Tree Analysis (FTA) is required experience using tools to perform FMEA, FTA preferred Familiarity with hardware failure rate calculation (FMEDA) experience using Siemens 29500 and/or IEC 62380 preferred Relevant Safety Certification is desired e.g. CFSE, CFSP

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: General Summary Join Qualcomms Wireless IP team to design and develop cutting-edge RTL for next-generation cellular and Wi-Fi modem IPs used in mobile, wearable, and IoT platforms. You will work on high-performance, low-power digital designs across the full VLSI development cycle"”from architecture and micro-architecture to RTL implementation and SoC integration. This role offers the opportunity to collaborate with global teams and contribute to market-leading wireless solutions. Key Responsibilities Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog. Develop micro-architecture specifications and deliver high-quality, synthesizable RTL. Integrate complex subsystems into SoC environments and support design convergence. Collaborate with system architects, verification, SoC, software, DFT, and physical design teams. Apply low-power design techniques including clock gating, power gating, and multi-voltage domains. Analyze and optimize for performance, area, and power. Ensure protocol compliance and performance of interconnects, buses (AXI, AHB, APB), and bridges. Conduct CDC and lint checks using tools like Spyglass and resolve waivers. Participate in post-silicon debug and bring-up activities. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Preferred Skills & Experience 2"“15 years of experience in digital front-end ASIC/RTL design. Strong expertise in Verilog/SystemVerilog RTL coding and micro-architecture development. Familiarity with wireless protocols such as IEEE 802.11 (a/b/g/n/ac/ax/be), LTE, or 5G NR is highly desirable. Solid understanding of bus protocols (AXI, AHB, APB) and bridge logic. Experience with wireless modem IPs or similar high-performance digital blocks is a plus. Familiarity with low-power design methodologies and CDC handling. Hands-on experience with tools like Spyglass, 0-in, Design Compiler, PrimeTime, and simulation environments. Exposure to post-silicon debug and SoC integration challenges. Strong documentation and communication skills. Self-motivated with a collaborative mindset and ability to work with minimal supervision. Minimum Qualifications Bachelors or Masters degree in Electronics, VLSI, Communications, or related field. Proven experience in RTL design and SoC development.

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: Organization overview: Qualcomm is a key enabler for the XR eco-system with a dominant market share. We build custom SoCs and technologies that are at the heart of existing and emerging XR products. Qualcomm XR Systems organization is responsible for architecture definition of Qualcomms next generation XR SoCs. Our portfolio of SoC offerings serve a broad range of XR products covering Mixed Reality, Augmented Reality and AI Glass product families. The span of technologies that go into these products and SoCs include high resolution immersive displays, perception features that are bulit on computer vision and deep learning technology, highly efficient DSP processors, dedicated deep learning accelerators, graphics engines supporting high resolution and high frame rate rendering and reprojection, multimedia processing engines (audio, video, imaging,..), CPUs and SoC infrastructure that ensures efficient and secure processing, as well as very low power architecture features such as power islands and power rail isolation, sleep modes etc. We are scaling up our operations!! We are looking for engineers with background in diverse areas including architecture and micro architecture definition, design and verification of IPs and SoCs. People who have experience in areas such as SoC architecture, networks on chip, virtual memory, on-chip and off-chip memory subsystems, security architecture, CPUs, etc, also development of IPs such as camera, video, GPU, DSPs, deep learning accelerators and neural signal processors (NSP), peripherals and interfaces such as PICe, SPI etc. Also, people with strong background on pre silicon and post silicon power estimation and optimization, performance estimation, power architecture design will be highly encouraged. We have openings at senior as well as junior job levels. We are keenly interested in you if you are someone who has gained expertise in your specific domain which could be one or more of the areas mentioned above and are excited to take the next step in your career to become architects of the SoCs that will shape the future generations of XR products!! Apart from a rewarding career and growth prospects, the organization offers a unique opportunity to learn from a diverse set of experts working collaboratively under the same roof, towards a common goal. Job Overview Qualcomm's XR Systems team is seeking system architects who will work on defining the next generation SoC architectures, enabling the future of Augmented Reality / Virtual Reality / Mixed Reality applications. Responsibilities of successful candidates may span one or more of the following areas: Working with lead XR OEMs and QCs customer-facing teams to understand end to end use cases Researching the product family roadmap to align internal IP and SoC architecture roadmap Collaborating with colleagues in the architecture team and across technology, IP and SoC teams with diverse expertise Exploring architectures for power efficient and performant mapping of use cases on future SoCs and coming up with architecture proposals Defining and optimizing use case data flows Use case power modeling, estimation and optimization Working with SoC design, and validation teams to ensure that the use case power and performance KPIs are met. Minimum Qualifications Bachelors degree in Electrical Engineering, Information Systems, Computer Science, or related field, and project experience in architecture/micro-architecture Experience (1 - 10 years) in areas covering at least one of the followingIP and SOC design, DV, micro architecture, architecture, camera, video, GPU, DSP, NSP, CPU, security, NOCs and DRAM controller subsystems, power architecture and power and performance estimation and optimization. Excellent problem solving and communication skills Preferred Qualifications Masters and/or PhD degree in Electrical Engineering, Information Systems, Computer Science Experience with Mixed & Augmented reality system design, constraints, and trade-offs Deep understanding of system architecture aspects such as NOCs, DRAM controller performance issues, power domains and sleep modes of memories, IPs and cores. Proven experience in conducting architectural trade-offs, power/performance analysis and/or SW-HW trade-offs Experience with system level modeling (performance and/or power) Proficiency in scripting languages such as python, perl, shell etc. Keywords Camera, GPU, CPU, SOC, SoC architecture, NOC, DDR subsystem, LPDDR IP, caches, security, virtual memory, development, RTL design, Computer vision, Artificial Intelligence, ML, DSP, AR, VR, MR, XR Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum 4 to 6 years of work experience in ASIC RTL Design Experience in Logic design/micro-architecture/RTL coding is a must. Must have hands on experience with design and integration of complex multi clock domain blocks Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, clocking/reset/debug architecture Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of Automotive System Designs, Functional Safety, Memory controller designs and microprocessors is an added advantage Work closely with the Design verification and validation teams for pre/post Silicon debug Hands on experience in Low power design is preferable Experience in Synthesis / Understanding of timing concepts for ASIC is must

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. General Summary: Responsibilities Front-End/Digital design implementation of Sensor/Mixed signal digital blocks RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules. Work with SoC power management team for power sequencing requirements and system level considerations Work with functional verification team on test-plan development and debug. Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD STA. UPF writing, power aware equivalence checks and low power checks. DFT insertion and ATPG analysis for optimal SAF, TDF coverage. Provide support to SoC integration and chip level pre/post-silicon debug. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. Skills & Experience MTech/BTech in EE/CS with hardware engineering experience of 8+ years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globe and possess good communication skills.