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ASIC Design Engineer - Design & Timing Constraints

ASIC Design Engineer - Design & Timing Constraints

Cisco

7 - 12 years

11 - 16 Lacs

bengaluru

Posted:2 days ago| Platform:

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Skills Required

perl tcl asic sta verilog physical design static timing analysis digital design vhdl rtl design formal verification fpga system verilog tcm synthesis python cdc primetime rtl uvm asic design cadence dft timing closure spyglass synopsys fc dc

Work Mode

Work from Office

Job Type

Full Time

Job Description

Your Impact

You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, youll contribute to developing next-generation networking chips.

Responsibilities include:

Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
Option to also do block level RTL design or block or top-level IP integration.
Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
Creating fullchip clocking diagrams and related documentation.

Minimum Qualifications

Bachelors Degree in Electrical or Computer Engineering with 7+ years of ASIC or related experience or Masters Degree in Electrical or Computer Engineering with 5+ years of ASIC or related experience
Experience with block/full chip SDC development in functional and test modes.
Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus
Understanding of related digital design concepts (eg. clocking and async boundaries)
Experience with synthesis tools (eg. Synopsys DC/DCG/FC), Verilog/System Verilog programming

Preferred Qualifications

Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence)
Experience with Spyglass CDC and glitch analysis
Experience using Formal Verification: Synopsys Formality and Cadence LEC.
Experience with scripting languages such as Python, Perl, or TCL

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ASIC Design Engineer - Design & Timing Constraints