Posted:23 hours ago|
Platform:
Work from Office
Full Time
We''re seeking a talented ASIC engineer with a proven track record in high-performance products, ready to make a significant impact in the industry. Join us and push the boundaries of what''s possible!Your ImpactYou are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, youll contribute to developing next-generation networking chips.
*Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
*Option to also do block level RTL design or block or top-level IP integration.
*Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
*Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
*Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
*Creating fullchip clocking diagrams and related documentation.
*Bachelors Degree in Electrical or Computer Engineering with 7+ years of ASIC or related experience or Masters Degree in Electrical or Computer Engineering with 5+ years of ASIC or related experience
*Experience with block/full chip SDC development in functional and test modes.
*Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus
*Understanding of related digital design concepts (eg. clocking and async boundaries)
*Experience with synthesis tools (eg. Synopsys DC/DCG/FC), Verilog/System Verilog programmingPreferred Qualifications
*Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence)
*Experience with Spyglass CDC and glitch analysis
*Experience using Formal Verification: Synopsys Formality and Cadence LEC.
*Experience with scripting languages such as Python, Perl, or TCL
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