1440 Uvm Jobs

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SE NIOR SILICON DESIGN ENGINEER THE ROLE (SOC Verification Engineer: GDP DV ): Work on SOC level verification activities for GDP (PCIE,USB,Ethernet,I2C,I3C,Uart,SPI) and subsystem or signature IP's in the complex SOC. He will be responsible for verifying and integration. Add on responsibility SOC Integration after having co-ordination with IPs, SOC (Design, DFT & PD) teams. To take complete IP integration responsibility, including the deployment verification. Understand spec, interact with customer, team members, lead and come up with testplan, code testcases, checkers, UVM agents, scoreboards and assertions. THE PERSON: Engineer with strong self-driving ability. Need excellent communication skills (both written and oral) Strong problem-solving skills, go to person for UVM coding, Testcase coding, checkers and assertions. KEY RESPONSIBILITIES: Understanding Ips like (PCIE,USB,Ethernet,I2C,I3C,UART,SPI) IP deployment to complex SOCs and get the integration testing done. Testcase coding, Debugging issues, regressions, UVM agent coding, checkers coding, scoreboard coding and Assertions coding. PREFERRED EXPERIENCE: Knowledge of High speed peripheral (PCIE,USB,Ethernet) and Low speed peripherals (I2C,I3C,UART,SPI) Expertise in IP, Subsystem and SOC Verification with specialization in Integration, verification tools Strong hands-on experience in different SOC Verification activities, UVM, System Verilog, kv, X86, C++, HW/SW co-verification, Test plan review, Debug/triage, Coverage, Strong Problem Solving, Automation and Debugging Skills, System bus protocol understanding including some of the common IPs like ACE, CHI, AXI, PCIe, DDR, memory controller etc. Comfortable with design/verification tools and flows like VCS, Verdi, SOC Connectivity, SV assertions, HW-SW co-simulations, UPF/CPF flows etc. Strong understanding of System integration, Make file flow, Verification Methodologies, Boot up sequence. JIRA based project management is a plus. ACADEMIC CREDENTIALS: BE/B.Tech/ME/MTECH/MS or equivalent in ECE/EEE/CSE 5-10 years of strong DV experience in IP, Sub System & SOC Verification, IP deployment/integration. #LI-SR4 Benefits offered are described: . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

Role Overview: As a Junior ASIC Verification Engineer at Kinara, you will be a key member of the dynamic team responsible for leading and executing verification efforts for complex ASIC designs. Your role will involve developing and maintaining verification plans, testbenches, and test cases to ensure the quality and reliability of our products. You will design and implement SystemVerilog/UVM-based verification environments, create and execute test cases, and write testplans at unit or SOC level. Key Responsibilities: - Develop and maintain verification plans, testbenches, and test cases for ASIC designs. - Design and implement SystemVerilog/UVM-based verification environments. - Create and execute test cases to verify functionality, performance, and compliance with specifications. - Write testplans, testcases at unit or SOC level. Qualifications Required: - Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. - Expertise in SystemVerilog, C, C++ languages. - Experience with verification tools such as VCS, QuestaSim, or similar is helpful. - Excellent problem-solving and debugging skills. - Strong communication and teamwork abilities. Additional Details: Kinara fosters an environment of innovation where technology experts and mentors work together to tackle exciting challenges. The team at Kinara values shared responsibilities and diverse perspectives, making it an ideal place to work. Join us and be a part of our journey towards creating a smarter, safer, and more enjoyable world through high-performance AI solutions embedded in edge devices. Make your mark and become a part of the Kinara team!,

Role Overview: As a Hardware Engineering Intern at Google, you will be part of a team shaping the future of Google Cloud Silicon, including TPUs, Arm-based servers, and network products. You will collaborate with hardware and software architects and designers to architect, model, analyze, define, and design next-generation Cloud Silicon. Your responsibilities will be dynamic and multi-faceted, focusing on product definition, design, and implementation. You will work closely with Engineering teams to achieve the optimal balance between performance, power, features, schedule, and cost. Key Responsibilities: - Work with hardware and software architects and designers to architect, model, analyze, define, and design next-generation Cloud Silicon - Collaborate with Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost - Have responsibilities in areas such as product definition, design, and implementation - Contribute to shaping the future of Google Cloud Silicon, including TPUs, Arm-based servers, and network products Qualifications Required: - Currently pursuing a PhD degree in Computer Engineering, Computer Science, Electronics and Communication Engineering, Electrical Engineering, or a related technical field - Experience in Hardware System Integration, Signal and Power Integrity, System Validation, Wireless Communications, Product Design, Computer Architecture, Digital Design Verification, Digital Circuits, ASIC Physical Design, FPGAs, Embedded Systems, Memory Systems - Experience in programming languages such as C++, Python, Verilog, UVM, Synopsys, and Cadence tools - Experience with wireless communication interfaces and sensors - Experience with performance modeling tools, C++, Python, Silicon design tools in Front End/Design Verification/Physical Design - Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies, computer architecture, linear algebra, ML/DL background - Knowledge of high performance and low power design techniques - Currently attending a degree program in India and available to work full time for 12 weeks outside of university term time Additional details of the company: Google is an engineering company that prioritizes security, efficiency, and reliability. The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services. Their end users are Googlers, Cloud customers, and people who use Google services around the world. The company focuses on developing the latest Cloud Si products and running a global network while driving towards shaping the future of hyperscale computing. Google engineers work on various technical challenges to make an impact on millions of users and revolutionize technology. (Note: The section "Additional details of the company" has been included based on the information provided in the job description),

Role Overview: As an experienced SoC Verification Engineer at Enphase Energy in Bangalore, India, you will be working on the next generation Control ASIC in 22nm technology. Your role will involve ensuring the verification of the new SOC design, setting the verification methodology, and collaborating with internal/contract verification resources, IP designers, and Full Chip RTL engineers to verify the RTL developed by Enphase engineers and 3rd party IP. Your deep understanding and experience in SoC architecture and verification will be crucial to the success of the project. Key Responsibilities: - Verify the new SOC design and set the verification methodology - Collaborate with internal/contract verification resources, IP designers, and Full Chip RTL engineers - Ensure verification of RTL developed by Enphase engineers and 3rd party IP - Utilize hands-on experience with UVM using SystemVerilog and coverage-driven verification methods - Apply formal verification methods for IP/SoC functional verification - Demonstrate knowledge of RTL verification methods, gate-level verifications, and mixed signal methodologies - Use specific experience in verifying the ARM CM4 and surrounding IP, such as AHB, AXI, RAM and ROM controllers, and DMA controllers - Apply experience in verifying high-speed and high-accuracy analog systems with a mixed signal methodology - Bring complex SOCs into production Qualifications Required: - At least 15+ years of proven experience in SoC verification - Deep understanding and experience in SoC architecture and verification - Experience with ARM CM4 and surrounding IP like AHB, AXI, RAM and ROM controllers, and DMA controllers - Hands-on experience with UVM using SystemVerilog and coverage-driven verification methods - Knowledge of formal verification methods for IP/SoC functional verification - Familiarity with RTL verification methods, gate-level verifications, and mixed signal methodologies - Ability to bring complex SOCs into production - Hands-on experience with RISC-V verification will be an added advantage (Note: Additional details about the company were not explicitly mentioned in the provided job description.),

**Job Description** **Role Overview:** In this role, you will work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. **Key Responsibilities:** - Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios. - Identify and write all types of coverage measures for stimulus and corner-cases. - Debug tests with design engineers to deliver functionally correct design blocks. - Measure to identify verification holes and to show progress towards tape-out. - Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM). **Qualifications Required:** - Bachelor's degree in Electrical Engineering or equivalent practical experience. - 4 years of experience in Verification, verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs. - Experience in verification and debug of IP/subsystem/SoCs in the Networking domain such as packet processing, bandwidth management, congestion control desired. - Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems). **About the Company:** The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.,

Role Overview: As an Individual contributor in the field of VLSI Frontend, Backend, or Analog design, you will be responsible for executing internal projects or small tasks of customer projects under minimal supervision from the Lead. Your main task will involve working on any one task of RTL Design/Module in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff. Key Responsibilities: - Analyse and complete the assigned task in the defined domain(s) successfully on-time with minimal support from senior engineers - Ensure quality delivery as approved by the senior engineer or project lead - Deliver clean modules that are easy to integrate at the top level - Ensure functional specifications and design guidelines are met without deviation - Document tasks and work performed - Meet project timelines as provided by the team lead/program manager - Support team members in their tasks and perform additional tasks if necessary - Plan approaches towards repeated work by automating tasks to save design cycle time - Participate in technical discussions Qualifications Required: - Bachelors or Masters degree in Electrical/Electronics Engineering or related field - 2-3 years of AMS Verification experience - Strong knowledge of analog and digital design fundamentals - Experience with simulation and verification tools like Cadence Spectre, Xcelium, AMS Designer, or similar - Familiarity with scripting languages (Python, Perl, or Tcl) for automation - Understanding of UVM or other verification methodologies is a plus - Experience in modeling using Verilog-AMS or SystemVerilog - Prior work on silicon-proven IPs or SoCs - Knowledge of power-aware verification or low-power design techniques About the Company: UST is a global digital transformation solutions provider with over 30,000 employees in 30 countries. UST partners with clients from design to operation, embedding innovation and agility into their clients" organizations. With deep domain expertise and a future-proof philosophy, UST aims to make a real impact through transformation, touching billions of lives in the process.,

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Physical Place and Route. Experience: 3-5 Years.

Dear Candidate We have immediate job openings for Design verification openings Exp : 3-10 years Location : Bangalore NP : less than 45 days Job details : Develop and maintain UVM-based verification environments. Define and review verification test plans with architecture and design teams. Perform design verification using directed and constraint-random tests. Maintain regression runs and debug test failures with designers. Report and analyze verification coverage metrics. Drive verification to achieve full coverage goals. Own verification of IP blocks, sub-systems, and top-level environments. Thanks Gayathri

Dear Candidate We have immediate job openings for Design verification openings Exp : 3-10 years Location : Bangalore NP : less than 45 days Job details : Develop and maintain UVM-based verification environments. Define and review verification test plans with architecture and design teams. Perform design verification using directed and constraint-random tests. Maintain regression runs and debug test failures with designers. Report and analyze verification coverage metrics. Drive verification to achieve full coverage goals. Own verification of IP blocks, sub-systems, and top-level environments. Thanks Gayathri

Job Specs : Expertise in Digital Verification Expertise in Functional Verification Expertise in SOC / IP Verification Expertise in working on system Verilog assertions & test benches Expertise in working on OVM / UVM / VMM based verification flow Expertise in working on ARM processor Expertise in working on AMBA bus protocols (AXI, AHB, APB) Expertise in CXL or PCIe Protocol Verification Expertise in simulation tools (VCS, ModelSim, Questa) Expertise in driving Verification Strategy, writing Test Plan, developing Test Bench, Test cases. Expertise in analysing Code Coverage, Functional Coverage and Assertions. Expertise in verification of complex SoCs. Expertise in Test Plan creation and Verification technologies like Code Coverage, Functional coverage, assertion based verification. Expertise in Verification of complex datapath, DSP based ASICs Expertise in MAC Protocol: USB, WiFi , Bluetooth , PCIe is mandatory Good knowledge in gate-level simulation, and Scripting languages like Python, TCL Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan are the preferred work locations Preferred resources with valid regional work permit.

The Core design and verification team is responsible for development of High performance and Ultralow power x86 microprocessor core . The role provides a unique opportunity to work at the micro-architectural level of the next-gen Core, with exposure to designs that defines the next wave of client (laptops / ultra-books / think-clients) and custom designs. The multi-billion gate complexity and high-frequency (GHz) design development gives the learning experience of the latest and greatest design and verification methodologies, using cutting edge advanced technology nodes. THE PERSON: Candidates should have solid track record of working on complex designs with hands on experience on architecting and developing test-bench, test-bench components, test-planning and execution of testplan, coverage development and closure. Candidate should have working experience with global teams spread across different geography and time-zones. KEY RESPONSIBILITIES: ASIC design verification experience 6 to 10 years. Verification of high performance x86-core ISA features Architecting and development of testbench, test-bench components for high performance Cache, x86 ISA features, clock/reset/power features of processor. Development of detailed test plans and driving the execution of test plan, including functional coverage. Understanding the existing test bench setup and look for opportunities to improve the existing test bench. Adhering to coding guideline practices, develop and implement code review process. Collaborate with global design verification teams and drive effectively the execution of the verification plans. Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion. PREFERRED EXPERIENCE: Strong understanding the design and verification life cycle. Hands on verification experience with C/C++/SystemVerilog testbench development. Hands on experience with coverage planning, coding and coverage closure. Experience with x86, ARM or any other industry standard microprocessor ISA. Experience with Cache, Coherency and Data-Consistency verification. Experience in clocking, reset, power-up sequences and power management verification. Knowledge of microprocessor design-for-debug (DFD) logic will be a plus. Understanding of low power design verification techniques is a plus. ACADEMIC CREDENTIALS: Master s degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or Computer Science with a focus on computer architecture

We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a passionate and experienced verification engineer eager to make a difference at the forefront of technology With a strong foundation in electronics and a deep understanding of System-on-Chip (SoC) verification, you thrive in collaborative environments where complex problem solving and innovation are key You have hands-on expertise in advanced verification methodologies?particularly UVM, SystemVerilog, and C/C++?and youre familiar with industry-standard protocols such as AXI-AMBA, USB, PCIe, and MIPI Your analytical skills are matched by your ability to mentor and lead, supporting younger engineers while driving project success, You recognize the value of diversity and inclusion and bring an open-minded, adaptable approach to your work Whether working independently or as part of a multidisciplinary team, you are proactive in learning new tools and methodologies, and you consistently deliver high-quality results Your communication skills help you collaborate effectively with architects, designers, and verification teams, and your experience with ARM-based technologies gives you a unique edge You are motivated by the opportunity to solve challenging customer problems and help shape the future of high-performance computing, automotive, aerospace, and defense solutions, What Youll Be Doing: Designing and developing comprehensive verification test plans and infrastructure based on design specifications and customer requirements, Implementing and analyzing SystemVerilog assertions and coverage metrics (code, toggle, functional) to ensure design correctness, Leading verification activities, mentoring junior engineers, and assisting in debugging complex issues, Collaborating closely with architects, designers, and pre & post silicon verification teams to achieve project goals, Adhering to rigorous quality standards and best practices in test and verification processes, Rapidly ramping up on new verification tools and methodologies using Synopsys products to enable customer success, Developing innovative, independent solutions to technical challenges with minimal guidance, Consistently setting and achieving task-level goals and project milestones, Working with Synopsys teams, including Business Unit Application Engineers and Sales, to broaden and deploy tool and IP solutions, The Impact You Will Have: Ensuring the delivery of robust, high-quality SoC solutions for leading-edge customers in diverse industries, Accelerating the verification process, reducing time-to-market for innovative chip designs, Enhancing customer satisfaction by solving complex design and verification challenges, Driving the adoption of Synopsys EDA tools and IP, strengthening the companys market leadership, Enabling the successful launch of products in high-performance computing, automotive, aerospace, and defense sectors, Mentoring and developing junior team members, fostering a culture of excellence and continuous learning, Contributing to the evolution of verification methodologies and best practices, What Youll Need: E/B Proven experience in IP or SoC level verification, including processor-based SoC environments (native, Verilog, SystemVerilog, UVM mixed), Hands-on expertise with verification tools such as VCS, waveform analyzers, and third-party VIP integration (e-g , Synopsys VIPs), Strong proficiency in UVM, SystemVerilog, and C/C++ for verification, Familiarity with AXI-AMBA protocol variants, scripting languages (shell, Makefile, Perl), and ASIC design concepts and flow, Experience with ARM core verification, USB, PCIe, MIPI protocols, and ARM-based technologies (Coresight Debug, Processor architecture) is highly desirable, Excellent problem-solving, analytical, and debugging skills, Effective communication skills for teamwork and customer engagement, Who You Are: Collaborative team player who thrives in a diverse, inclusive environment, Proactive learner, always eager to master new tools and methodologies, Detail-oriented with a strong commitment to quality and excellence, Natural mentor and leader, able to support and guide junior engineers, Resourceful thinker with a passion for solving complex technical challenges, Clear communicator, able to convey technical concepts to various audiences, The Team Youll Be A Part Of: Youll join the System Solutions Group (SSG), a dynamic team delivering expertise in tool, methodology, architecture, design creation, verification, and physical implementation SSG partners with startups, industry leaders, commercial companies, and government agencies to tackle the most challenging SoC projects?from sub-blocks to full turnkey solutions Our team is passionate about enabling customers in high-performance computing, automotive, aerospace, and defense to achieve their goals with innovative, reliable solutions, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process, Show more Show less

About this opportunity: Are you passionate about driving innovation and working on groundbreaking 5G and 6G mobile communication solutions? Do you thrive in a flexible working culture, where new insights are championed, and you are encouraged to develop new skills? We are looking for an FPGA Verifier to join the Ericsson Silicon organization. You will work with dedicated engineers who are passionate about developing world-class Radio and RAN Compute products. You will play a key role in the FPGA team defining verification strategies and implementing environments for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity and teamwork You will do: - Participate in test plan, test case, code review and ensure high standards. - Assist in defining verification requirements and strategies for FPGA/ASIC projects. - Measure functional and code coverage metrics, driving towards completion targets. - Analyse simulation results, debug issues, and collaborate with design teams for resolution. - Contribute to the continuous improvement of products, tools, and processes. - Maintain and enhance regression test suits and support continuous integration flows. - Follow and contribute to the team s best practices, processes, and documentation standard. You must have: - 3 to 5 years of experience in FPGA/ASIC verification. - Familiarity with the process of verifying IPs and subsystem components. - Good expertise in verification methodologies such as UVM. - Proficiency in SystemVerilog. - Ability to understand, reuse existing code effectively and/or write reusable, module level and well documented code for verification. - Experience with simulation and verification tools like Xcelium, VCS, QuestaSim. - Experience with waveform viewers, debugging techniques and coverage-driven verification. - Experience with scripting languages such as Python, Tcl, shell scripting, etc. - Understanding of digital design fundamentals. - Familiarity in version control GIT. - A problem-solving attitude, self-motivation, and eagerness to learn and contribute. - Excellent English verbal and written communication skills - Bachelor/Master degree in Electronics or Computer Engineering or equivalent. Nice to have: - Ability to architect and create UVM/test benches from scratch - Familiarity with modern FPGA device families and tools - Wireless/5G IP/SOC verification experience Why join Ericsson? At Ericsson, you ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what s possible. To build solutions never seen before to some of the world s toughest problems. You ll be challenged, but you won t be alone. You ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next. What happens once you apply? Click Here to find all you need to know about what our typical hiring process looks like. Encouraging a diverse and inclusive organization is core to our values at Ericsson, thats why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more. Primary country and city: India (IN) || Bangalore Req ID: 772847

Mesh / Coherency Design Verification Engineer in Bangalore, KA, India Mesh / Coherency Design Verification Engineer Description Invent the future with us. Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team we d love to have you apply. Come invent the future with us. About the role: You will work on the verification of a server-class microprocessor-based CPU/Coherent Mesh interconnect. Youll be involved with all aspects of pre-silicon verification at unit and system level to ensure functional correctness and performance of microprocessors. Youll also partner with other teams to accelerate post-silicon validation and debug of the product. In this role, you will be at the forefront of AI innovation, building AmpereOne Aurora, our groundbreaking AI compute solution. Aurora combines high-performance general-purpose CPUs with integrated AI capabilities, offering a compelling combination of efficiency and market reach. This revolutionary product is poised to deliver superior performance while consuming significantly less power. What you ll achieve: Define requirements for block level and subsystem level testing infrastructure Create test plans for unit-level and chip-level verification and post-silicon validation Architect, design and implement test benches and other components of design verification environment Create random test generators to find bugs in design Debug failures and drive speedy resolution of bugs Create coverage monitors and drive coverage to required quality targets Define post-silicon validation plans, and engage in post-silicon activities to accelerate product launch Lead verification activities within a team and guide other engineers to achieve project goals About you: M.Tech in Electronics Engineering or Computer Engineering with 3+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 5+ years of semiconductor experience Solid understanding of high-performance microprocessor architecture concepts Experience using industry standard HDL languages (Verilog, System Verilog, VHDL) and simulation tools Experience developing verification environments in one or more industry standard languages like SVTB UVM/OVM Programming experience in languages common to the industry (e.g., C, C++, Perl, Python) Experience in automating design, verification, and validation tasks Hands on experience in post-silicon validation Knowledge of ARM or x86 architecture and assembly language programming Previous experience in CPU/core design verification is preferred Previous experience in Network-on-chip (NoC) design verification is preferred Previous experience with Arm AMBA (APB/AHB/AXI/ACE/CHI) protocols is preferred Previous experience with formal verification is preferred What we ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits highlights include: Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process. #LI-SF1 Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.

Mesh / Coherency Design Verification Engineer in Pune, MH, India Mesh / Coherency Design Verification Engineer Description Invent the future with us. Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team we d love to have you apply. Come invent the future with us. About the role: You will work on the verification of a server-class microprocessor-based CPU/Coherent Mesh interconnect. Youll be involved with all aspects of pre-silicon verification at unit and system level to ensure functional correctness and performance of microprocessors. Youll also partner with other teams to accelerate post-silicon validation and debug of the product. In this role, you will be at the forefront of AI innovation, building AmpereOne Aurora, our groundbreaking AI compute solution. Aurora combines high-performance general-purpose CPUs with integrated AI capabilities, offering a compelling combination of efficiency and market reach. This revolutionary product is poised to deliver superior performance while consuming significantly less power. What you ll achieve: Define requirements for block level and subsystem level testing infrastructure Create test plans for unit-level and chip-level verification and post-silicon validation Architect, design and implement test benches and other components of design verification environment Create random test generators to find bugs in design Debug failures and drive speedy resolution of bugs Create coverage monitors and drive coverage to required quality targets Define post-silicon validation plans, and engage in post-silicon activities to accelerate product launch Lead verification activities within a team and guide other engineers to achieve project goals About you: M.Tech in Electronics Engineering or Computer Engineering with 3+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 5+ years of semiconductor experience Solid understanding of high-performance microprocessor architecture concepts Experience using industry standard HDL languages (Verilog, System Verilog, VHDL) and simulation tools Experience developing verification environments in one or more industry standard languages like SVTB UVM/OVM Programming experience in languages common to the industry (e.g., C, C++, Perl, Python) Experience in automating design, verification, and validation tasks Hands on experience in post-silicon validation Knowledge of ARM or x86 architecture and assembly language programming Previous experience in CPU/core design verification is preferred Previous experience in Network-on-chip (NoC) design verification is preferred Previous experience with Arm AMBA (APB/AHB/AXI/ACE/CHI) protocols is preferred Previous experience with formal verification is preferred What we ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits highlights include: Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process. #LI-SF1 Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.

Desired Profile : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering. Expertise in execution and debugging of test-suites at the GPU sub-system level Expertise in GLS (Gate-Level Simulation) Expertise in writing assertions and test benches using system verilog Expertise in UVM methodologies Expertise in Test planning Expertise in sub-system level DV Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations Preferred resources with valid regional work permit

Desired Profile : Bachelor's / Master's degree in engineering from EEE / E&C Expertise in managing and leading technical teams across different continents Expertise in leading business strategy in the VLSI / Semiconductor Services / foundry business industry Expertise in managing end to end projects including tape outs Must be willing to travel at short notice, relocate as per business needs Must be willing to work onsite (customer premises) as per business needs Expertise in working on any of the following technologies is mandatory : ANALOG MIXED SIGNAL LAYOUT - finfet / high speed / planar technology nodes ANALOG DESIGN - data converter / power management / pll ANALOG VERIFICATION ASIC PHYSICAL DESIGN ASIC RTL DESIGN DFT DESIGN - jtag / mbist / lbist / scan DIGITAL VERIFICATION - OVM / UVM / VMM EDA CAD FLOW - tcl / primetime / design compiler Job Specs : Responsible for meeting delivery, revenue, operational, customer satisfaction targets and team management Hire and manage high caliber technical teams across GCC, ODC and onsite Develop, Drive high quality business / technology strategy and oversee the translation of this strategy into tactical action Uphold the organization's culture and long term missions Liaise and negotiate with various partners around the world to bring in new partnership. Synergize all company's resources and talents for the growth of company's business Oversee all sectors and fields of the business to ensure the company's competitiveness Provide leadership, direction, major decision making and resolution support to operations, projects and staff. Build strategic business partnerships and execute these opportunities through collaboration with external partners Location - Bengaluru,Bhubaneswar,Kolkata,Kochi,Mysuru

Work on creating verification plan for RISC-V based application specific IP Build Standalone IP test bench using System Verilog Develop test cases, coverage model and assertions needed to ensure functional correctness of the Design Under Test (i.e., IP/SOC) Use the IP/SOC RTL in system verilog based logic verification environment complete the functional verification Generate functional and code coverage metrics, collaborate with IP developers on the correctness completeness of IP functionality. Deliver the functional test vectors needed to be used for post-silicon validation. Be the single point contact for the concerned IP Verification and enable the Tapeout for all control ASICs of Enphase Who you are and what you bring Proficient in UVM, Verilog, SystemVerilog, C, Python. Working on the HW/SW interface. Strong understanding and experience of logic verification environment (UVM System Verilog) Strong understanding of RISC-V architecture functional verification Experience with processor toolchains (compiler, assembler, simulator). Experience with processor verification. Directed tests and random program generated tests. Experience with functional processor simulators. Experience with verification of secure processor boot code. Experience with Floating point instructions implementation verification in micro controller based ASIC designs Ability to quickly adapt to other categories of C-based/System Verilog based IP verification Experience and ability to bring complex SOCs into the physical world and into production. Excellent problem solving skills, written verbal communication skills Logic Verification #Embedded C Verification #ARM #Boot. Prior hands on work experience of at least 8 years in Logic IP Verification based on System Verilog.

Job Title: Lead / Staff Engineer ASIC IP & Subsystem Verification Location : Bangalore Notice Period : Immediate to 30 Days About the Role We are seeking a highly experienced Design Verification professional (Lead/Staff Engineer) to drive IP, Subsystem, and SoC-level verification for Micron’s advanced memory and semiconductor products. This role is hands-on with opportunities to mentor small teams, own verification strategy, and ensure signoff-quality verification closure across a wide range of products (digital, mixed-signal, low-power). Key Responsibilities Lead end-to-end verification for IPs, Subsystems, and SoCs – including planning, execution, and coverage closure. Architect, enhance, and maintain UVM/SystemVerilog/Specman-based testbenches . Define and execute verification plans (VPlans) , ensuring 100% functional, assertion, and code coverage. Drive low-power (PARTL, PAGLS) and GLS verification flows to ensure signoff-quality. Collaborate with design, architecture, STA, PD, and firmware teams for bug closure and performance validation. Debug RTL/netlist issues and provide hands-on technical guidance to team members. Automate regression, coverage, and debug tasks using Python/Perl/Shell scripting . Contribute to methodology enhancements and drive adoption across teams. Lead and mentor small teams (5–8 members) , providing ramp-up, task delegation, and review support. Interface with cross-geo teams and contribute to global project execution. Technical Expertise Required Experience : 14–26 years in ASIC/SoC/IP Verification with strong subsystem experience. Languages/Methodologies : SystemVerilog, UVM, Specman “e”, Verilog, VMM. Verification Domains : IPs (PCIe/CXL, Cache, PHY, Modem, Display, Crypto), Subsystems (DSP, MSS, Memory Controllers), and SoC-level integration. Low-Power & GLS : Power-aware RTL verification (PARTL), GLS, PAGLS, UPF/CPF flows. Protocols/Interfaces : AXI, AHB, APB, OCP, PCIe, CXL, DDR, I2C, SPI. Tools : VCS, NCSim, Specman, Verdi, IUS, vManager, IMC, adcanvas. Scripting : Python, Perl, Shell, TCL for automation and debug. Mixed-Signal/AMS : Experience in verification of digital + mixed-signal subsystems (MPHY receiver, display, PHYs). Validation : Experience in pre-silicon validation environments with SoC bring-up support. Soft Skills & Leadership Proven ability to lead 5–8 member teams – task delegation, ramp-up, mentoring. Strong debug, problem-solving, and performance analysis skills . Track record of technical papers/publications (SNUG, TI ITC, CDNLive). Ability to collaborate effectively with multi-site and multicultural teams . Why Join Micron Work on state-of-the-art memory and SoC verification challenges across IP, Subsystem, and SoC. Lead cross-functional and cross-geo projects with ownership of signoff quality. Exposure to low-power verification, AMS/DMS flows, and validation . Drive methodology improvements and leadership opportunities within a global engineering team. Immediate–30 Day joiners please share your CVs to: prabhu.p@acldigital.com WhatsApp/Call: +91-8754387484

As a Portable Stimulus (PSS) Verification Lead at Vayavya Labs, you will play a crucial role in understanding customer requirements on system-level verification scenarios and developing test scenarios in PSS language and C or SystemVerilog/UVM. Your responsibilities will include executing test scenarios in pre-silicon and post-silicon environments, as well as debugging the test scenarios. Key Responsibilities: - Understand customer requirements on system-level verification scenarios - Develop test scenarios in PSS language and in C or SystemVerilog/UVM - Execute test scenarios in pre-silicon (simulation, emulation) and post-silicon environments - Debug test scenarios Qualifications Required: - Hands-on experience in C programming for embedded systems - Expertise in pre-silicon validation of system-level scenarios - Experience with verification of controllers for protocols like PCIe, Ethernet, MIPI CSI/DSI - Familiarity with verification on emulator environments Vayavya Labs has been actively contributing to the development and adoption of the PSS standard, making it a leader in the industry. By joining our team, you will have the opportunity to work on Portable Stimulus technologies and develop scenarios for various SoC sub-systems. Additionally, you will receive training on PSS as part of the ramp-up phase. You will also be involved in project planning, effort estimation, technical leadership, and mentoring other team members on PSS. It is essential to have strong analytical and problem-solving skills, excellent communication skills, and a self-managed approach to work. This position offers a great learning opportunity for engineers with experience in system-level verification scenarios and a keen interest in SoC verification technologies. Vayavya Labs is at the forefront of the industry, driving discussions and advancements in Portable Stimulus technologies. If you are eager to take on new challenges and work with cutting-edge verification methodologies, this role is perfect for you.,

Experience : 3 to 10 Years Qualification : Bachelors or Masters (Electronics and Communication Engineering or equivalent) Job Description: As an Emulation Engineer, youll be an integral part of a dynamic team dedicated to creating cutting-edge ASIC solutions for High-Performance Computing (HPC) systems. Your role will involve defining the validation strategy leading to functional sign-off for these high-performance computing designs. Key functions and responsibilities: Proficient in various emulation technologies, including simulation acceleration, in-circuit emulation, speed bridges, virtual prototyping, and hybrid methods. Familiarity with tools such as Palladium, Protium, Veloce, or Zebu. Good Knowledge of SystemC/C/C++ and UVM/SV verification languages Experience with SystemVerilog and C++ for modelling RTL components and transactors. Ability to develop C/C++/SystemC/SV tests in HDL-HVL (Hardware Description Language-Hardware Verification Language) Co-emulation platforms. Understanding of compilation and build flow. Skilled at building images from scratch, making necessary design modifications to adapt to emulation. Work closely with verification teams to define and implement comprehensive pre and post silicon test plans. Interface effectively with design, verification, validation, and software development teams to understand their needs from an emulation perspective. Experience in architecting emulation systems for various design scales (IP blocks, SOC, multi-chip systems). Balancing performance and ease of debug. Proficient in post-silicon bring-up, debugging, and issue reproduction on emulators. Familiarity with Python and TCL scripting languages. Exposure to domains such as PCIe, CXL, DDR, Flash, Memory, USB, and CPU. Strong communication and collaboration skills to work effectively with cross-functional teams and domain experts. Successfully manage multiple design releases and provide support for debugging customer issues.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: GPU Design and micro-Architect who will work across functions like GPU architecture and Systems in design and micro-architecture of the next generation GPU features. Work very closely with Architecture teams to come up with micro-architecture and hardware specification for features Design and RTL ownership Work very closely with Design Verification teams to review test plans and sign off the validation of all design features across products Work closely with physical design teams to achieve the right power, performance and area metrics for the GPU blocks Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Overview UVM Based verificaton at SOC level Responsibilities As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Requirements Bachelor’s/ Master’s degree or higher in EEE/ECE 5+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platformsUVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with ARM/RISCV Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skills

Overview Developing emulation testbenches to support necessary DV scenarios and firmware/software/hardware bring up Responsibilities Build emulation models from RTL and release/support those models Develop emulation tools such as debugger and monitor features Work closely with verification and software development teams Develop emulation and verification strategy Develop test framework and test cases Write documents such as verification specification and reports Coach younger colleagues Emulation and Prototyping technologies such as Palladium, Veloce, Zebu, HAPS, (these names are registered trade marks of their respective owners) Requirements Experience - minimum 15+ yrs and above with minimum of 5+ yrs of experience of woking on any one of the Emulation platform. Education QualificationBE/BTech

Overview Lead Verification engineer Responsibilities As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Requirements Bachelors/ Masters degree or higher in EEE/ECE 7+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platforms: UVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with ARM/RISCV Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skills