234 Formal Verification Jobs - Page 2

Qualcomm India Private Limited is seeking an experienced individual for the role of Micro-Architect and RTL Design Engineer to take ownership of the System Memory Management Unit (SMMU) IP for the next generation System-on-Chip (SoC) for smartphones, tablets, and other product categories. The SMMU performs virtual to physical address translation, dynamic allocation, and access control of DDR memory, designed in accordance with the ARM SMMU architecture spec. In this role, you will collaborate with Hardware and Software teams to comprehend design requirements, specifications, and interface details for the SMMU IP. You will be responsible for developing a micro-arch design specification that is optimized for performance, area, power, and software use cases. Additionally, you will implement the design spec in RTL coding language, ensuring code quality through various checks such as Lint, CDC, Synthesis, DFT, and low power checks. You will also work with the SoC level performance modeling team on latency, bandwidth analysis, and fine-tuning hardware configuration. The ideal candidate should possess expertise in VLSI logic design, ARM system architecture, memory management, virtual memory concepts, and core sight architecture. Knowledge of on-chip interconnect protocols like APB/AHB/AXI/ACE/ACE-Lite is essential, along with strong debugging, analytical, and problem-solving skills. A good understanding of the ASIC design convergence cycle and effective communication and collaboration abilities are also required. Desired skills include experience in designs optimized for low power, proficiency in scripting languages (Python or Perl) for automation initiatives, and working knowledge of Synthesis, DFT, LEC, functional cover points/assertions, and formal verification. The minimum qualifications for this role include a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field, with 4+ years of Hardware Engineering or related work experience. Alternatively, a Master's degree with 3+ years of experience or a PhD with 2+ years of experience is also acceptable. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com. Additionally, Qualcomm expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. Please note that Qualcomm's Careers Site is intended for individuals seeking job opportunities directly with Qualcomm. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes through the site. Unsolicited submissions from agencies will not be considered. For more information about this role, please reach out to Qualcomm Careers.,

Qualcomm India Private Limited is a leading technology innovator that is dedicated to pushing the boundaries of what's possible in order to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, your role will involve planning, designing, optimizing, verifying, and testing electronic systems. This includes working on a variety of systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems for cutting-edge products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. To be considered for this position, you must possess a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 4 years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years of experience or a PhD with 2+ years of experience will also be considered. Join Qualcomm's design verification team to work on Digital Low Power IPs for products aimed at 5G, AI/ML, compute, IOT, and automotive applications. This team is responsible for the complete design verification lifecycle, from system-level concept to tape out and post-silicon support. Key responsibilities in this role include defining pre-silicon and post-silicon test plans based on design specs, developing testbenches using advanced verification methodologies like SystemVerilog/UVM, authoring assertions, developing test cases, and ensuring coverage closure. Collaboration with various teams such as digital design, analog circuit design, modeling, and SoC integration is crucial for successful IP level verification and integration. Minimum qualifications for this role include a Master's/Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with at least 8 years of ASIC design verification experience. Knowledge of methodologies like SystemVerilog/UVM and experience with ASIC simulation/formal tools is required. Preferred qualifications for this position include experience with Low power design verification, Formal verification, Gate level simulation, and knowledge of standard protocols such as Power Management Flows, PCIe, USB, MIPI, LPDDR, etc. Experience in scripting languages like Python or Perl will be an advantage. Qualcomm is an equal opportunity employer and is committed to providing reasonable accommodations for individuals with disabilities during the application/hiring process. If you require an accommodation, please contact disability-accommodations@qualcomm.com. Qualcomm expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. For more information about this role, please reach out to Qualcomm Careers.,

Qualcomm India Private Limited is seeking a Hardware Engineer to join the Engineering Group, specifically in the Hardware Engineering area. As a Hardware Engineer at Qualcomm, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other systems to contribute to the development of cutting-edge products. You will collaborate with cross-functional teams to find solutions and meet performance requirements. The ideal candidate should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 4 years of experience in Hardware Engineering, or a Master's degree with 3+ years of experience, or a PhD with 2+ years of experience. Strong understanding and knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools is required. Experience in writing timing constraints, STA, timing closure, pipelining, and multi-clock domain designs is essential. Familiarity with MCMM synthesis, low-power design implementation using UPF, scripting languages such as Perl/Python, TCL, power optimization flows like clock gating, and handling ECOs and formal verification are also necessary. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. Reasonable accommodations can be requested by contacting disability-accommodations@qualcomm.com or Qualcomm's toll-free number. The company expects its employees to adhere to all applicable policies and procedures, including those related to security and protection of confidential information. For this role, Qualcomm does not accept unsolicited resumes or applications from staffing and recruiting agencies. Any submissions from unauthorized sources will be considered unsolicited. For more information about this position, please reach out to Qualcomm Careers.,

You will be working at Qualcomm India Private Limited in the Engineering Group, specifically in the Hardware Engineering department. As a Camera Design Lead/Staff, your primary responsibility will involve designing and developing next-generation SoC sub-systems for mobile phone cameras. This role will require you to work on ASICs based on the latest technology nodes, covering all aspects of VLSI development cycle such as architecture, microarchitecture, Synthesis/PD interaction, and design convergence. To excel in this role, you should have 5-10 years of experience with a Master's degree (6 to 10 years with a Bachelor's degree) and possess the following skills: - Solid experience in digital front-end design for ASICs - Expertise in RTL microarchitecture and design coding in Verilog/SV for complex designs with multiple clock and power domains - Familiarity with bus protocols like AHB, AXI, and NOC designs - Experience in low power design methodology and clock domain crossing designs - Understanding of full RTL to GDS flow to collaborate with DFT and PD teams - Proficiency in tools like Spyglass Lint/CDC checks and waiver creation - Exposure to formal verification with Cadence LEC - Additional experience in mobile Multimedia/Camera design, DSP/ISP knowledge, timing closure, Perl, TCL language, post-Si debug is a plus Apart from technical skills, you should possess good communication skills to interact effectively with Engineering Management and mentor group members. Being self-motivated with a good team-working attitude is essential, as you will be expected to function with minimal direct guidance or supervision. Minimum Qualifications for this role include: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 4+ years of Hardware Engineering or related work experience OR - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 3+ years of Hardware Engineering or related work experience OR - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 2+ years of Hardware Engineering or related work experience Qualcomm is an equal opportunity employer and is committed to providing reasonable accommodations for individuals with disabilities during the application/hiring process. If you require such accommodations, you can contact Qualcomm at disability-accommodations@qualcomm.com or through their toll-free number. It is important to note that Qualcomm expects its employees to adhere to all applicable policies and procedures, including those related to the protection of company confidential information. Please refrain from sending unsolicited resumes or applications to Qualcomm, as the company does not accept such submissions from staffing and recruiting agencies. For more information about this role, you can contact Qualcomm Careers directly.,

Qualcomm India Private Limited is seeking a Hardware Engineer to join the Engineering Group. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Your role will involve launching cutting-edge, world-class products by collaborating with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. The role involves Physical Implementation activities for high-performance Cores for various technologies, including floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), Low Power verification, PDN, Timing Closure, power optimization, and more. The ideal candidate should have exposure to PD implementation of PPA critical cores, timing convergence of high-frequency data-path intensive Cores, advanced STA concepts, clocking architecture, and should be proficient in Tcl/Python/Perl Scripting for automation. Strong problem-solving skills, communication skills, and the ability to work well in a team are essential. Collaboration with design, DFT, and PNR teams to support issue resolutions is also a key aspect of the role. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. Reasonable accommodations can be requested by contacting disability-accommodations@qualcomm.com. Qualcomm expects its employees to adhere to all applicable policies and procedures, including security and confidentiality requirements. Recruitment agencies are advised that Qualcomm's Careers Site is intended for individuals seeking jobs at Qualcomm. Unsolicited submissions from agencies will not be accepted. For more information about this role, please contact Qualcomm Careers.,

You will be responsible for Physical Implementation activities for sub systems, including Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure, and power optimization. Your role will involve ensuring good exposure to PD implementation of PPA critical Cores and making the right PPA trade-off decisions. You should possess knowledge in timing convergence of high-frequency data-path intensive Cores and advanced STA concepts. Additionally, familiarity with Block level PnR convergence using tools like Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus is essential. A good understanding of clocking architecture is required for this role. You will collaborate closely with design, DFT, and PNR teams to resolve issues related to constraints validation, verification, STA, Physical design, etc. Proficiency in Tcl/Perl Scripting and strong problem-solving skills, along with effective communication skills, are vital for this position. Qualcomm India Private Limited is seeking candidates with a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field and 2+ years of Hardware Engineering or related work experience. Alternatively, a Master's degree in a relevant field and 1+ year of Hardware Engineering experience, or a PhD in a related field, are also acceptable qualifications. The ideal candidate should have 1-3 years of experience in Physical Design/Implementation. Qualcomm is an equal opportunity employer and is committed to providing reasonable accommodations for individuals with disabilities during the application/hiring process. Qualcomm expects all employees to adhere to applicable policies and procedures, including those related to security and the protection of Company and proprietary information. It is essential to ensure workplace accessibility for individuals with disabilities. For further information about this role, please contact Qualcomm Careers.,

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER THE ROLE: Execute formal verification for complex blocks for AMD's graphics processor IP, resulting in no bugs in the final design. THE PERSON: Good knowledge of formal verification along with understanding of complex designs. KEY RESPONSIBILITIES: Understand the design to be verified Plan and execute formal verification. Formal test plan documentation. Estimate the time required for formal verification, coverage and clock gating checks. Build the formal property verification/datapath verification environments. PREFERRED EXPERIENCE: 7+ years of formal verification experience . Familiarity with CPUs/GPUs/Cache is desirable. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-NS1 Benefits offered are described: . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

Wipro Limited is a leading technology services and consulting company dedicated to developing innovative solutions that cater to the most intricate digital transformation needs of clients. With a vast portfolio of capabilities in consulting, design, engineering, and operations, Wipro assists clients in achieving their most ambitious goals and establishing future-ready, sustainable businesses. The company, with over 230,000 employees and business partners operating in 65 countries, is committed to aiding customers, colleagues, and communities in thriving amidst a constantly changing world. For more information, visit www.wipro.com. As a Lead Design Verification Engineer with at least 7 years of hands-on DV experience in SystemVerilog/UVM, you will be responsible for owning and driving the verification of a block/subsystem or a SOC. An ideal candidate should have a proven track record of leading a team of engineers and possess extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. Proficiency in Tesplan and Testbench development, execution of test plans using high-quality constrained random UVM tests to achieve coverage goals on time, and adeptness in debugging and exposure to all aspects of verification flow including Gatesims are essential. The candidate must have extensive experience in the verification of technologies such as PCI Express or UCIe, CXL or NVMe, AXI, ACE or CHI, Ethernet, RoCE or RDMA, DDR or LPDDR or HBM, ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages, and Power Aware Simulations using UPF. Experience in using EDA tools like VCS, Verdi, Cadence Xcelium, Simvision, Jasper, and revision control systems such as Git, Perforce, Clearcase is required. Experience in SVA and formal verification is desirable, and knowledge of script development using Python, Perl, or TCL is an added advantage. The position is available in various locations including Bangalore, Hyderabad, Kochi, Pune, Ahmedabad, and Pune. The ideal candidate must have a minimum of 7 years of YoE. Key Responsibilities: - Define product requirements and implement VLSI and hardware devices - Continuously upgrade and update design tools and frameworks - Analyze and select the right components and hardware elements for product engineering - Conduct cost-benefit analysis to choose the best design - Develop architectural designs for new and existing products - Implement derived solutions and troubleshoot critical problems - Evangelize architecture to project and customer teams to achieve the final solution - Monitor product solution and make continuous improvements - Understand market-driven business needs and technology trends to define architecture requirements and strategy - Develop Proof of Concepts (POCs) to demonstrate product feasibility - Provide solutioning for RFPs from clients and ensure overall product design assurance - Collaborate with sales, development, and consulting teams to reconcile solutions to architecture - Provide technical leadership in designing custom solutions using modern technology - Validate solutions from technology, cost structure, and customer differentiation perspectives - Identify and resolve problem areas in architectural design and solutions - Monitor industry and application trends and provide strategic input during product deployment - Support delivery team in product deployment and issue resolution - Develop product validation and performance testing plan in alignment with business requirements - Maintain product roadmap and provide inputs for product upgrades based on market needs - Build competencies and branding through necessary trainings, certifications, and Thought leadership content development - Mentor developers, designers, and junior architects for career enhancement - Contribute to the architecture practice by conducting selection interviews Performance Parameters: - Product design, engineering, and implementation: Measure based on CSAT, quality of design/architecture, FTR, delivery as per cost, quality, and timeline, POC review and standards - Capability development: Measure based on % of trainings and certifications completed, mentorship of technical teams, and development of Thought leadership content Wipro is dedicated to reinventing your world by building a modern, end-to-end digital transformation partner with ambitious goals. The company is looking for individuals who are inspired by reinvention and are committed to constant evolution in their careers and skills. Join Wipro to realize your ambitions and be part of a purpose-driven business that empowers you to design your own reinvention. Applications from people with disabilities are explicitly welcome.,

You will be joining VIDAL HEALTH INSURANCE TPA PRIVATE LIMITED, a rapidly growing health care company located in Bangalore, Karnataka, India. Our office is based in the EPIP Zone, Whitefield, specifically on the 1st Floor, Tower 2 of SJR i Park. We are dedicated to providing top-tier health insurance services and third-party administration solutions. As a Verification professional in Bengaluru, your primary responsibility will be to verify insurance claims with precision and integrity while delivering exceptional customer service. This full-time, on-site role entails engaging in formal verification tasks, utilizing analytical skills to evaluate data, and maintaining effective communication with stakeholders. To excel in this role, you should possess proficiency in Insurance Verification and Formal Verification, along with strong analytical capabilities and excellent customer service skills. Your communication skills, both written and verbal, should be exemplary. Attention to detail and accuracy are paramount, and the ability to work autonomously as well as collaboratively is essential. Familiarity with health insurance procedures would be advantageous, and a Bachelor's degree in a related field is preferred. Join us at VIDAL HEALTH INSURANCE TPA PRIVATE LIMITED and contribute to our mission of providing industry-leading health insurance services and third-party administration solutions.,

This position offers a compelling opportunity for a skilled and driven verification engineer to become a valuable member of the Arm Systems Media IP team. The team is focused on designing Image Signal Processors (ISPs), Display Processors, and Video codecs for deployment within Arm Compute Subsystems across diverse markets such as automotive, IoT, and client segments. Our intellectual property includes RTL, reference drivers, tools, and libraries, which empower our clients to innovate and develop cutting-edge products. Your primary responsibilities will involve specifying and creating new hardware verification testbenches for upcoming hardware IP iterations. You will enhance existing testbenches to boost performance, quality, and efficiency. Additionally, you will be tasked with identifying areas for process and methodology enhancement, implementing necessary changes to elevate hardware verification practices. This role offers a unique opportunity to contribute to the team's growth and your professional advancement. Key Responsibilities: - Taking ownership of verification at the unit level or multi-unit hierarchy, or leading verification efforts for an entire IP (ISP, Display, Video). - Designing verification IP and comprehensive verification environments. - Evaluating proposed design modifications based on verification complexity. - Analyzing simulation data using machine learning and data science techniques for effective bug detection and debugging. - Recognizing opportunities for process and methodology improvement within Media IP, driving efficiency in hardware verification. - Collaborating closely with other Arm engineering teams to deliver high-quality IP that integrates seamlessly into complete systems. - Mentoring and supporting team members. Required Skills and Experience: - Proficiency in constrained-random verification, including the development of complex verification environments and testbenches. - Expertise in developing reusable and scalable code, with a strong command of SV-UVM. - Proficient scripting skills to create scripts supporting various flows. - Solid software engineering skills encompassing object-oriented programming, data structures, and algorithms. - Familiarity with tools and processes for testbench development and verification completion. - Previous technical and/or team leadership experience, essential for senior roles. Desired Skills and Experience: - Experience in team leadership and mentoring. - Knowledge of multiprocessing microarchitecture, including bus protocols like AMBA APB/AHB/AXI. - Past involvement in Formal Verification testbenches. - Experience with video codec, ISP, or display projects, including familiarity with advanced image processing algorithms. - Understanding of Functional Safety product development for the Automotive market, applying standards such as ISO 26262 and/or IEC 61508. - Exposure to Continuous Integration flows. In Return: This role offers you the opportunity to leverage your engineering expertise to support innovative technologies that will impact millions of devices over the long term. You will have the platform to advocate for and implement your ideas on a broader scale, while enhancing your technical leadership and influence. Should you require any accommodations or support to excel during the recruitment process, please reach out to accommodations@arm.com. Your requested information will be handled with confidentiality, and any accommodations will be arranged accordingly. Arm's Hybrid Working Approach: Arm's hybrid working model is designed to foster a work environment that promotes both high performance and personal well-being. We believe in the importance of in-person interactions for productivity, while also acknowledging the value of flexibility. Teams are empowered to determine their own hybrid working patterns based on the nature of their work and team requirements. Specific details regarding hybrid working arrangements for each role will be communicated during the application process. We are committed to collaborating with you to find the best solution that aligns with local legal, regulatory, tax, and other considerations. For more insights on how this approach can be tailored to your needs, please engage with us. Equal Opportunities at Arm: Arm is dedicated to providing equal opportunities for all individuals, fostering an inclusive work environment where diversity is celebrated and respected.,

Qualcomm India Private Limited is seeking an experienced RTL designer to join the DSP processor team. In this role, you will be responsible for developing RTL for multiple logic blocks of a DSP core. You will work closely with various teams including physical design, power optimization, and verification to ensure successful project completion. The ideal candidate will have 10 to 15 years of practical experience in RTL development using VHDL and/or Verilog. You should have a strong understanding of functional and structural RTL design, design partitioning, simulation, and collaboration with the design verification team. Familiarity with the latest RTL languages and tools such as Modelsim, VCS, Design Compile, Prime Time, Linting tools, CDC tools, UPF, and System Verilog Assertion is essential. Experience in processor architecture, microarchitecture implementation, microprocessor integration, and low power design is highly desirable for this role. You will also be responsible for running various frontend tools to check for linting, clock domain crossing, and synthesis, as well as working on design constraints and timing closure with the physical design team. To qualify for this position, you must have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering experience, or a Master's degree with 5+ years of experience, or a PhD with 4+ years of experience. Qualcomm is an equal opportunity employer and is committed to providing reasonable accommodations for individuals with disabilities during the application/hiring process. If you have a disability and require assistance, please contact Qualcomm at disability-accommodations@qualcomm.com or through their toll-free number. If you are passionate about RTL design and are looking to join a dynamic team at Qualcomm, we encourage you to apply for this exciting opportunity.,

The ideal candidate for this role should hold a BE/B.Tech/ME/M.Tech degree in EEE/ECE/CSE with 5-12 years of relevant industry experience. You should have a strong background in verification methodology and be proficient in architecting and developing testbench components for ISA features, clock/reset/power features of processors. Your expertise should include a deep understanding of assembly and CPU architecture, particularly in x86/ARM/RISC-V. Proficiency in programming languages such as C, C++, Verilog, and scripting languages like Perl and Python is essential. You should be able to work independently and collaborate effectively across different geographies. Main responsibilities of this role include working closely with CPU architects to comprehend processor micro-architecture, developing detailed test and coverage plans for ISA and micro-architecture features, designing and implementing component, block, and core level testbenches, and building architectural tools for ISA level verification. You will be expected to create stimulus generators that can be utilized across various domains ranging from pre-silicon to emulation and post-silicon. Additionally, you will execute verification plans, conduct DV environment bring-up, enable regression for all features under your responsibility, and troubleshoot test failures. Tracking and reporting DV progress using metrics like bugs and coverage will also be a key part of your role. Preferred qualifications for this position include in-depth knowledge of processor verification function and architecture, particularly in areas like cache coherence, memory ordering and consistency, prefetching, branch prediction, renaming, speculative execution, and memory translation. Experience in Random Instruction Sequencing (RIS) and testing at block/unit and chip levels is highly valued. Leading a team of verification engineers in CPU verification, proficiency in advanced techniques like formal, assertions, and silicon bring up, and experience in writing test plans, portable benches, transactors, and assembly are also preferred. Familiarity with various verification methodologies and tools such as simulators, coverage collection, and gate-level simulation is advantageous. The ability to independently develop test benches for a block/unit of the design is a desired skill for this role.,

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems. You will work on a wide range of systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. You should possess a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field along with 3+ years of Hardware Engineering experience. Alternatively, a Master's degree with 2+ years of related work experience or a PhD with 1+ year of related work experience is also acceptable. A minimum of 5 years of RTL Design/Hardware Engineering experience is required. Strong domain knowledge in RTL design (Verilog/VHDL/System Verilog), implementation, integration, micro-architecture, and designing cores and ASICs is essential. Additionally, familiarity with Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, scripting (Pearl/Python/TCL), and strong debugging capabilities at simulation, emulation, and Silicon environments are required. You will collaborate closely with cross-functional teams to research, design, and implement performance and power management strategies for the product roadmap. Knowledge in designing low power/power management controller IP blocks including AVS (adaptive voltage scaling), ACD (adaptive clock distribution), on-chip sensor controller is necessary. Your role will involve working closely with the technology/circuit design team to close IP block specifications, collaborating with the verification/physical design team for IP design implementation, and supporting the SoC team to integrate low power/power management IP solutions into wireless SoC chips and front-end design flows. Furthermore, you will work closely with the system/software/test team to enable low power features in SoC products. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities during the application/hiring process. If you require accommodation, you may contact disability-accommodations@qualcomm.com. Qualcomm expects its employees to adhere to all applicable policies and procedures, including security requirements for protecting confidential information. Please note that our Careers Site is intended for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies are not authorized to use this site for submissions. For more information about this role, please reach out to Qualcomm Careers directly.,

You should have experience in Logic design and RTL coding, as well as SoC design and integration for complex SoCs. Proficiency in Verilog/System-Verilog and Multi Clock designs including Asynchronous interfaces is essential. Familiarity with ASIC development tools such as Lint and CDC is required. Knowledge of Synthesis and understanding of timing concepts is a plus. Experience with ECO fixes, formal verification, and AMBA protocols like AXI, AHB, and APB, along with SoC clocking/reset architecture is necessary. Strong communication skills, proactive attitude, creativity, curiosity, motivation to learn, and good collaboration skills are expected. Your responsibilities will include understanding standards and specifications, developing architecture, documenting implementation details, hands-on work throughout the verification cycle, ensuring compliance with the latest methodologies, developing Verification IPs, defining Functional Coverage matrix and Comprehensive Test plan, managing regression and functional coverage closure, integrating and verifying DUT for IP delivery sign-off, leading a small team, and demonstrating hands-on experience in the complete verification cycle with strong verification concepts. You should have a strong knowledge of Verilog, SystemVerilog, and UVM, experience in UVM-based Verification IP development, familiarity with AMBA AXI/AHB/APB System buses, hands-on experience with PCIe/Eth/USB/DDR, expertise in System Verilog Assertions, scripting for automation, release processes, simulations, and regressions, and excellent written and oral communication skills. Leading the Verification IP development with junior engineers, exposure to the full verification cycle, and being a DV Engineer, Design Verification, or Verification Engineer are desirable skills and experiences.,

We are looking for passionate individuals who are ready to take on challenges in IP/ASIC/SOC Verification. We have open positions at all levels including Engineer, Senior Engineer, Lead, Manager, Director, and Head of Verification. The ideal candidate will have 3-20 years of experience in the field. In this role, you will be an integral part of the ASIC verification team. Your primary responsibility will be the functional verification of ASIC IPs. Our verification methodology utilizes cutting-edge techniques and tools such as coverage-driven constrained random verification and formal verification. Our design and implementation of verification environments heavily rely on object-oriented architectures and frameworks. We are seeking individuals with expertise and aptitude in verifying functions like image processing, video compression, and computer vision. As a verification engineer, you will also get the opportunity to delve into the algorithms that drive the hardware. The ideal candidate is an experienced engineer with exceptional programming skills and a genuine interest in ASIC verification. Our verification environments are complex, so a strong ability to comprehend, implement, and maintain intricate software systems is essential. Previous experience in hardware verification using SystemVerilog, UVM, low power verification, and formal methods would be advantageous. Analytical thinking, systematic approach, and attention to detail are traits we highly value in potential candidates. If you meet these criteria and are ready for an exciting challenge in the field of ASIC verification, we would love to hear from you. References are most appreciated. (ref:hirist.tech),

As a Silicon Design Engineer at AMD, you will have the opportunity to work with formal experts and designers to verify formal properties and drive convergence. Your passion for modern, complex processor architecture, digital design, and verification will be put to good use in this role. You will be a key team player with excellent communication skills, strong analytical abilities, and problem-solving skills. Your willingness to learn and readiness to take on challenges will be crucial for success in this position. Your key responsibilities will include driving formal verification for the block, writing formal properties and assertions to verify the design, coordinating with RTL engineers to implement logic design for better clock gating, and verifying various aspects of the design. You will also be responsible for writing tests, sequences, and testbench components in SystemVerilog and UVM along with formal to achieve verification of the design. Additionally, you will be accountable for verification quality metrics such as pass rates, code coverage, and functional coverage. Preferred experience for this role includes project-level experience with design concepts and RTL implementation, familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics, and a good understanding of computer organization/architecture. To qualify for this position, you should hold a Bachelor's or Master's degree in computer engineering or Electrical Engineering. Join AMD to be part of a culture that pushes the limits of innovation to solve the world's most important challenges. Together, we advance the building blocks for next-generation computing experiences in the data center, artificial intelligence, PCs, gaming, and embedded systems. At AMD, we strive for execution excellence while embodying qualities of being direct, humble, collaborative, and inclusive of diverse perspectives.,

As a Formal verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Develop skills in IBM Formal verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 – 10 years of relevant industry experience Proven experience in Formal/Functional Verification - Demonstrated execution experience of verification of logic blocks verification. Knowledge of formal methodology, Knowledge of HDLs (Verilog, VHDL, SV), Good programming skills in python, processor core u-arch skills Exposure in developing testbench environment, debugging and triaging fails. Good communication skills and be able to work effectively in a global team environment. Drive verification coverage closure, lead verification team. Drive complex scenarios, participate in High level design discussions. Track record in leading teams. Preferred technical and professional experience Writing test plans, building random / exhaustive formal verification environment, functional and coverage analysis and debug. Good understanding of the Server System

You will specify and develop new hardware verification testbenches for future generation hardware IP. You will improve existing testbenches to increase performance, quality and efficiency. You will also identify areas for improvement in processes and methodologies, then implement those changes to advance our best-practises and state of the art for hardware verification. The responsibilities of a member of the Verification team are: Reviewing and assessing proposed design changes from a verification complexity point of view Investigating and scripting new verification flows and optimising existing ones Analysis of data from simulation runs using machine learning and data science techniques to drive efficient bug discovery and debug Developing methodology and deploying within the group and having full ownership of verification closure and mentoring other members of the team. Close collaboration with other Arm engineering teams leading to high quality IP that works well in a complete system. Required skills and experience: 4+ years hardware verification experience You can demonstrate experience in working with constrained-random verification including ownership of a suitably complex verification environment. Experience of architecting and implementing functional verification environments for complex IP. Experience developing re-usable and scalable code whilst having good knowledge of UVM. Strong scripting skills being able to develop scripting to support new flows. Proven software engineering skills including understanding of object-oriented programming, data structures, and algorithms. You are familiar with the tools and processes for developing testbenches and finishing all aspects of the verification process. Strong communication skills and ability to work well as part of a team. Dedicated with a focused approach to problem analysis and solving. Strong experience in planning and estimation.

SILICON DESIGN ENGINEER 2 THE ROLE: As a Silicon Design Engineer, you will work with formal experts and designers to verify formal properties and drive convergence . THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem - solving skills and are willing to learn and ready to take on problems . KEY RESPONSIBILITIES: Drive formal verification for the block and write formal properties and assertions to verify the design Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design Write tests, sequences, and testbench components in SystemVerilog and UVM along with formal to achieve verification of the design Responsible for verification quality metrics like pass rates, code coverage and functional coverage PREFERRED EXPERIENCE: Project level experience with design concepts and RTL implementation for same Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics Good understanding of computer organization/architecture ACADEMIC CREDENTIALS: Bachelor s or M aster s degree in computer engineering/Electrical Engineering #LI-PK1

NVIDIA is at the forefront of innovation, constantly reinventing itself to meet the demands of the evolving technology landscape. Our groundbreaking invention of the GPU has not only revolutionized modern computer graphics and parallel computing but has also played a pivotal role in the growth of the PC gaming market. In the current era, the global surge in artificial intelligence research necessitates highly scalable and massively parallel computational power, which NVIDIA GPUs excel at providing. At NVIDIA, we are dedicated to amplifying human creativity and intelligence, striving to address complex challenges and opportunities that have a profound impact on the world. As a valued member of our team, you will be part of a diverse and supportive environment that encourages everyone to excel and contribute their best work. We are currently seeking passionate, highly motivated individuals to join our automotive verification team. In this role, you will have the opportunity to work on projects that will shape the future of automotive chips and systems. You will be exposed to cutting-edge technologies such as high-performance CPU and Memory sub-systems, NOC-based Interconnect Fabric, High-speed IOs, and more, all integrated into our Tegra chips. Your responsibilities will include creating advanced UVM-based verification test benches and methodologies to validate complex IPs and Sub-systems. Additionally, you will engage in system-level verification using C/C++. Throughout a project, you will be tasked with various verification aspects for your unit, such as architecting testbenches, defining test plans, building efficient bus functional models, implementing functional coverage, and collaborating with different teams to ensure the robustness of your unit. To excel in this role, you should hold a BTech/MTech degree with a minimum of 2 years of experience in verification closure at the Unit, Sub-system, or SOC level. Proficiency in domains such as CPU verification, Memory controller verification, Interconnect verification, High-Speed IO verification, and Bus protocols will be advantageous. Knowledge of the latest verification methodologies like UVM/VMM, exposure to industry-standard verification tools, and strong debugging and analytical skills are essential. Moreover, excellent interpersonal and communication skills are crucial for effective collaboration with cross-cultural teams in a matrix organization. Joining NVIDIA means becoming part of a team that offers highly competitive salaries and a comprehensive benefits package. Recognized as one of the most desirable employers in the technology sector, we take pride in having some of the brightest minds in the industry. If you are a creative, independent individual with a genuine passion for technology, we invite you to be a part of our team and make a significant impact on the world. JR2001732,

Job Overview This position is an excellent opportunity for an experienced and highly motivated verification engineer to join the Arm Systems Media IP team! The team is responsible for the development of Image Signal Processors (ISPs), Display Processors, and Video codecs for deploying within Arm Compute Subsystems for various end markets, including automotive, IoT, and client market segments. Our intellectual property encompasses RTL, reference drivers, tools, and libraries, enabling our customers to build upon our work to create innovative products! You will specify and develop new hardware verification testbenches for future generation hardware IP. You will improve existing testbenches to increase performance, quality and efficiency. You will also identify areas for improvement in processes and methodologies, then implement those changes to advance our best-practices for hardware verification. This is a new team with plenty of opportunities to shape its future, and your own growth and career progression. Responsibilities Depending on prior experience, the responsibilities of the role can include: Verification ownership of unit level or multi-unit hierarchy or alternatively verification lead of an overall IP (ISP, Display, Video). Architecting verification IP and full verification environments. Reviewing and assessing proposed design changes from a verification complexity point of view. Analysis of data from simulation runs using machine learning and data science techniques to drive efficient bug discovery and debug. Identify cross Media IP process or methodology improvement opportunities, implementing changes to advance hardware verification efficiency. Close collaboration with other Arm engineering teams leading to high quality IP that works well in a complete system. Mentor & support other members of the team. Required skills and experience: Experience in working with constrained-random verification including ownership of a suitably complex verification environment and creating testbenches. Experience developing reusable and scalable code whilst having in-depth knowledge of SV-UVM. Strong scripting skills being able to develop scripts to support new and existing flows. Solid software engineering skills including understanding of object-oriented programming, data structures, and algorithms. Familiar with the tools and processes for developing testbenches and finishing all aspects of the verification process. Prior technical and/or team leadership skills required for more senior positions. Nice to Have skills and Experience: Team leadership and mentoring experience. Multiprocessing microarchitecture experience including knowledge of bus protocols (e.g. AMBA APB/AHB/AXI). Past experience in Formal Verification testbenches. Experience in video codec, ISP, or display projects, including knowledge of advanced image processing algorithms, such as local tone mapping, noise reduction, motion estimation, transform coding, etc. Experience of Functional Safety product development for the Automotive market (applying standards such as ISO 26262 and/or IEC 61508). Experience with Continuous Integration flows. In Return: You will get to utilise your engineering skills to build support for the technologies and influence millions of devices for years to come. You will be able to drive and bring your ideas to a wider audience, while building your technical leadership and influencing skills. Equal Opportunities at Arm Apply Save Job View location Our Hiring Process

Job Overview: This position is an excellent opportunity for an experienced and highly motivated verification engineer to join the hardworking System IP team! This is a fast-paced technical role employing the latest hardware design and verification methodologies to develop complex and highly configurable hardware IP that sit at the heart of Arm-based Systems! This role is for the Coherent Mesh Network (CMN) interconnect product team. The Interconnect team develops the Arm Corelink Interconnect IP family. Our Interconnects and NoCs are designed for intelligent connected systems across a wide range of applications including networking infrastructure, automotive etc. The highly scalable IP is optimised for AMBA-compliant SoC connectivity and can be customised for multiple performance points. Responsibilities: You will specify and develop new hardware verification testbenches for future generation hardware IP. You will improve existing testbenches to increase performance, quality and efficiency. You will also identify areas for improvement in processes and methodologies, then implement those changes to advance our best-practises and state of the art for hardware verification. The responsibilities of a member of the Verification team are: Reviewing and assessing proposed design changes from a verification complexity point of view Investigating and scripting new verification flows and optimising existing ones Analysis of data from simulation runs using machine learning and data science techniques to drive efficient bug discovery and debug Developing methodology and deploying within the group and having full ownership of verification closure and mentoring other members of the team. Close collaboration with other Arm engineering teams leading to high quality IP that works well in a complete system. Required skills and experience: 4+ years hardware verification experience You can demonstrate experience in working with constrained-random verification including ownership of a suitably complex verification environment. Experience of architecting and implementing functional verification environments for complex IP. Experience developing re-usable and scalable code whilst having good knowledge of UVM. Strong scripting skills being able to develop scripting to support new flows. Proven software engineering skills including understanding of object-oriented programming, data structures, and algorithms. You are familiar with the tools and processes for developing testbenches and finishing all aspects of the verification process. Strong communication skills and ability to work well as part of a team. Dedicated with a focused approach to problem analysis and solving. Strong experience in planning and estimation. "Nice to Have" skills and Experience : Experience with protocols such as AMBA CHI, AMBA AXI or PCI Express Experience with Memory Management Units (MMUs) Experience with cache coherence protocols Experience in Formal Verification testbenches is a plus. In Return: Arm is committed to global talent acquisition, offering an attractive relocation package. With offices around the world, Arm is a diverse organisation of dedicated, creative and highly talented engineers. By enabling a dynamic, inclusive, meritocratic, and open workplace, where all our people can grow and succeed, we encourage our people to share their unrivalled contributions to Arms success in the global marketplace. We are an Equal Opportunity Employer, value diversity at our company and do not discriminate against any employee or applicant for employment on the basis of race, colour, gender, age, national origin, religion, sexual orientation, gender identity, status as a veteran, and basis of disability or any other federal, state or local protected class. Equal Opportunities at Arm Apply Save Job View location Our Hiring Process

Responsibilities As a creative Design Constraints Engineer, you will be part of the Front-End Design team, developing, validating , optimizing , and handing off constraints for complex SoCs, ensuring robust timing closure and seamless integration across the various stages of SOC design cycle. Your key responsibilities will include creating and maintaining Design constraints, validating them using industry standard STA tools and handing off to the Implementation teams. You will closely work with the Design team to capture the Design constraints. You will be validating these constraints using industry standard constraint validation tools like Time Vision and other equivalent tools. You will partner with the Implementation teams to resolve timing and constraint-related issues . You will also contribute to developing and enhancing the design methodologies used by the team. You will guide and support other members of the team as needed to enable the successful completion of project activities. Required Skills and Experience: Bachelor s or master s degree on Electrical & Electronics Engineering, VLSI or an equivalent discipline. Experience of 8+ years working in Design, Synthesis and Design constraints of complex Subsystems or SoCs Strong expertise in SDC syntax and timing constraint methodologies Expertise in Constraints development and validation tools such as Time Vision, or any equivalent Proficient in STA tools such as Synopsys PrimeTime , Cadence Tempus, or equivalent Experience in synthesis tools (Design Compiler, Genus) and PnR tools (ICC2, Innovus) preferred Familiarity with multi-mode multi-corner (MMMC) timing closure Proficient in Perl, Python, Tcl or other scripting language Good communication (written, verbal, presentations) skills. Desired Skills and Experience: Experience leading Synthesis and Design constraints for Subsystems or SoCs Knowledge of clock-domain crossing (CDC) and asynchronous design constraints Familiarity with formal verification of constraints. Exposure to high-speed interface constraints (DDR, PCIe, etc.). Knowledge of DFT and Physical Implementation Experience with ARM-based designs and/or ARM System Architectures Equal Opportunities at Arm Apply Save Job View location Our Hiring Process

Description Enphase Energy is a global energy technology company and a leading provider of solar, battery, and electric vehicle charging products. Founded in 2006, our innovative microinverter technology revolutionized solar power, making it a safer, more reliable, and scalable energy source. Today, the Enphase Energy System enables users to make, use, save, and sell their own power. Enphase is also one of the most successful and innovative clean energy companies in the world, with more than 80 million products shipped across 160 countries. Join our dynamic teams designing and developing next-gen energy technologies and help drive a sustainable future! Enphase is looking for experienced SoC Verification engineer to join our team in Bangalore India. The team is working on next generation Control ASIC in 22nm technology. This ASIC uses the ARM CM4 core, so experience with that core is a must. This SOC includes safety and security features into this next generation of MCU so a deep understanding of these SoC challenges is required. Similar to many other SOCs, our Control ASIC includes the CPU as mentioned above, a large Analog Front End (AFE) consisting of references, clocks, multiple ADCs, DAC functions, and analog muxes for the needed measurements in the Inverter, a Power Line Communications Modem (PLC), our proprietary Power Production control block and a host of other peripherals. This position is in our ASIC Engineering Team Reporting to the Senior Director of ASIC Engineering in Bangalore India. Responsibilities Working with our Internal/ Contract verification resources, IP designers and the Full Chip RTL engineers you will verify the new SOC design. You will also have responsibility set the verification methodology and verify the RT L developed by Enphase engineers and 3 rd party IP. Requirements Deep understanding and experience in SoC architecture and verification Specific experience verifying the ARM CM4 and all the surrounding IP, like: AHB, AXI, RAM and ROM controllers, DMA controllers. As our new MCUs will include security features for the first time, experience with the ARM Protection units is preferred. As these Control ASICs from Enphase contain a large AFE, experience with verifying high speed and high accuracy analog systems with a mixed signal methodology is an added advantage. Hands on experience with RISC-V verification will be an added advantage. Hands-on experience with UVM using SystemVerilog, Coverage driven verification methods, formal verification methods for IP/SoC functional verification is highly preferred. Knowledge of all the RTL verification methods, Gate level verifications, and mixed signal methodologies. Experience and ability to bring complex SOCs into production This position is based in Bangalore Credentials Proven track record based on at least 15+ years of experience

We are seeking a highly qualified and technically accomplished Principal Engineer / Engineering Manager with a consistent record in leading ASIC front-end methodologies across IP and SoC design and verification domains. The ideal candidate will bring VLSI experience, having successfully handled and scaled engineering teams, deployed sophisticated automation flows, and collaborated multi-functionally to deliver innovative solutions in the semiconductor domain. The role includes working with global design teams, vendors, and internal collaborators to develop, implement, and maintain IP/SoC design integration and verification methodologies. Responsibilities: Lead the development and deployment of sophisticated front-end methodologies for ASIC design, including Verification, SoC Integration, LEC, and Implementation processes. Drive and deliver customer-centric automation and tool development initiatives in collaboration with IT and software teams. Lead all aspects of migration strategies for major EDA tool transitions (e.g., CDC 0in to SpyGlass, RealIntent RDC to VC RDC). Collaborate closely with worldwide vendor R&D and AE teams to evaluate and deploy AI and automation solutions for ASIC workflows. Orchestrate RTL quality improvement initiatives including CDC SVA-based verification, Lint optimization, and formal verification improvements. Own vendor management responsibilities, including SOWs, important metric tracking, license management, tool evaluation, and documentation. Represent the company in technical conferences, working groups, and internal award forums. Required Skills and Experience : 15+ years of experience in VLSI ASIC design, verification, and methodology development. Confirmed leadership in setting up and handling high-performance teams and engineering charters. Expertise in EDA tools such as SpyGlass, VC RDC, LEC, Design Compiler, VCFSM, and formal verification tools. Proficiency in scripting and automation using Python, Perl, TCL. Strong understanding of Verilog/SystemVerilog and front-end design verification techniques (CDC, Lint, FV). Experience with tool migrations and performance benchmarking. Solid background in multi-functional collaboration with software, IT, and program management teams. Exceptional communication, collaborator management, and technical program leadership. "Nice to Have" Skills and Experience : Experience with AI flow optimization and automation in EDA environments. Familiarity with automotive and compute SoC programs and compliance processes. Awards or accolades demonstrating innovation, execution excellence, and peer recognition.