Why Join QFAI? Join a passionate team, dedicated to making a difference. We are a close-knit team, with strong mission, vision and values that guide our day-to-day. Recognition of work, respect, and our multicultural community are key aspects of the employee experience and contribute to our continued success. Would you like to be part of our story? Don't hesitate, come and join us! About this opportunity We are seeking a highly skilled and passionate Formal Verification Engineer to join our team working with the best in the Industry, developing innovative ASIC solutions for data center and AI Infrastructure. The ideal candidate will develop comprehensive formal test plans and be responsible for complete formal verification sign-off of single or multiple complex blocks. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success. Key Responsibilities: Contribute to Formal Verification applying and evangelizing state of the art Formal Verification Methodologies across IP-level, subsystem-level and SOC Level. Collaborate with Architecture and Design teams to develop formal specifications and implementations. Define formal verification scope, create formal environments, and achieve coverage sign-off using targeted formal verification techniques. Develop comprehensive formal test plans, including unique security requirement verification. Build reusable and scalable formal verification environments and deploy relevant tools. Evaluate and recommend EDA solutions for Formal Verification and drive improvements to methodologies and flows. Debug complex issues in RTL designs based on formal results and contribute to design improvements. Required Skills: Strong hands-on experience with Formal Verification tools (e.g., JasperGold, VC-Formal, Questa Formal). Experience writing formal properties using System Verilog Assertions (SVA) or Property Specification Language (PSL). Proven understanding of Formal Verification methodologies, complexity reduction techniques, and abstraction techniques. Fluency in hardware description languages, such as SystemVerilog. Proficiency in scripting languages such as Python, Perl, or Tcl within Unix/Linux environments. Education: Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field, or equivalent practical experience. Experience: 5+ years of experience in Design Verification, with at least 1 year in Formal Verification. QFocus AI Pvt Ltd is an Equal Employment Opportunity employer.
Role & responsibilities We are seeking a highly skilled and passionate Design Verification Engineer to join our team working with the best in the Industry, developing innovative ASIC solutions for data center and AI Infrastructure. As a design verification engineer, you will lead end-to-end design verification by creating verification plans, building test benches, and driving closure through functional and code coverage. Collaborate across design, modelling, emulation, and validation teams to ensure robust debug, high quality, and complete verification. Key Responsibilities: Define and implement verification plans, and build test benches for block, IP, sub-system, and SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality Debug, root-cause and resolve functional failures in the design, partnering with the Design team Review specifications, contribute to architecture discussions, and ensure verification completeness. Required Skills: Experience in Revision control systems like Mercurial (Hg), Git or SVN Architecting and implementing Design Verification infrastructure and executing the full verification cycle Development of Universal Verification Methodology (UVM) based verification environments from scratch Verifying ARM/RISC-V based sub-systems and SoCs Verifying CPU/GPU designs One or more of the following areas: SystemVerilog Assertions (SVA), Formal, and Emulation Standard protocols ( PCIe, AMBA, DDR , etc.) is a plus. Preferred candidate profile Education: Bachelors or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Experience: 5+ years of hands-on experience in SystemVerilog / UVM methodology 5+ years’ experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments QFocus AI Pvt Ltd is an Equal Employment Opportunity employer.