Design Verification Engineer

Role & responsibilities

We are seeking a highly skilled and passionate Design Verification Engineer to join our team working with the best in the Industry, developing innovative ASIC solutions for data center and AI Infrastructure. As a design verification engineer, you will lead end-to-end design verification by creating verification plans, building test benches, and driving closure through functional and code coverage. Collaborate across design, modelling, emulation, and validation teams to ensure robust debug, high quality, and complete verification.

Key Responsibilities:

• Define and implement verification plans, and build test benches for block, IP, sub-system, and SoC level verification
• Develop functional tests based on verification test plan
• Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
• Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality
• Debug, root-cause and resolve functional failures in the design, partnering with the Design team
• Review specifications, contribute to architecture discussions, and ensure verification completeness.

Required Skills:

• Experience in
• Revision control systems like Mercurial (Hg), Git or SVN
• Architecting and implementing Design Verification infrastructure and executing the full verification cycle
• Development of Universal Verification Methodology (UVM) based verification environments from scratch
• Verifying ARM/RISC-V based sub-systems and SoCs
• Verifying CPU/GPU designs
• One or more of the following areas: SystemVerilog Assertions (SVA), Formal, and Emulation
• Standard protocols (

  PCIe, AMBA, DDR

  , etc.) is a plus.

  Preferred candidate profile

Education:

Bachelors or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

Experience:

• 5+ years of hands-on experience in SystemVerilog / UVM methodology
• 5+ years’ experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
• Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments

QFocus AI Pvt Ltd is an Equal Employment Opportunity employer.