137 Ip Verification Jobs

HI All, Immediate hiring for VLSI Engineers for below location DV - SOC - BLR Location ( DDR, Ethernet) DV - Ip - HYD Location ( Pcie, Ethernet, DDR)

Expertise in Digital Verification Expertise in MAC Protocol: USB, WiFi , Bluetooth , PCIe Expertise in SOC / IP Verification Expertise in working on system Verilog assertions & test benches Expertise in working on OVM / UVM / VMM based verification flow Good knowledge in gate-level simulation, and Scripting languages like Python, TCL Must be a resident of India, preferably in Bangalore or Pune

Dear Candidate We have immediate job openings for Design verification openings Exp : 3-10 years Location : Bangalore NP : less than 45 days Job details : Develop and maintain UVM-based verification environments. Define and review verification test plans with architecture and design teams. Perform design verification using directed and constraint-random tests. Maintain regression runs and debug test failures with designers. Report and analyze verification coverage metrics. Drive verification to achieve full coverage goals. Own verification of IP blocks, sub-systems, and top-level environments. Thanks Gayathri

Dear Candidate We have immediate job openings for Design verification openings Exp : 3-10 years Location : Bangalore NP : less than 45 days Job details : Develop and maintain UVM-based verification environments. Define and review verification test plans with architecture and design teams. Perform design verification using directed and constraint-random tests. Maintain regression runs and debug test failures with designers. Report and analyze verification coverage metrics. Drive verification to achieve full coverage goals. Own verification of IP blocks, sub-systems, and top-level environments. Thanks Gayathri

Work on creating verification plan for RISC-V based application specific IP Build Standalone IP test bench using System Verilog Develop test cases, coverage model and assertions needed to ensure functional correctness of the Design Under Test (i.e., IP/SOC) Use the IP/SOC RTL in system verilog based logic verification environment complete the functional verification Generate functional and code coverage metrics, collaborate with IP developers on the correctness completeness of IP functionality. Deliver the functional test vectors needed to be used for post-silicon validation. Be the single point contact for the concerned IP Verification and enable the Tapeout for all control ASICs of Enphase Who you are and what you bring Proficient in UVM, Verilog, SystemVerilog, C, Python. Working on the HW/SW interface. Strong understanding and experience of logic verification environment (UVM System Verilog) Strong understanding of RISC-V architecture functional verification Experience with processor toolchains (compiler, assembler, simulator). Experience with processor verification. Directed tests and random program generated tests. Experience with functional processor simulators. Experience with verification of secure processor boot code. Experience with Floating point instructions implementation verification in micro controller based ASIC designs Ability to quickly adapt to other categories of C-based/System Verilog based IP verification Experience and ability to bring complex SOCs into the physical world and into production. Excellent problem solving skills, written verbal communication skills Logic Verification #Embedded C Verification #ARM #Boot. Prior hands on work experience of at least 8 years in Logic IP Verification based on System Verilog.

Required Skills & Experience 3 to 5 years of experience in IP/Subsystem/SoC design verification. Strong knowledge in SystemVerilog, UVM , and functional coverage. Understanding of digital design concepts (FSMs, pipelines, FIFOs, memory, clock/reset domains). Experience with protocols like AMBA (AXI/AHB/APB) or similar. Familiarity with assertion-based verification (SVA) . Hands-on with EDA tools (Cadence Xcelium, Synopsys VCS, Mentor Questa, or equivalent). Proficiency in debug tools (Verdi, SimVision, DVE). Strong problem-solving and debugging skills. Scripting skills in Python/Perl/TCL/Makefile for automation. Good to Have (Optional) Exposure to DFT/DFX verification, UPF/power-aware flows, or GLS . Experience with high-speed interfaces (PCIe, USB, DDR, UCIe, etc.) . Familiarity with C/C++/embedded software-driven verification . Role & responsibilities Location: Bangalore Looking for immediate joiners.

Role & responsibilities Job Summary: We are seeking a highly skilled ASIC Design Verification Engineer with extensive experience in various verification methodologies. The ideal candidate will have a deep understanding of functional, formal, CPU, and GLS verification. The role requires expertise in SoC and IP level verification, particularly with high-speed protocols. This position demands a thorough knowledge of verification techniques, tools, and processes to ensure the highest quality in our ASIC designs. Key Responsibilities: - Develop and execute comprehensive verification plans for ASIC designs. - Utilize various verification methodologies, including functional, formal, CPU, and GLS verification. - Conduct SoC level verification, ensuring integration and functionality of multiple IPs. - Implement IP verification strategies for high-speed protocols such as PCIe, USB, Ethernet, DDR, MIPI, and others. - Collaborate with design and architecture teams to understand design specifications and requirements. - Create, maintain, and enhance testbenches and simulation environments. - Perform coverage analysis and closure to ensure all scenarios are tested. - Debug and resolve complex design and verification issues. - Document and present verification results to cross-functional teams. - Mentor junior engineers and contribute to the continuous improvement of verification processes. --- Required Skills and Qualifications: - **Experience:** 5+ to 20+ years in ASIC design verification. - **Education:** Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. - **Languages and Methodologies:** - Proficient in SystemVerilog, UVM (Universal Verification Methodology), C/C++. - Strong understanding of OO (Object-Oriented) concepts. - Experience in writing assumptions, sequences, virtual sequences, tests, and coverage closures. - Knowledge of UVM factory and configurations, UVM callbacks. - **Tools:** - Simulation tools: VCS, ModelSim, Questa, etc. - Formal verification tools: JasperGold, VC Formal, etc. - GLS tools: Synopsys, Cadence, or Mentor tools. - Debug tools: Verdi, DVE, SimVision, etc. - Coverage tools: Specman, Coverage Analyzer, etc. - **Protocols:** - High-speed protocols: PCIe, USB, Ethernet, DDR, MIPI, SATA, SerDes, etc. - SoC level protocols: AMBA (AXI, AHB, APB), ARM CoreSight, etc. - **Techniques:** - Assertion-based verification. - Random and directed test methodologies. - Power-aware verification. - Performance and throughput analysis. - Emulation and prototyping. --- SoC Level Verification: - **Responsibilities:** - Verify the integration of various IP blocks within the SoC. - Ensure proper functionality and communication between different IPs. - Utilize techniques such as simulation, emulation, and formal methods. - Perform power and performance analysis. - Validate system-level features and use cases. - **Required Knowledge:** - Advanced knowledge of SoC architectures. - Experience with ARM cores and subsystems. - Familiarity with interconnects and communication protocols. --- Subsystem Level Verification: - **Responsibilities:** - Verify individual subsystems such as memory controllers, interconnects, and peripheral interfaces. - Ensure subsystem integration within the larger SoC context. - Develop and execute detailed verification plans specific to each subsystem. - **Required Knowledge:** - Deep understanding of subsystem-level protocols and interfaces. - Experience with verification of memory interfaces (DDR, LPDDR), high-speed interfaces (PCIe, Ethernet), and peripheral interfaces (I2C, SPI, UART). --- Soft Skills: - Strong analytical and problem-solving skills. - Excellent communication and collaboration abilities. - Ability to work independently and as part of a team. - Leadership skills for mentoring junior engineers. Preferred Qualifications: - Prior experience in leading verification projects. - Contributions to industry standards or verification methodologies. - Publications or patents in the field of ASIC verification.

Job Title: Lead Design Verification Engineer Location: m Bangalore Job Type: Full-time Experience Level: 7+ years Department: Hardware Engineering / VLSI Design Job Summary: We are seeking a highly experienced Lead Design Verification Engineer to lead verification efforts for complex digital designs. The ideal candidate will drive testbench architecture, verification planning, and execution for ASIC/SoC or FPGA-based designs, ensuring first-time-right silicon or system functionality. You will work closely with RTL design, DV, and system engineering teams to deliver high-quality products. Key Responsibilities: Lead and drive the verification strategy, planning, and execution for IP, subsystem, or full-chip level. Define and implement constrained-random, directed, and coverage-driven verification methodologies (UVM/SystemVerilog preferred). Develop and maintain scalable and reusable testbench components. Mentor and guide junior verification engineers in testbench architecture, debugging, and coverage closure. Collaborate with RTL designers, architects, and firmware/software teams to understand design intent and develop test plans. Own and track functional coverage metrics and ensure 100% coverage goals are met. Drive regular reviews of verification status, risks, and issues with stakeholders. Support post-silicon validation teams with test vectors, debugging, and failure analysis. Required Qualifications: Bachelors or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 7+ years of industry experience in digital design verification. Strong expertise in SystemVerilog, UVM, and advanced verification methodologies. Experience in testbench architecture, test planning, and constrained-random stimulus generation. Solid understanding of digital design concepts, SoC/ASIC design flows, and bus protocols (e.g., AXI, AHB, PCIe, etc.). Hands-on experience with simulation tools (VCS, Questa, etc.) and coverage analysis tools. Excellent debugging and problem-solving skills using waveform viewers and assertion-based techniques. Familiarity with scripting languages such as Python, Perl, or TCL for automation. Strong communication and leadership skills with experience leading small to mid-sized teams. Preferred Qualifications: Experience in formal verification techniques. Experience with emulation, FPGA prototyping, or post-silicon bring-up. Exposure to power-aware or low-power verification (UPF/CPF). Knowledge of hardware security, safety, or compliance standards (ISO 26262, DO-254, etc.) is a plus. Familiarity with CI/CD flows and version control (Git, Jenkins, etc.). Why Join Us: Work on cutting-edge technologies and next-generation chip designs. Opportunity to lead high-impact projects and influence verification strategy. Collaborative and innovative work environment. Competitive salary, benefits, and career growth opportunities.

Job Description: We are seeking Design Verification Engineers with 515 years of experience in SystemVerilog, UVM, and SoC/IP-level verification. The role involves building scalable verification environments, driving coverage closure, debugging complex issues, and ensuring robust design quality. Key Responsibilities & Requirements: Strong experience in ASIC/IP/SoC design verification (block/IP/SoC level). Expertise in SystemVerilog, UVM, testbench architecture, and reusable verification components. Ability to create and execute detailed verification plans. Skilled in constrained-random verification, functional coverage, assertions, and scoreboarding. Solid knowledge of AMBA protocols (AXI, AHB, APB). Proficiency with simulation tools (VCS, Questa, XSIM, etc.) and debug tools (Verdi, DVE). Strong background in testcase development, coverage closure, and issue debugging. Experience with assertion-based and formal verification techniques. Hands-on in developing block-level and SoC-level verification environments. Scripting skills in Python, Perl, or TCL for automation.

Responsibilities: * Collaborate with cross-functional teams on design verification strategies. * Develop UVM testbenches for PCIe, SOC, IP, DDR, USB, Ethernet interfaces.

General Summary: QCT's Bangalore Wireless R&D(WRD) HW team in Bangalore is looking for experienced Wireless HW design verification engineers to work on Qualcomms best in class chipsets for mobile phones, wearables and IOT . Candidate will be working with ASIC designs on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies. In this role of WRD Verification Engineer, you will be verifying Wifi and/or Modem from both TX and RX perspective. The responsibilities will majorly include : Understanding of Wireless systems PHY TX and RX design paths, Algorithms that control the various aspects of wireless systems. Own complete IP/Block/SS level DV. Own end to end DV tasks from design analysis, Verification Plan development , Coding Test bench and test cases, write assertions, running simulations and achieving all coverage goals. Explore innovative DV methodologies (formal, simulation and emulation based) to continuously improve the quality and efficiency of test benches. Successful candidate will be required to collaborate with worldwide design, architecture teams and other stake holder to achieve all project goals. Hence, strong communication skills are a must. Skills/Experience: 2-10 years of strong experience in design verification Strong knowledge of System Verilog/UVM based verification skills & experience with assertion & coverage-based verification methodology Proven experience of building or maintaining a medium to complex SV/UVM environments Proven experience of writing efficient constraint random tests Prior Experience in verifying WIFI, Modem PHY layer is a strongly desirable. Strong debugging and analytical skills and independent problem-solving ability Proficient in debugging RTL/TB issues using Verdi or similar tools Experience in formal / static verification methodologies will be a plus Good understanding of Wireless protocols, Modem/Wifi Standards is a plus Experience with Power Aware verification, GLS, and scripting languages such as Perl, Python is a plus. Experience in formal / static verification methodologies will be a plus Preferred Qualifications: Understanding of Wireless protocols, Modem/Wifi Standards Experience in IP verification of DSP related HW blocks. Knowledge on scripting languages such as Perl and(or) Python Education Requirements BE/BTech/ME/MTech/MS Communication Engineering and/or Electronics, VLSI , from reputed university preferably with distinction Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

You have an exciting opportunity with Tessolve Semiconductor in Bangalore for the roles of RTL Design Engineer and Design Verification Engineer. For the position of RTL ASIC Engineer, you should have at least 7 years of work experience in ASIC/IP Design with expertise in Logic design and RTL design. Your responsibilities will involve IP design and integration, along with proficiency in tools such as Lint and CDC for ASIC development. Knowledge of Synthesis and understanding of timing concepts would be advantageous. Additionally, familiarity with AMBA protocols like AXI, AHB, APB, and SoC clocking/reset architecture is preferred. As a Design Verification Engineer, you are required to have 5 to 20 years of experience. You should be well-versed in IP verification using SV/UVM, SOC Verification using C/SV, and Third Party VIP Integration. Your expertise in Interconnect Protocols such as AHB, AXI, APB, SOC Interfaces like GPIO, SPI, I2C, UART, High-Speed Serial Interfaces including PCIe Gen 3/4, USB, MIPI, and Memory Interfaces like DDR or HBM I/O will be crucial. Proficiency in Coverage Closure (Code, Functional, Toggle) and tools like Synopsys VCS or Cadence Incsive is essential. Experience in Technical Documentation, Foundry Porting, and Technology Library Conversion related to Verification will be advantageous. If you meet the requirements and are interested in these positions, please share your updated CV with Gayatri Kushe at gayatri.kushe@tessolve.com or contact at 6361542656. Thank you for considering this opportunity with Tessolve Semiconductor.,

Wafer Space is looking for smart and enterprising Design Verification engineers to join the team and engage in cutting-edge work within a dynamic and exciting work environment. We are currently involved in various in-house turnkey projects and client site projects, many of which require comprehensive verification from specification to closure, including the development of complete DV environments in SV-UVM. As a Design Verification Engineer at Wafer Space, your responsibilities will include building SV, SV UVM, OVM based environments and working with a variety of networking and other protocols. The role requires 3 to 7 years of experience in IP verification, with a strong background in SV/UVM based verification projects and excellent debugging skills. Experience in constructing components such as Scoreboard, functional coverage, and writing sequences using SV/UVM based Verification environments is essential for this position. Additionally, expertise in one of the following areas is highly desirable: - Experience in Video/Display domain, particularly DP, oLDI, MIPI CSI/DSI - Experience in high-speed protocols such as USB3, PCIe, MIPI, Unipro, etc. If you are passionate about design verification, possess the required skills and experience, and are seeking an opportunity to work on challenging projects in a collaborative and engaging environment, we would love to hear from you. Join Wafer Space and be a part of our innovative team where work is always fun and exciting.,

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the worlds mostinnovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as theyprovide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days arethe same. About The Role About The Role : You will be part of the team verifying IPs and SoCs leading to first Si success. Manage and lead a team of Verification engineers IP verification is coverage driven using latest industry standard methodologies and HVLs. Work involves defining verification strategy, writing test plans, developing efficient test benches and test cases. Code coverage, Functional coverage and assertions are desired. ARM based SoC verification experience is an added advantage. Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell Scripts etc. is a great plus. Multiple positions with emphasis on AMS and Power aware verification. Should have worked on GLS. Primary Skills: Verilog, SV, UVM/OVM, IP Verification, SoC Verification, scripting Perl, Python, Shell, and Tcl. Secondary Skills: Test bench / model / VIP development, Functional coverage, GLS, LEC, Emulation, AMS, ARM, Protocols AHB/AXI/APB, Ethernet, USB, PCIe, I2C, SPI, CAN, Mipi CSI/DSI, LPDDR.

Job Description Responsibilities : - Expertise in Digital Verification - Expertise in Functional Verification - Expertise in SOC / IP Verification - Expertise in working on system Verilog assertions & test benches - Expertise in working on OVM / UVM / VMM based verification flow - Expertise in working on ARM processor - Expertise in working on AMBA bus protocols (AXI, AHB, APB) - Expertise in CXL or PCIe Protocol Verification - Expertise in simulation tools (VCS, ModelSim, Questa) - Expertise in driving Verification Strategy, writing Test Plan, developing Test Bench, Test cases. - Expertise in analysing Code Coverage, Functional Coverage and Assertions. - Expertise in verification of complex SoCs. - Expertise in Test Plan creation and Verification technologies like Code Coverage, Functional coverage, assertion based verification. - Expertise in Verification of complex datapath, DSP based ASICs - Expertise in MAC Protocol: USB, WiFi , Bluetooth , PCIe is mandatory for Pune location - Good knowledge in gate-level simulation, and Scripting languages like Python, TCL - Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan are the preferred work locations - Preferred resources with valid regional work permit. Location - Bangalore/Pune/Beijing,Dallas,Romania,Taiwan

Responsibilities : - Expertise in Digital Verification - Expertise in Functional Verification - Expertise in SOC / IP Verification - Expertise in working on system Verilog assertions & test benches - Expertise in working on OVM / UVM / VMM based verification flow - Expertise in working on ARM processor - Expertise in working on AMBA bus protocols (AXI, AHB, APB) - Expertise in CXL or PCIe Protocol Verification - Expertise in simulation tools (VCS, ModelSim, Questa) - Expertise in driving Verification Strategy, writing Test Plan, developing Test Bench, Test cases. - Expertise in analysing Code Coverage, Functional Coverage and Assertions. - Expertise in verification of complex SoCs. - Expertise in Test Plan creation and Verification technologies like Code Coverage, Functional coverage, assertion based verification. - Expertise in Verification of complex datapath, DSP based ASICs - Expertise in MAC Protocol: USB, WiFi , Bluetooth , PCIe is mandatory for Pune location - Good knowledge in gate-level simulation, and Scripting languages like Python, TCL - Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan are the preferred work locations - Preferred resources with valid regional work permit. Location - Bangalore/Pune/Beijing,Dallas,Romania,Taiwan

Role & responsibilities 4+ Years of experience in Design Verification Expertise in SV & UVM Experience in any one of the following protocols like PCIe, Ethernet, DDR, USB, AXI etc., Excellent Communication

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBLITIES: Strong knowledge in IP/SOC design methodologies. Power aware verification expertise using UPF (Unified Power Format) Sound knowledge of RTL/SOC design/integration with Verilog/system Verilog Mentoring juniors and enhancing their skill set Must have strong knowledge of AMBA AHB/AXI protocol Working knowledge on code coverage, functional coverage, Lint, CDC etc IP development and coding using standard coding guide lines knowledge Excellent communication skills. Must be able to particpate lead in global meetings Soft skills to be able to work in a cross functional international team digital and software design engineers Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requireme PREFERRED EXPERIENCE: 6+ Years for experience Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Experience with power-aware verification methodologies and UPF Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions.

The preferred candidate will have proven experience verifying complex design blocks at the IP, Sub-system or SoC level using System Verilog/UVM or related technologies. He or she should be comfortable creating and executing on test plans in collaboration with design and verification colleagues in a metric-focused environment. KEY RESPONSIBILITIES: Develop and enhance System Verilog / UVM-based testbenches to verify new features for client, server, graphics, and semi-custom interconnects. Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture. Understand TestBench Architecture and develop expertise in TestBench Verification Components. Mentor junior engineers. PREFERRED EXPERIENCE: Proficient in IP or Sub-system level ASIC verification Architected and developed complex verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar. Exposure to RTL design, software development, formal verification, or other related domains. Experience in UVM TestBench Development for complex designs preferred. Experience in RAL is preferred

This job might be for you if You enjoy solving problems. You love taking on difficult challenges and finding creative solutions. You dont know the answer but will dig until you find it. You communicate clearly. You write well. You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference. You can impress our customers with your enthusiasm to solve their issues (and solve them!) Job Overview We are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs. Job Description Lead and manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans. Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR and HBM Conduct Gate-level simulations, and power-aware verification using Xprop and UPF.Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams. Analyze and implement System Verilog assertions and coverage (code, toggle, functional). Provide mentorship and technical guidance to junior verification engineers.Manage and lead a dynamic team of verification engineers, fostering a collaborative and innovative work environment. Ensure verification signoff criteria are met and documentation is comprehensive.Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines. Adhere to quality standards, implement good test practices, and contribute to the continuous improvement of verification methodologies. Experience with verification tools from Synopsys and Cadence, including VCS and Xsim. Integration of third-party VIPs (Verification IP) from Synopsys and Cadence. Qualifications Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. ORMasters degree in computer science, Electrical/Electronics Engineering, or related field. ORPhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design Verification. Expertise in UVM (Universal Verification Methodology) and System Verilog. Prior experience working on IP level and SOC level verification projects. Proficient in verification tools such as VCS, Xsim, waveform analyzers, and third-party VIP integration (e.g., Synopsys VIPs and Cadence VIPs). Hands-on experience with UFS (Universal Flash Storage), Ethernet, PCIe, CXL, MIPI protocols.Solid understanding of low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols. Experience in DDR, HBM, Gate-level simulations, and power-aware verification using Xprop and UPF. Proficiency in scripting languages such as shell, Makefile, and Perl. Strong understanding of processor-based SOC verification, including native, Verilog, System Verilog, and UVM mixed environment. C-System Verilog handshake and writing C test cases for bootup verification. Excellent problem-solving, analytical, and debugging skills.

Role & responsibilities Key Responsibilities: Develop and execute test plans for high-speed protocols such as PCI, PCIe (Gen1 to Gen5), USB (2.0/3.0), Ethernet (10/100/1G/10G), and MAC. Write and maintain SystemVerilog/UVM testbenches for functional verification. Collaborate with design teams to understand architecture and develop verification strategies. Debug RTL issues, analyze simulation failures, and provide comprehensive bug reports. Perform coverage analysis (code and functional) and drive coverage closure. Integrate VIPs (Verification IPs) and ensure compliance with industry standard protocol specifications. Work on assertions, checkers, and monitor development for protocol features. Participate in design and verification reviews, and contribute to continuous improvement. Required Skills: Strong expertise in SystemVerilog, UVM methodologies. Solid understanding of PCIe, USB, Ethernet/MAC protocols . Experience in testbench architecture, test planning, and constrained-random verification . Knowledge of debugging tools like SimVision , Verdi , or similar. Exposure to protocol compliance testing and formal verification is a plus. Experience with scripting languages (Python, Perl, Tcl, Shell) for automation. Preferred candidate profile

At Cadence, we are seeking individuals who are passionate about technology and aspire to lead and innovate in the field. As a design and verification engineer, you will play a crucial role in making a significant impact on the world of technology. The ideal candidate should hold a BE/BTech/ME/MTech degree in Electrical, Electronics, or VLSI with a minimum of 8 years of experience in Design Verification, specifically with SV/UVM. A strong foundation in functional verification fundamentals, including environment planning, test plan generation, and environment development, is essential for this role. In this position, you will be responsible for verifying complex designs and leading projects from concept to verification closure. Proficiency in UVM and System Verilog coding, as well as experience in functional verification environment development, are key requirements for this role. Additionally, prior experience in IP verification of memory IP such as DDR, HBM, or GDDR would be considered a valuable asset. Join us at Cadence, where we are committed to tackling challenges that others may find insurmountable. Your contributions will be instrumental in solving problems that truly matter in the realm of technology.,

Experience : 5+years Location : Bangalore Job Description: You will be part of the team verifying IPs and SoCs leading to first Si success. Manage and lead a team of Verification engineers IP verification is coverage driven using latest industry standard methodologies and HVLs. Work involves defining verification strategy, writing test plans, developing efficient test benches and test cases. Code coverage, Functional coverage and assertions are desired. ARM based SoC verification experience is an added advantage. Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell Scripts etc. is a great plus. Multiple positions with emphasis on AMS and Power aware verification. Should have worked on GLS. Primary Skills: Verilog, SV, UVM/OVM, IP Verification, SoC Verification, scripting Perl, Python, Shell, and Tcl. Secondary Skills: Test bench / model / VIP development, Functional coverage, GLS, LEC, Emulation, AMS, ARM, Protocols AHB/AXI/APB, Ethernet, USB, PCIe, I2C, SPI, CAN, Mipi CSI/DSI, LPDDR. Show more Show less

The position is with one of our IDM client. As a Functional Verification Engineer, you will be responsible for verifying RTL designs using SystemVerilog and UVM. You will develop testbenches, build reusable components, and ensure complete functional coverage of IPs or SoC-level designs. Key Responsibilities: - Develop and maintain UVM-based testbenches for IP/subsystem/SoC verification - Create test plans from microarchitecture/design specifications - Write and debug directed and constrained-random tests - Implement functional coverage, assertions (SVA), and checkers - Run regressions using simulators like VCS, Xcelium, or Questa - Interface with RTL, DFT, and Firmware teams to track and resolve bugs - Analyze waveforms (using DVE/SimVision), track bugs, and maintain bug databases (JIRA, Bugzilla) Education: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design Job Types: Full-time, Permanent Schedule: Day shift Work Location: In person,

We are looking for passionate individuals who are ready to take on challenges in IP/ASIC/SOC Verification. We have open positions at all levels including Engineer, Senior Engineer, Lead, Manager, Director, and Head of Verification. The ideal candidate will have 3-20 years of experience in the field. In this role, you will be an integral part of the ASIC verification team. Your primary responsibility will be the functional verification of ASIC IPs. Our verification methodology utilizes cutting-edge techniques and tools such as coverage-driven constrained random verification and formal verification. Our design and implementation of verification environments heavily rely on object-oriented architectures and frameworks. We are seeking individuals with expertise and aptitude in verifying functions like image processing, video compression, and computer vision. As a verification engineer, you will also get the opportunity to delve into the algorithms that drive the hardware. The ideal candidate is an experienced engineer with exceptional programming skills and a genuine interest in ASIC verification. Our verification environments are complex, so a strong ability to comprehend, implement, and maintain intricate software systems is essential. Previous experience in hardware verification using SystemVerilog, UVM, low power verification, and formal methods would be advantageous. Analytical thinking, systematic approach, and attention to detail are traits we highly value in potential candidates. If you meet these criteria and are ready for an exciting challenge in the field of ASIC verification, we would love to hear from you. References are most appreciated. (ref:hirist.tech),