470 Soc Verification Jobs

Understand the design specification, Power On Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verificationChip reset sequence and initialization, and/or Power management. Knowledge of verification methodology, Knowledge of HDLs (VHDL,Verilog) Good programming skills in C++/C/OOPs, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge High Speed Serdes Phy, PCIe, DDR, Ethernet protocol Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Lead the development of the verification plans, environment, testbenches and writing testcases to verify Cache structures & protocols in processor. Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Work with development team to ensure coverage criteria is met. Required education Master's Degree Required technical and professional expertise 6 + years of experience in Functional Verification of processors or ASICs. 3+ years of experience in the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processor Cache (L2/L3) Coherency, Memory Hierarchy Verification Minimum one full life cycle leadership experience of a processor/SoC verification flow with focus on Cache Coherency Verification Developed test-plans and test strategies for IP/unit/block level verification of Cache Coherency structures in processor/SoC Good object-oriented programming skills in C++/SV, scripting languages like Python/Perl. Knowledge of functional verification methodology like UVM/OVM Knowledge of HDLs (VHDL/Verilog) Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenarios, debugging and triaging fails Experience in driving verification coverage closure. Preferred technical and professional experience Stress testing and ability to identify corner case scenarios. Good understanding of computer system architecture and microarchitecture.

* As a Formal verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. * Develop the verification environment and test bench and creating testcases.* Develop skills in IBM Formal verification tools and methodologies. * Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Required technical and professional expertise * 5 - 10 years of relevant industry experience * Proven experience in Formal/Functional Verification - Demonstrated execution experience of verification of logic blocks verification. * Knowledge of formal methodology, Knowledge of HDLs (Verilog, VHDL, SV), Good programming skills in python, processor core u-arch skills * Exposure in developing testbench environment, debugging and triaging fails. Preferred technical and professional experience * Good communication skills and be able to work effectively in a global team environment. * Drive verification coverage closure, lead verification team. * Drive complex scenarios, participate in High level design discussions. * Track record in leading teams.

HI All, Immediate hiring for VLSI Engineers for below location DV - SOC - BLR Location ( DDR, Ethernet) DV - Ip - HYD Location ( Pcie, Ethernet, DDR)

Job Description Play senior verification member role and development of verification of SoC level scenarios and IP integration verification Owning the Testbench architecture and development Thriving to bring innovation in Verification Methodologies and optimizing the flow and turn around time. Key contributor for post silicon validation support, pattern generation. Develop tests , Debug failures and perform root cause analysis Develop/execute/debug test cases in simulation and Pre-Sillicon Validation on palladium Collaborate with validation and FW teams. Working closely with different teams within organization and tracking bugs to closure Be involved in SOC bring-up and Pre/Post Si Validation Qualifications Required Skills/Experience: B.E/B.Tech with 14+ years of experience in SoC verification/post silicon debug Excellent design and verification concepts Experience in C based So

We are looking for Design verification Engineer with Soc, DDR/ Ethernet Exp Exp: 7+yrs Loc: BLR If Interested, please share your Profile to my mail id sushma.vunnam@modernchipsolutions.com

Expertise in Digital Verification Expertise in MAC Protocol: USB, WiFi , Bluetooth , PCIe Expertise in SOC / IP Verification Expertise in working on system Verilog assertions & test benches Expertise in working on OVM / UVM / VMM based verification flow Good knowledge in gate-level simulation, and Scripting languages like Python, TCL Must be a resident of India, preferably in Bangalore or Pune

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SE NIOR SILICON DESIGN ENGINEER THE ROLE (SOC Verification Engineer: GDP DV ): Work on SOC level verification activities for GDP (PCIE,USB,Ethernet,I2C,I3C,Uart,SPI) and subsystem or signature IP's in the complex SOC. He will be responsible for verifying and integration. Add on responsibility SOC Integration after having co-ordination with IPs, SOC (Design, DFT & PD) teams. To take complete IP integration responsibility, including the deployment verification. Understand spec, interact with customer, team members, lead and come up with testplan, code testcases, checkers, UVM agents, scoreboards and assertions. THE PERSON: Engineer with strong self-driving ability. Need excellent communication skills (both written and oral) Strong problem-solving skills, go to person for UVM coding, Testcase coding, checkers and assertions. KEY RESPONSIBILITIES: Understanding Ips like (PCIE,USB,Ethernet,I2C,I3C,UART,SPI) IP deployment to complex SOCs and get the integration testing done. Testcase coding, Debugging issues, regressions, UVM agent coding, checkers coding, scoreboard coding and Assertions coding. PREFERRED EXPERIENCE: Knowledge of High speed peripheral (PCIE,USB,Ethernet) and Low speed peripherals (I2C,I3C,UART,SPI) Expertise in IP, Subsystem and SOC Verification with specialization in Integration, verification tools Strong hands-on experience in different SOC Verification activities, UVM, System Verilog, kv, X86, C++, HW/SW co-verification, Test plan review, Debug/triage, Coverage, Strong Problem Solving, Automation and Debugging Skills, System bus protocol understanding including some of the common IPs like ACE, CHI, AXI, PCIe, DDR, memory controller etc. Comfortable with design/verification tools and flows like VCS, Verdi, SOC Connectivity, SV assertions, HW-SW co-simulations, UPF/CPF flows etc. Strong understanding of System integration, Make file flow, Verification Methodologies, Boot up sequence. JIRA based project management is a plus. ACADEMIC CREDENTIALS: BE/B.Tech/ME/MTECH/MS or equivalent in ECE/EEE/CSE 5-10 years of strong DV experience in IP, Sub System & SOC Verification, IP deployment/integration. #LI-SR4 Benefits offered are described: . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

Role Overview: As an experienced SoC Verification Engineer at Enphase Energy in Bangalore, India, you will be working on the next generation Control ASIC in 22nm technology. Your role will involve ensuring the verification of the new SOC design, setting the verification methodology, and collaborating with internal/contract verification resources, IP designers, and Full Chip RTL engineers to verify the RTL developed by Enphase engineers and 3rd party IP. Your deep understanding and experience in SoC architecture and verification will be crucial to the success of the project. Key Responsibilities: - Verify the new SOC design and set the verification methodology - Collaborate with internal/contract verification resources, IP designers, and Full Chip RTL engineers - Ensure verification of RTL developed by Enphase engineers and 3rd party IP - Utilize hands-on experience with UVM using SystemVerilog and coverage-driven verification methods - Apply formal verification methods for IP/SoC functional verification - Demonstrate knowledge of RTL verification methods, gate-level verifications, and mixed signal methodologies - Use specific experience in verifying the ARM CM4 and surrounding IP, such as AHB, AXI, RAM and ROM controllers, and DMA controllers - Apply experience in verifying high-speed and high-accuracy analog systems with a mixed signal methodology - Bring complex SOCs into production Qualifications Required: - At least 15+ years of proven experience in SoC verification - Deep understanding and experience in SoC architecture and verification - Experience with ARM CM4 and surrounding IP like AHB, AXI, RAM and ROM controllers, and DMA controllers - Hands-on experience with UVM using SystemVerilog and coverage-driven verification methods - Knowledge of formal verification methods for IP/SoC functional verification - Familiarity with RTL verification methods, gate-level verifications, and mixed signal methodologies - Ability to bring complex SOCs into production - Hands-on experience with RISC-V verification will be an added advantage (Note: Additional details about the company were not explicitly mentioned in the provided job description.),

Dear Candidate We have immediate job openings for Design verification openings Exp : 3-10 years Location : Bangalore NP : less than 45 days Job details : Develop and maintain UVM-based verification environments. Define and review verification test plans with architecture and design teams. Perform design verification using directed and constraint-random tests. Maintain regression runs and debug test failures with designers. Report and analyze verification coverage metrics. Drive verification to achieve full coverage goals. Own verification of IP blocks, sub-systems, and top-level environments. Thanks Gayathri

Dear Candidate We have immediate job openings for Design verification openings Exp : 3-10 years Location : Bangalore NP : less than 45 days Job details : Develop and maintain UVM-based verification environments. Define and review verification test plans with architecture and design teams. Perform design verification using directed and constraint-random tests. Maintain regression runs and debug test failures with designers. Report and analyze verification coverage metrics. Drive verification to achieve full coverage goals. Own verification of IP blocks, sub-systems, and top-level environments. Thanks Gayathri

Desired Profile : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering. Expertise in execution and debugging of test-suites at the GPU sub-system level Expertise in GLS (Gate-Level Simulation) Expertise in writing assertions and test benches using system verilog Expertise in UVM methodologies Expertise in Test planning Expertise in sub-system level DV Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations Preferred resources with valid regional work permit

Desired Profile : Bachelor's / Master's degree in engineering from EEE / E&C Expertise in managing and leading technical teams across different continents Expertise in leading business strategy in the VLSI / Semiconductor Services / foundry business industry Expertise in managing end to end projects including tape outs Must be willing to travel at short notice, relocate as per business needs Must be willing to work onsite (customer premises) as per business needs Expertise in working on any of the following technologies is mandatory : ANALOG MIXED SIGNAL LAYOUT - finfet / high speed / planar technology nodes ANALOG DESIGN - data converter / power management / pll ANALOG VERIFICATION ASIC PHYSICAL DESIGN ASIC RTL DESIGN DFT DESIGN - jtag / mbist / lbist / scan DIGITAL VERIFICATION - OVM / UVM / VMM EDA CAD FLOW - tcl / primetime / design compiler Job Specs : Responsible for meeting delivery, revenue, operational, customer satisfaction targets and team management Hire and manage high caliber technical teams across GCC, ODC and onsite Develop, Drive high quality business / technology strategy and oversee the translation of this strategy into tactical action Uphold the organization's culture and long term missions Liaise and negotiate with various partners around the world to bring in new partnership. Synergize all company's resources and talents for the growth of company's business Oversee all sectors and fields of the business to ensure the company's competitiveness Provide leadership, direction, major decision making and resolution support to operations, projects and staff. Build strategic business partnerships and execute these opportunities through collaboration with external partners Location - Bengaluru,Bhubaneswar,Kolkata,Kochi,Mysuru

Overview Lead Verification engineer Responsibilities As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Requirements Bachelors/ Masters degree or higher in EEE/ECE 7+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platforms: UVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with ARM/RISCV Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skills

ASIC Design Verification Engineer - ( SystemVerilog, UVM test bench, C/C++ , Perl/Python scripting, (VCS, DVE, Verdi), TCL/Shell scripting) | 10+ years Meet the Team Join our dynamic front-end design team at Cisco Silicon One, where innovation meets innovative technology! As part of the heart of silicon development at Cisco, you'll engage in every facet of chip design, from architecture to validation, using the latest silicon technologies to create groundbreaking devices. Cisco Silicon One is the only unified silicon architecture that empowers customers to deploy top-tier silicon across diverse applications, from top-of-rack switches to expansive data centres. Be a part of shaping Cisco's progressive solutions by designing and testing advanced ASICs that integrate networking, compute, and storage into a single system. With tightly integrated hardware and software solutions, you'll gain exposure to all aspects of our systems, using the latest technology. We're seeking a dedicated ASIC engineer with a proven track record in high-performance products, ready to make a significant impact in the industry. Join us and push the boundaries of what's possible! Your Impact Develop test plans, cover points, and qualification tests Perform end-to-end verification of design blocks and top-level Build and maintain block, cluster, and top-level DV environment infrastructure Construct testbenches components like scoreboard, agents, sequencers, and monitors Write tests, debug regressions, and drive to module verification closure Collaborate with designers and verification engineers for cross-block verification Upgrade configuration/reset sequences (APIs) Develop environment and tests for emulation Ensure complete verification coverage through code, functional coverage, and gate level simulations Support post-silicon bring-up and optimize integration and performance Minimum Qualifications Bachelors Degree in EE, CE, or other related fields with 6+ years or Masters Degree with 4+ years of ASIC design or verification experience Experience in developing verification environment for complex blocks from design specifications document Proficient in verifying complex blocks and/or clusters for ASIC using UVM/System Verilog. Scripting experience with Perl, Python, TCL, shell scripts. Preferred Qualifications Experience in Data center/ Hyper scaler /AI Networking technologies Proven experience meeting and delivering project milestones and deadlines. Ability to communicate technical concepts to audiences spanning executives to junior engineers to customers. Demonstrated ability in troubleshooting and debugging. Experience with Emulation and Formal Verification tools is a plus.

We are seeking a skilled Validation Engineer to join our team, focusing on ASIC/SoC product validation with strong background in hardware validation, functional testing, and software development.

Responsibilities Understand the standards/specifications Architecture development and documenting implementation level details Hands on work for every aspect of verification cycle Responsible for the compliance with the latest Methodologies. Developing Verification IPs Define Functional Coverage matrix and Comprehensive Test plan Regression management and functional coverage closure DUT integration and verification for IP delivery sign-off Leading small team Person Specification Required Skills Hands-on experience of complete verification cycle with strong verification concepts Strong knowledge of Verilog, SystemVerilog and UVM Experience in UVM based Verification IP development Experience in AMBA AXI/AHB/APB System buses Hands on work experience on any of PCIe/Eth/USB/DDR etc. Hands on experience with System Verilog Assertions Scripting for automation, release process, simulations, regressions Good command over written and oral communication Desirable Skills Lead the Verification IP development with 2 or more junior engineers Exposure to full verification cycle Desired Skills and Experience DV Engineer, Design Verification, Verification Engineer

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: Semiconductor Integration . Experience: 3-5 Years . >

Role & responsibilities Job Summary: We are seeking a highly skilled ASIC Design Verification Engineer with extensive experience in various verification methodologies. The ideal candidate will have a deep understanding of functional, formal, CPU, and GLS verification. The role requires expertise in SoC and IP level verification, particularly with high-speed protocols. This position demands a thorough knowledge of verification techniques, tools, and processes to ensure the highest quality in our ASIC designs. Key Responsibilities: - Develop and execute comprehensive verification plans for ASIC designs. - Utilize various verification methodologies, including functional, formal, CPU, and GLS verification. - Conduct SoC level verification, ensuring integration and functionality of multiple IPs. - Implement IP verification strategies for high-speed protocols such as PCIe, USB, Ethernet, DDR, MIPI, and others. - Collaborate with design and architecture teams to understand design specifications and requirements. - Create, maintain, and enhance testbenches and simulation environments. - Perform coverage analysis and closure to ensure all scenarios are tested. - Debug and resolve complex design and verification issues. - Document and present verification results to cross-functional teams. - Mentor junior engineers and contribute to the continuous improvement of verification processes. --- Required Skills and Qualifications: - **Experience:** 5+ to 20+ years in ASIC design verification. - **Education:** Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. - **Languages and Methodologies:** - Proficient in SystemVerilog, UVM (Universal Verification Methodology), C/C++. - Strong understanding of OO (Object-Oriented) concepts. - Experience in writing assumptions, sequences, virtual sequences, tests, and coverage closures. - Knowledge of UVM factory and configurations, UVM callbacks. - **Tools:** - Simulation tools: VCS, ModelSim, Questa, etc. - Formal verification tools: JasperGold, VC Formal, etc. - GLS tools: Synopsys, Cadence, or Mentor tools. - Debug tools: Verdi, DVE, SimVision, etc. - Coverage tools: Specman, Coverage Analyzer, etc. - **Protocols:** - High-speed protocols: PCIe, USB, Ethernet, DDR, MIPI, SATA, SerDes, etc. - SoC level protocols: AMBA (AXI, AHB, APB), ARM CoreSight, etc. - **Techniques:** - Assertion-based verification. - Random and directed test methodologies. - Power-aware verification. - Performance and throughput analysis. - Emulation and prototyping. --- SoC Level Verification: - **Responsibilities:** - Verify the integration of various IP blocks within the SoC. - Ensure proper functionality and communication between different IPs. - Utilize techniques such as simulation, emulation, and formal methods. - Perform power and performance analysis. - Validate system-level features and use cases. - **Required Knowledge:** - Advanced knowledge of SoC architectures. - Experience with ARM cores and subsystems. - Familiarity with interconnects and communication protocols. --- Subsystem Level Verification: - **Responsibilities:** - Verify individual subsystems such as memory controllers, interconnects, and peripheral interfaces. - Ensure subsystem integration within the larger SoC context. - Develop and execute detailed verification plans specific to each subsystem. - **Required Knowledge:** - Deep understanding of subsystem-level protocols and interfaces. - Experience with verification of memory interfaces (DDR, LPDDR), high-speed interfaces (PCIe, Ethernet), and peripheral interfaces (I2C, SPI, UART). --- Soft Skills: - Strong analytical and problem-solving skills. - Excellent communication and collaboration abilities. - Ability to work independently and as part of a team. - Leadership skills for mentoring junior engineers. Preferred Qualifications: - Prior experience in leading verification projects. - Contributions to industry standards or verification methodologies. - Publications or patents in the field of ASIC verification.

Enphase Energy is a global energy technology company and a leading provider of solar, battery, and electric vehicle charging products. Since its establishment in 2006, Enphase has been at the forefront of innovation in solar power, enhancing its safety, reliability, and scalability. With the Enphase Energy System, individuals can generate, utilize, store, and even sell their own power. The company has a remarkable global presence, having shipped over 80 million products to 160 countries. In this role at Enphase, you will be part of a dynamic team focused on designing and developing next-generation energy technologies to contribute towards a sustainable future. The position requires your presence onsite for 3 days a week initially, with a plan to transition back to a full 5-day in-office schedule gradually. As an experienced SoC Verification engineer, you will join the Enphase team in Bangalore, India, contributing to the development of the next generation Control ASIC in 22nm technology. This ASIC incorporates the ARM CM4 core, necessitating expertise in this core. The SOC integrates safety and security features, demanding a comprehensive understanding of these SoC challenges. The Control ASIC includes various components such as the CPU, Analog Front End (AFE), Power Line Communications Modem (PLC), proprietary Power Production control block, and other peripherals. Reporting to the Senior Director of ASIC Engineering in Bangalore, you will collaborate with internal/contract verification resources, IP designers, and Full Chip RTL engineers to verify the new SOC design. Your responsibilities will involve defining the verification methodology and verifying the RTL developed by Enphase engineers and 3rd party IP. The ideal candidate for this role possesses: - Deep understanding and experience in SoC architecture and verification - Specific experience in verifying the ARM CM4 and associated IP like AHB, AXI, RAM and ROM controllers, and DMA controllers - Hands-on experience with RISC-V verification (preferred) - Proficiency in UVM using SystemVerilog, Coverage driven verification methods, and formal verification methods for IP/SoC functional verification - Knowledge of RTL verification methods, Gate-level verifications, and mixed-signal methodologies - Experience in bringing complex SOCs into production To be considered for this position, you should have a proven track record with at least 15+ years of experience in the field. Join Enphase Energy in shaping the future of energy technology and playing a significant role in building a sustainable future.,

Job Details Job Description: Come join Intel&aposs Design Development Group organization as an SOC Verification engineering focused on Design for Debug (DFD). As a member of the product team, you will work firsthand with multi-function teams/sites, implementing and validating state-of-the-art debug solutions appropriate for new and existing technology in the product. In this role you will be working as part of a pre-silicon validation team for future Intel SoCs or IPs, focusing on debug validation. You will be working with pre-silicon and post -silicon validation teams to improve debug features and tools suites. You will also work closely with post-silicon validation SW teams on debug tool validation and silicon enabling. You will be pioneering new debug tools and flows, reviewing and publishing architectural specs and supporting next-generation silicon enabling on system platforms. Your Responsibilities Will Include But Not Be Limited To Verification of Design for Debug features (e.g. low and high-bandwidth signal tracing and event triggering) using simulation, emulation, and/or FPGA. Creating test plans and tests for validating portions of a complex microarchitecture using written specs, RTL code and other tests as a guide. Learning Power Management, Memory and debug architecture and microarchitecture by debugging failures to the root cause. Developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design. Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models. Developing debugging tools and software. Qualifications Minimum Qualifications: Candidate must have either a BE /ME / MTech or MS in Electronics, VLSI, Microelectronics, Computer Science or Electrical Engineering with 4-10 Years of experience. Extensive Pre-silicon Track record of driving debug tools enabling and validation, improvements and getting them adopted by others. Proven record of working across verification teams to solve problems. Expert of HW and SW Interaction and debug to root cause. Experience working across verification, architecture, SW, and design teams to resolve debug issues. Minimum 4 years of experience with writing verification plans and testcases to implement those validation plans. Minimum 4years of SOC Verification or Functional verification. Minimum 2yrs experience with Programming languages/Scripting: C, Perl, Python, Verilog and UNIX or Linux. Minimum 2yrs experience with SOC Architecture. Must have 4yrs+ experience with SOC Verification or Functional Verification. Must have 4yrs+ experience with validation or testing experience, especially in a silicon design team. Preferred Qualifications Good to have 2yrs+ experience with industry standards such as JTAG, Tessent and Debug architecture. Good to have working experience on assertions, coverage and Formal verification Job Type Experienced Hire Shift Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel&aposs PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people&aposs potential - allowing each person use our products to focus, create and connect in ways that matter most to them. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. Show more Show less

Job Title: Lead Design Verification Engineer Location: m Bangalore Job Type: Full-time Experience Level: 7+ years Department: Hardware Engineering / VLSI Design Job Summary: We are seeking a highly experienced Lead Design Verification Engineer to lead verification efforts for complex digital designs. The ideal candidate will drive testbench architecture, verification planning, and execution for ASIC/SoC or FPGA-based designs, ensuring first-time-right silicon or system functionality. You will work closely with RTL design, DV, and system engineering teams to deliver high-quality products. Key Responsibilities: Lead and drive the verification strategy, planning, and execution for IP, subsystem, or full-chip level. Define and implement constrained-random, directed, and coverage-driven verification methodologies (UVM/SystemVerilog preferred). Develop and maintain scalable and reusable testbench components. Mentor and guide junior verification engineers in testbench architecture, debugging, and coverage closure. Collaborate with RTL designers, architects, and firmware/software teams to understand design intent and develop test plans. Own and track functional coverage metrics and ensure 100% coverage goals are met. Drive regular reviews of verification status, risks, and issues with stakeholders. Support post-silicon validation teams with test vectors, debugging, and failure analysis. Required Qualifications: Bachelors or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 7+ years of industry experience in digital design verification. Strong expertise in SystemVerilog, UVM, and advanced verification methodologies. Experience in testbench architecture, test planning, and constrained-random stimulus generation. Solid understanding of digital design concepts, SoC/ASIC design flows, and bus protocols (e.g., AXI, AHB, PCIe, etc.). Hands-on experience with simulation tools (VCS, Questa, etc.) and coverage analysis tools. Excellent debugging and problem-solving skills using waveform viewers and assertion-based techniques. Familiarity with scripting languages such as Python, Perl, or TCL for automation. Strong communication and leadership skills with experience leading small to mid-sized teams. Preferred Qualifications: Experience in formal verification techniques. Experience with emulation, FPGA prototyping, or post-silicon bring-up. Exposure to power-aware or low-power verification (UPF/CPF). Knowledge of hardware security, safety, or compliance standards (ISO 26262, DO-254, etc.) is a plus. Familiarity with CI/CD flows and version control (Git, Jenkins, etc.). Why Join Us: Work on cutting-edge technologies and next-generation chip designs. Opportunity to lead high-impact projects and influence verification strategy. Collaborative and innovative work environment. Competitive salary, benefits, and career growth opportunities.

Job Area :Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Job Function BDC SerDes Mixed-Signal design team is actively looking for experienced (8+ years) analog circuit designers to work on high speedSerDes PHYs . You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Experience in designing multiple analog building blocks - LDO,high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc. Analog and or Digital PLLs for frequency synthesis and/or SerDes applications Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers. PLL Loop Dynamics, Jitter sources and modeling (RJ & DJ) Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY. Skills & Experience For lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC & interaction with post silicon teams like HSIO, ATE, SVE, CE etc. Understanding of advance Finfet process effects on designs and layout is required. Experience in using SPICE simulators, adexl & virtuoso. Experience with post-Si bring-up and debug is must. Good understanding on peripheral PHYs (USBs, UFS, PCIe) protocols is added advantage. Master/Bachelor in Electronics Shell/Perl-python scripting to automate circuit design and verification work. Able to work with teams across the globeand possess good communication and presentationskills. Preferred Mixed signal designexperience Keywords Analog circuit Design, Rx, Tx, PLL, SerDes, PHY, Serializer, Deserializer, VCO, High-speed Trans receiver

Job Area :Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience inVerilog/System-Verilogis a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Experience creating padring and working with the chip level floorplan team is an added advantage. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Position Overview: This is for a Senior Systems Engineer position in the airplane network systems engineering organization in the Boeing Commercial Airplanes (BCA) BU. As a member of this team, you will be responsible for leading System design development of aircraft network systems and development assurance (ARP4754A) activities. Also, you will be responsible for systems architecture, system design, system level requirements development, verification, validation and support FAA certification documents. This position provides consultation and technical direction to design and management teams on near-term and longer-range projects related to system safety requirements and risk estimation and management, including applicable regulations and standards. This role will be based out of Bangalore, India . Position Responsibilities: Demonstrate expert airplane network systems domain knowledge (network architecture & design -onboard network system, aircraft interface device, file servers; cloud and edge networking; antenna; communication protocols; wireless networking; data security & identity; virtualization; cyber security; avionics gateways) Designing the building blocks for the avionics systems as per ARP4754 & ARP4761. Define & own system Architecture. propose architectural enhancements for optimal safety solution Derive System, Sub-System level requirements from aircraft level requirements, industry standards, concept operations and/or trade studies. Perform trade studies, and evaluate alternate systems designs to propose the most optimal solutions for future avionics systems. Coordinating and communicating regularly with experts in Boeing organizations around the world. Identify, analyze, review, and mitigate potential hazards and risks associated with system designs to achieve enterprise and customer safety objectives while ensuring that the systems remain operationally responsive and effective Develops the basis of certification in accordance with the commercial / foreign military airworthiness certification standards. Review and approve stage gate exits (SRR, PDR, CDR, MRR, TRR, CERT and QUAL) Leads the SRR PDR, CDR, MRR, TRR, Certification/Qualification reviews Checks for reuse and productivity improvement on overall architecture Perform systematic and comprehensive safety assessments on the system architecture, integrated design, Hardware/software, support equipment, and installation of the subsystems, and experiments to ensure that relevant safety requirements are met Partner with Technical Fellowship to author and maintain System Engineering Design Practices Ensure Safety Management System goals are well understood and deployed in day-to-day activities. Identify, communicate and mitigate the Risk, issues and Opportunities on a timely manner Coordinate and collaborate across stakeholders (engineering, EHS, technicians, quality, leadership, customers) to ensure safety is integral to all activities and operations Review engineering design specifications, test operations procedures, change proposals, deficiency reports, exceptions, and/or deviation/waiver requests for potential flight/ground test safety impacts Represent Systems Group in Industry Standard Committee and support teams to adopt the practices Participating in incident investigations and root cause/corrective action analyses as requested. Acts as a technical advisor across group and supports multiple programs as needed. Support preparation of presentations, analyses, and reports for government/customer, program design reviews, and test/mission readiness reviews. Basic Qualifications A Bachelors degree or higher is required as a BASIC QUALIFICATION Experience in design/development or in integrating multiple systems into aircraft platforms with special focus on safety requirements development and associated hazard analyses. Excellent people skills, very strong verbal and written communication skills. Having Hardware exposure from end-to-end lifecycle, integration experience is must. Experience with Aircraft systems integration activities. Ability to effectively collaborate with internal and external partners. Strong decision making and problem-solving skills. Demonstrated ability to be proactive, self-motivated, flexible and creative. Typical Education & Experience: Engineering degree (Electronics & communication, Electronics & telecommunication / Electrical & electronics) and 16+ years related work experience, a masters degree and 15+ years related work experience or an equivalent combination of education and experience. Relocation: This position offers relocation within INDIA. Education Bachelor's Degree or Equivalent Required