Verification Engineer - Embedded System

In this role, you will be responsible for defining and implementing a power-aware verification strategy using UPF (IEEE 1801). Your key responsibilities will include: - Integrate power intent into simulation environments and verify power management features. - Develop and maintain power-aware test benches and testcases in System Verilog/UVM. - Run simulations, debug failures, and ensure design functionality across power states. - Collaborate with RTL designers and architects to ensure correct power domain partitioning and isolation. - Perform static checks for power intent correctness using tools such as Synopsys VC LP or Cadence Conformal Low Power. - Ensure compliance of low-power implementation with overall chip power and performance goals. You should have a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Additionally, you should have 5+ years of experience in ASIC/SoC verification with a focus on low-power design. Other qualifications include: - Solid understanding of UPF 2.0/2.1/3.0 and power-aware verification methodologies. - Experience with simulation tools (e.g., Synopsys VCS, Cadence Xcelium) and waveform debugging tools. - Proficiency in System Verilog, UVM, scripting (Python/Perl/TCL). - Good understanding of power management techniques like power gating, clock gating, multi-voltage domains. If you are looking to join a company that focuses on cutting-edge technologies and innovative solutions, this opportunity might be a great fit for you.,