4 Clock Gating Jobs

Sr. Engineer - ASIC Digital Design (Physical Implementation/Design/STA, 2+ years of exp) We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and experienced ASIC Digital Design Engineer passionate about working on the latest processes for STA and physical implementation flows on cutting-edge technology nodes. You thrive in dynamic environments and excel in collaborating with functional teams to optimize and develop IO validation vehicles, Mixed Signal IPs, 3DIO PHYs and UCIe-3D PHY. You have a strong focus on Timing Closure and are adept at defining signoff criteria. Your background includes extensive experience with ASIC design flow, hierarchical physical design strategies, and a deep understanding of sub-micron technology issues. You possess a strong knowledge of timing analysis, constraints management, and various verification strategies, including Primepower-based power analysis. Your scripting skills are excellent, and you are innovative, self-motivated, and able to work both independently and as part of a team. Your communication skills, both verbal and written, are outstanding, and you have a desire to understand RTL/Timing signoff criteria. What Youll Be Doing: Working on new processes for physical implementation flows and cutting-edge technology nodes. Collaborating with functional teams to optimize and develop Qualificaition vehicles and 3D PHYs. Defining signoff criteria with a strong focus on Timing Closure. Maturing the physical implementation guide used for customers and internal hardening teams. Participating in next-generation physical design methodology and flow development. Performing physical design implementation, including synthesis, floor planning, PG Grid design, PnR, CTS, STA, and power/signal integrity signoff. Evaluating PPA targets (Area/Speed/Power) and collaborating with the design team to improve design and constraints. The Impact You Will Have: Ensuring the optimization and successful implementation of cutting-edge technology nodes. Contributing to the development of high-performance silicon chips and software content. Enhancing the efficiency and performance of Synopsys IPs through rigorous timing closure and signoff criteria. Improving customer satisfaction by maturing physical implementation guides. Supporting the achievement of Synopsys' operational goals through innovative design solutions. What Youll Need: Extensive experience with ASIC design flow and hierarchical physical design strategies. Strong background in timing analysis, constraints management, and frontend synthesis. Experience with physical-aware synthesis, formality, and various verification strategies. Knowledge of Primepower-based power analysis and clock gating for power reduction. Fair knowledge of FC design planning methodologies, floor planning, and PG Grid creation using Synopsys Tools. Strong physical implementation flow debugging skills and scripting abilities. Who You Are: Innovative, self-motivated, and able to work independently or as a team player. Excellent verbal and written communication skills. Strong analytical and problem-solving abilities. Passionate about continuous learning and staying updated with the latest technological advancements in ASIC digital design. The Team Youll Be A Part Of: You will join a highly skilled and collaborative team focused on developing and optimizing physical design flows for cutting-edge technology nodes. The team is dedicated to innovation, continuous improvement, and delivering high-performance solutions that meet the evolving needs of our customers. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

As a candidate for this position, you should hold a Bachelor's degree in Electronics or Computer Engineering/Science, or possess equivalent practical experience. With a minimum of 8 years of experience in SoC power modeling and analysis, you should also have a solid understanding of SOC architecture and power techniques. A Master's degree or PhD in Electronics, Computer Engineering, or Computer Science would be considered a preferred qualification. Additionally, experience with ASIC design flows and knowledge of low power architecture and power optimization techniques such as multi Vth/power/voltage domain design, clock gating, power gating, and Dynamic Voltage Frequency Scaling would be advantageous. Join a diverse team that is dedicated to pushing boundaries and developing custom silicon solutions to power the future of Google's direct-to-consumer products. Your contribution to the innovation behind products loved by millions worldwide will be crucial. Your expertise will play a significant role in shaping the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. At Google, our mission is to organize the world's information and make it universally accessible and useful. The Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. Through research, design, and development of new technologies and hardware, we aim to enhance user interaction with computing, making it faster, seamless, and more powerful. The Devices & Services team is dedicated to improving people's lives through technology by exploring new ways to capture and sense the world, advancing form factors, and enhancing interaction methods. Your responsibilities in this role will include defining power requirements for an SoC to optimize Power-Performance-Area (PPA) under current and thermal constraints. You will define power KPIs and SoC/IP-level power goals, guide architecture, design, implementation, and software to achieve power goals, and track power throughout the design cycle. Additionally, you will propose and drive power optimizations throughout the design process, perform algorithm development, modeling, and analysis of various power approaches, and lead power-performance trade-off analysis for engineering reviews and product roadmap decisions.,

We are seeking a skilled and detail-oriented Engineer specializing in Synthesis, Physical Synthesis, and pre-layout Static Timing Analysis (STA). The ideal candidate will have strong expertise in various aspects of digital design implementation, including UPF generation, synthesis optimizations, and constraint development. This role is crucial for ensuring the functional correctness, performance, and power efficiency of our semiconductor designs. Key Responsibilities: Perform Synthesis, Physical Synthesis, and pre-layout Static Timing Analysis (STA) for complex digital designs. Responsible for UPF (Unified Power Format) generation from scratch to define power intent for low-power designs. Execute synthesis of RTL code into gate-level netlists. Implement Multi-Vt (Multi-Threshold Voltage) optimizations to achieve power and performance targets. Implement and optimize Clock Gating techniques for power reduction. Perform Datapath Synthesis to ensure efficient data flow implementation. Conduct Scan Insertion for Design For Testability (DFT). Ensure designs are Multi-supply/Switching aware for robust power management. Implement and verify DVFS (Dynamic Voltage and Frequency Scaling) techniques. Perform Retiming to optimize critical paths for timing closure. Undertake Constraint Development , ensuring accurate and comprehensive timing constraints. Possess IP constraint knowledge on interfaces like DDR3/4, Multiprotocol SerDes, ARM core and Subsystem, USB3.0 , which is a significant plus. Required Skills and Qualifications: Strong expertise in digital design Synthesis and Physical Synthesis . Proficient in pre-layout Static Timing Analysis (STA) . Experience with UPF generation . Knowledge of Multi-Vt optimizations, Clock Gating, Datapath Synthesis, Scan Insertion, Multi-supply/Switching awareness, DVFS, and Retiming . Strong skills in Constraint Development . Familiarity with IP constraints on DDR3/4, Multiprotocol SerDes, ARM core and Subsystem, USB3.0 is highly desirable.

Qualcomm India Private Limited is looking for a passionate STA and Synthesis Engineer to join their Engineering Group in Chennai. As an integral part of the cross-functional engineering teams, you will be engaged in all phases of design and development cycles, specifically focusing on Synthesis, Static Timing Analysis, and LEC of SoC/Cores. Your responsibilities will include full chip and block level timing closure, IO budgeting for blocks, logical equivalence checks between RTL to Netlist and Netlist to Netlist, as well as implementing low-power techniques such as clock gating, power gating, and MV designs. Additionally, you will be involved in ECO timing flow and should be proficient in scripting languages like TCL and Perl. The ideal candidate should possess a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 2+ years of experience in Hardware Engineering. Alternatively, a Master's degree with 1+ year of relevant experience or a PhD in the aforementioned fields is also acceptable. Applicants with 1-5 years of experience are encouraged to apply. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact Qualcomm at disability-accommodations@qualcomm.com or refer to their toll-free number for assistance. Qualcomm also emphasizes the importance of compliance with company policies and procedures, including security measures for protecting confidential information. Staffing and Recruiting Agencies are advised that Qualcomm's Careers Site is exclusively for individuals seeking job opportunities directly with Qualcomm. Agency submissions will be considered unsolicited, and Qualcomm does not accept unsolicited resumes or applications from agencies. For further details about this role, please reach out to Qualcomm Careers.,