BoltChip builds Global Capability Centres (GCCS) for semiconductor IC Design and AI innovation companies in ASIA Role : Senior Layout Engineer – TSMC 12nm and Below Location: Gujarat Experience: 5+ years Industry: Semiconductor Design About the Role: We are seeking an experienced Senior Layout Engineer to join our semiconductor design team. This role is ideal for professionals with a solid background in deep sub-micron technologies and hands-on experience in analog layout, particularly with TSMC 12nm and below process nodes. Key Responsibilities: Execute full custom layout for analog and mixed-signal blocks including IO (TX and RX), PLLs , and other analog circuits. Ensure high-quality layout design aligned with DRC, LVS, and EMIR compliance using industry-standard tools. Collaborate closely with circuit design teams and physical verification engineers to resolve layout issues. Participate in design reviews and contribute to layout planning and optimization. Maintain quality and performance standards in high-speed, low-power layout design. Required Qualifications: 5+ years of experience in custom analog/mixed-signal layout. Proven hands-on experience on TSMC 12nm or smaller technology nodes. Direct experience for at least 1–2 years in layout of IO blocks (TX/RX) , PLLs , and various analog IP blocks . Proficient with tools like Virtuoso, Calibre, and Assura. Strong understanding of parasitic extraction, signal integrity, and layout best practices. Ability to work independently and in collaboration with cross-functional teams. Preferred Qualifications: Experience with lower nodes such as 7nm or 5nm is a plus. Exposure to ESD, latch-up protection, and high-speed signaling considerations. Why Join Us? Be part of a fast-growing semiconductor design group working on cutting-edge technology. You’ll collaborate with some of the sharpest minds in the industry and help shape the future of SoC innovation. Show more Show less