BoltChip builds Global Capability Centres (GCCS) for semiconductor IC Design and AI innovation companies in ASIA Role : Senior Layout Engineer – TSMC 12nm and Below Location: Gujarat Experience: 5+ years Industry: Semiconductor Design About the Role: We are seeking an experienced Senior Layout Engineer to join our semiconductor design team. This role is ideal for professionals with a solid background in deep sub-micron technologies and hands-on experience in analog layout, particularly with TSMC 12nm and below process nodes. Key Responsibilities: Execute full custom layout for analog and mixed-signal blocks including IO (TX and RX), PLLs , and other analog circuits. Ensure high-quality layout design aligned with DRC, LVS, and EMIR compliance using industry-standard tools. Collaborate closely with circuit design teams and physical verification engineers to resolve layout issues. Participate in design reviews and contribute to layout planning and optimization. Maintain quality and performance standards in high-speed, low-power layout design. Required Qualifications: 5+ years of experience in custom analog/mixed-signal layout. Proven hands-on experience on TSMC 12nm or smaller technology nodes. Direct experience for at least 1–2 years in layout of IO blocks (TX/RX) , PLLs , and various analog IP blocks . Proficient with tools like Virtuoso, Calibre, and Assura. Strong understanding of parasitic extraction, signal integrity, and layout best practices. Ability to work independently and in collaboration with cross-functional teams. Preferred Qualifications: Experience with lower nodes such as 7nm or 5nm is a plus. Exposure to ESD, latch-up protection, and high-speed signaling considerations. Why Join Us? Be part of a fast-growing semiconductor design group working on cutting-edge technology. You’ll collaborate with some of the sharpest minds in the industry and help shape the future of SoC innovation. Show more Show less
As an ASIC Design Engineer specializing in UPF and Low Power Design, you will be responsible for owning and driving RTL design for complex digital blocks with multiple power domains. Your role will involve defining, implementing, and validating power intent using UPF 2.0/3.0 for ASIC and SoC designs. Collaboration with verification and physical design teams will be crucial to ensure correct propagation and verification of power intent across the flow. You will work closely with architecture teams to define low power design strategies including power gating, clock gating, and multi-voltage domains. Additionally, analyzing and debugging power-related issues during RTL and gate-level simulations will be part of your responsibilities. It is essential to develop and maintain design documentation such as micro-architecture specs and power intent specifications. Supporting integration and implementation teams in handling low power design constraints and challenges will also be a key aspect of your role. To be successful in this position, you should hold a Bachelors or Masters degree in Electronics/Electrical Engineering or a related discipline. With a minimum of 7 years of ASIC front-end design experience, including at least 3 years focused on low power/UPF design, you should be proficient in RTL coding using Verilog/SystemVerilog with strong design fundamentals. A deep understanding of low power architecture techniques like power gating, retention, isolation, and voltage scaling is required. Hands-on experience with UPF-based flows and power-aware tools from Synopsys, Cadence, or Mentor is essential. Experience in running LINT, CDC, and synthesis with power intent, along with excellent debugging and problem-solving skills, are also necessary. Preferred skills include exposure to DFT constraints and the impact of power intent on scan/ATPG, familiarity with scripting languages like Python/Perl/TCL for automation, and experience in collaborating across global design and verification teams. A working knowledge of timing closure, clock domain crossing (CDC), and logic equivalence checks (LEC) would be beneficial in this role. Joining BOLTCHIP will offer you the opportunity to be part of a cutting-edge semiconductor design team focused on innovation and quality. You will collaborate with top-tier professionals in the low-power design domain and benefit from competitive compensation and opportunities for growth. If you meet the requirements and are excited about this opportunity, please apply by sending your resume to jasmine.h@boltchip.com.,
Boltchip is a Singapore based Transformation Consulting company setting up Global Capability centres for global clients in ASIA. We are on the lookout for a team of Senior Design Verification engineers for our client in India. Location – India (Bangalore & Ahmedabad ( Onsite only )) Qualification (s) – BE/ BTech/ MTech/MS/ PhD Domain - Electronics, Electrical, Computer Engineering or Computer Science Engineering Experience – 7+ years We are looking for a highly skilled and experienced Design Verification Engineer to join our team. This role is ideal for someone who brings deep technical expertise in verification along with a strong grasp of industry protocols and low-power design techniques. You'll work on advanced IP and SoC subsystems involving both RISC-V and ARM-based architecture, and collaborate closely with our architecture, design, and validation teams. What You'll Do: Own and drive the full verification cycle for IP blocks and subsystems Create detailed verification plans, identify test items, and track coverage Build UVM-based test benches from scratch, including drivers, monitors, and scoreboards Perform low power verification using both UPF and Native Low Power (NLP) methods Develop and run UVM-based test environments for Ethernet and other protocol interfaces Integrate and work with third-party Verification IPs (VIPs) Write and debug assertions and functional coverage models Collaborate with design and architecture teams to close verification cycles efficiently Support silicon bring-up and post-silicon debug when required Mentor junior team members on verification techniques and best practices Key Skills We Are Looking For: UPF / Low Power Verification (UVM expert) Strong understanding of low-power concepts in ASIC design (UPF/NLP) from a verification perspective UVM with Ethernet protocol expertise NLP Testbench Verification with Native Low Power (UVM expert) Strong command over System Verilog , Verilog , and UVM methodology Solid understanding of ASIC design flows and power-aware design concepts Experience with protocols like PCIe, AXI, CHI, Ethernet, USB, NVMe, DDR, and CXL Good working knowledge of System Verilog Assertions (SVA) and formal verification techniques Hands-on experience with scripting ( Python, Perl, Shell, TCL ) Comfortable working in Linux development environments Excellent debugging, problem-solving, and analytical thinking Strong communication and collaboration skills Qualifications: Bachelor’s degree in Electrical Engineering, Electronics and Communications Engineering, Computer Engineering, Computer Science, or related fields Fluent in both written and spoken English Excellent collaborative skills Highly motivated and self-driven individual Strong coding and object-oriented programming skills Excellent debugging, problem solving, and analytical skills Knowledgeable in digital design Minimum 7 years of industry experience in Design Verification roles. A track record of successfully verifying complex IP blocks or subsystems from spec to silicon.
Boltchip is a Talent Transformation company based in Singapore. One of our global client is building their Design teams in India. We are building their entire capability for ASIA. Role : Senior Design Engineer Location : Ahmedabad Qualification (s) – BE / BTech / MTech / MS / PhD Domain - Electronics, Electrical, Computer Engineering or Computer Science Engineering Experience – 7+ years We are looking for a highly skilled and experienced Design Verification Engineer to join our team. This role is ideal for someone who brings deep technical expertise in verification along with a strong grasp of industry protocols and low-power design techniques. You'll work on advanced IP and SoC subsystems involving both RISC-V and ARM-based architecture, and collaborate closely with our architecture, design, and validation teams. What You'll Do: · Own and drive the full verification cycle for IP blocks and subsystems · Create detailed verification plans, identify test items, and track coverage · Build UVM-based test benches from scratch, including drivers, monitors, and scoreboards · Perform low power verification using both UPF and Native Low Power (NLP) methods · Develop and run UVM-based test environments for Ethernet and other protocol interfaces · Integrate and work with third-party Verification IPs (VIPs) · Write and debug assertions and functional coverage models · Collaborate with design and architecture teams to close verification cycles efficiently · Support silicon bring-up and post-silicon debug when required · Mentor junior team members on verification techniques and best practices Key Skills We Are Looking For: · UPF / Low Power Verification (UVM expert) · Strong understanding of low-power concepts in ASIC design (UPF/NLP) from a verification perspective · UVM with Ethernet protocol expertise · NLP Test bench Verification with Native Low Power (UVM expert) · Strong command over System Verilog , Verilog , and UVM methodology · Solid understanding of ASIC design flows and power-aware design concepts · Experience with protocols like PCIe, AXI, CHI, Ethernet, USB, NVMe, DDR, and CXL · Good working knowledge of System Verilog Assertions (SVA) and formal verification techniques · Hands-on experience with scripting ( Python, Perl, Shell, TCL ) · Comfortable working in Linux development environments · Excellent debugging, problem-solving, and analytical thinking · Strong communication and collaboration skills Qualifications: · Bachelor’s degree in Electrical Engineering, Electronics and Communications Engineering, Computer Engineering, Computer Science, or related fields · Fluent in both written and spoken English · Excellent collaborative skills · Highly motivated and self-driven individual · Strong coding and object-oriented programming skills · Excellent debugging, problem solving, and analytical skills · Knowledgeable in digital design · Minimum 7 years of industry experience in Design Verification roles. · A track record of successfully verifying complex IP blocks or subsystems from spec to silicon. Please forward your resume to jasmine.h@boltchip.com
Boltchip is a Consulting firm based in Singapore building Innovation Capability Centers (ICCS) for global clients. One of our US clients is building their products on NOC and having IPS in front end design is expanding their team in Bhubaneshwar and Bangalore India. Position: Verification Engineer Experience: 4–6 years Location: Bangalore / Bhubaneswar Qualification: B.Tech / M.Tech in Electronics or related field About the Role We are seeking skilled Verification Engineers with strong experience in SoC design verification. The candidates should have expertise in verifying complex SoC-level designs, with exposure to industry-standard protocols and verification methodologies(UVM). He/She will be part of a dynamic team working on state-of-the-art SoC projects, contributing to verification planning, test bench development, execution, and closure. Key Responsibilities Develop, implement, and maintain verification environments using SystemVerilog and UVM. Perform test planning, test case development, debugging, and functional coverage closure. Verify SoC-level integration of IPs and subsystems. Work closely with design, architecture, and validation teams to ensure first-pass silicon success. Drive verification strategies, regression automation, and debug complex failures. Required Skills & Experience 4–7 years of experience in ASIC/SoC functional verification. Strong hands-on expertise with SystemVerilog and UVM methodology. Solid experience in SoC verification including bus/protocol-level testing. Good understanding and working knowledge of standard protocols such as: AMBA (AXI/AHB/APB) UART, SPI, I2C/I3C MIPI, and other SoC-relevant protocols Experience in developing and debugging complex test benches. Familiarity with coverage-driven verification and constrained-random testing. Proficiency with simulation, waveform debug, and regression tools. Strong problem-solving, analytical, and communication skills. Preferred Skills (Good to Have) Exposure to low-power verification (UPF). Experience with gate-level simulations and formal verification. Knowledge of scripting (Perl/Python/Shell) for automation. Experience with verification of subsystems such as USB subsystem, UCIe, PCIe/CXL subsystem, memory controllers, interconnects, or peripheral IPs.
Boltchip is a Consulting company in Singapore building Innovation Capability centers (ICCs) for global semiconductor companies in ASIA. We are building Analog team for one of product-based company that provides silicon, software, and solutions for connected devices, with a focus on wireless technology for the Internet of Things (IoT). Position: Analog Architect Location: Hyderabad, India Employment Type: Full-Time Role Overview: We are seeking an experienced Analog Architect to lead the design and architecture of advanced analog and mixed-signal circuits. You will collaborate closely with system and digital teams to deliver high-performance, low-power solutions across semiconductor products. Responsibilities: Lead architecture and design of analog/mixed-signal blocks (ADCs, DACs, PLLs, LDOs, power management). Translate system requirements into robust analog design specifications. Mentor and guide analog engineers, ensuring best practices and quality. Drive innovation and optimization for performance, power, and area. Qualifications: Bachelor’s or Master’s in Electrical/Electronics Engineering. 10+ years in analog/mixed-signal design, with leadership experience. Hands-on experience with Cadence, Virtuoso, or similar tools. Proven track record of successful IC design and tape-outs. Why Join: Be part of a cutting-edge semiconductor team shaping next-generation analog and mixed-signal solutions in a collaborative and high-impact environment.
Boltchip is a Consulting company based in Singapore and building Innovation Capability Centers for semiconductor engineering clients in ASIA. For one of US MNC clients, we are building their Analog and Mixed signal team. We are seeking experienced RF and Analog/Mixed-Signal (AMS) Design Engineers to contribute to the design and development of high-performance ICs. The ideal candidates will bring strong technical expertise in Analog/RF design, IP development, and cross-node porting, supporting collaborative projects with global semiconductor partners. Key Responsibilities Lead and execute Analog/RF IP design from specification through verification and validation. Support IP porting across process nodes. Collaborate with digital, layout, and verification teams to ensure seamless integration. Perform circuit simulations, design reviews, and performance optimizations. Work closely with foundry partners and customers for tape-out readiness and characterization. Contribute to capability building within BOLTCHIP's Innovation Capability Centers (ICCs). Required Skills & Experience Bachelor's/Master's in Electrical/Electronics Engineering or related field. 510 years of experience in Analog/RF IC design or AMS IP development. Expertise in one or more of: RF blocks (LNAs, Mixers, PAs, VCOs, PLLs) AMS circuits (ADCs, DACs, amplifiers, bandgaps, regulators) Experience with EDA tools (Cadence Virtuoso, Spectre, ADS, etc.). Understanding of process technology variations and design migration. Strong analytical, problem-solving, and documentation skills. Only shortlisted resumes would be intimated. www.boltchip.com
Boltchip is a Singapore based Consulting company focussing on building Innovation Capability centres for Semiconductor clients in ASIA. Role : RF Analog IC Design Lead. Location : Hyderabad, Telangana, India. Experience : 7 - 10 years Key Responsibilities Lead end-to-end design of RF/Analog circuits including LNAs, mixers, PLLs, VCOs, power amplifiers, and data converters. Define design architecture, specifications, and verification methodologies. Collaborate closely with digital, layout, and system teams to ensure optimal performance and manufacturability. Mentor and guide junior design engineers in best practices for RF and analog design. Participate in silicon validation, characterization, and yield optimization. Interface with customers and cross-functional teams to ensure technical excellence and timely delivery. Qualifications Master’s or PhD in Electrical/Electronic Engineering or related field. 7-10 years of experience in RF/Analog IC design, preferably in CMOS or BiCMOS technologies. Proven track record of leading design projects from concept to silicon validation. Strong understanding of circuit simulation tools (Spectre, ADS, Cadence Virtuoso) and RF measurement techniques. Excellent analytical, problem-solving, and communication skills. Preferred Experience Exposure to wireless communication standards (Wi-Fi, Bluetooth, 5G, etc.). Experience with mixed-signal integration and system-level co-design.
Boltchip is a Singapore based Consulting company focussing on building Innovation Capability centres for Semiconductor clients in ASIA. Role : RF Analog IC Design Lead. Location : Hyderabad, Telangana, India. Experience : 7 - 10 years Key Responsibilities Lead end-to-end design of RF/Analog circuits including LNAs, mixers, PLLs, VCOs, power amplifiers, and data converters. Define design architecture, specifications, and verification methodologies. Collaborate closely with digital, layout, and system teams to ensure optimal performance and manufacturability. Mentor and guide junior design engineers in best practices for RF and analog design. Participate in silicon validation, characterization, and yield optimization. Interface with customers and cross-functional teams to ensure technical excellence and timely delivery. Qualifications Master's or PhD in Electrical/Electronic Engineering or related field. 7-10 years of experience in RF/Analog IC design, preferably in CMOS or BiCMOS technologies. Proven track record of leading design projects from concept to silicon validation. Strong understanding of circuit simulation tools (Spectre, ADS, Cadence Virtuoso) and RF measurement techniques. Excellent analytical, problem-solving, and communication skills. Preferred Experience Exposure to wireless communication standards (Wi-Fi, Bluetooth, 5G, etc.). Experience with mixed-signal integration and system-level co-design.
As an RF IC Design Lead at Boltchip, a Singapore based Consulting company focusing on building Innovation Capability centres for Semiconductor clients in ASIA, your role will involve: - Leading end-to-end RF IC design circuits, which includes LNAs, mixers, PLLs, VCOs, power amplifiers, and data converters. - Defining RF IC design architecture, specifications, and verification methodologies. - Collaborating closely with digital, layout, and system teams to ensure optimal performance and manufacturability. - Mentoring and guiding junior design engineers in best practices for RF IC design. - Participating in silicon validation, characterization, and yield optimization. - Interfacing with customers and cross-functional teams to ensure technical excellence and timely delivery. Qualifications required for this role include: - Masters or PhD in Electrical/Electronic Engineering or related field. - 7-10 years of experience in RF IC design, preferably in CMOS or BiCMOS technologies. - Proven track record of leading design projects from concept to silicon validation. - Strong understanding of circuit simulation tools such as Spectre, ADS, Cadence Virtuoso, and RF measurement techniques. - Excellent analytical, problem-solving, and communication skills. Preferred experience for the role includes exposure to wireless communication standards (Wi-Fi, Bluetooth, 5G, etc.) and experience with mixed-signal integration and system-level co-design.,