BOLTCHIP

BoltChip builds Global Capability Centres (GCCS) for semiconductor IC Design and AI innovation companies in ASIA Role : Senior Layout Engineer – TSMC 12nm and Below Location: Gujarat Experience: 5+ years Industry: Semiconductor Design About the Role: We are seeking an experienced Senior Layout Engineer to join our semiconductor design team. This role is ideal for professionals with a solid background in deep sub-micron technologies and hands-on experience in analog layout, particularly with TSMC 12nm and below process nodes. Key Responsibilities: Execute full custom layout for analog and mixed-signal blocks including IO (TX and RX), PLLs , and other analog circuits. Ensure high-quality layout design aligned with DRC, LVS, and EMIR compliance using industry-standard tools. Collaborate closely with circuit design teams and physical verification engineers to resolve layout issues. Participate in design reviews and contribute to layout planning and optimization. Maintain quality and performance standards in high-speed, low-power layout design. Required Qualifications: 5+ years of experience in custom analog/mixed-signal layout. Proven hands-on experience on TSMC 12nm or smaller technology nodes. Direct experience for at least 1–2 years in layout of IO blocks (TX/RX) , PLLs , and various analog IP blocks . Proficient with tools like Virtuoso, Calibre, and Assura. Strong understanding of parasitic extraction, signal integrity, and layout best practices. Ability to work independently and in collaboration with cross-functional teams. Preferred Qualifications: Experience with lower nodes such as 7nm or 5nm is a plus. Exposure to ESD, latch-up protection, and high-speed signaling considerations. Why Join Us? Be part of a fast-growing semiconductor design group working on cutting-edge technology. You’ll collaborate with some of the sharpest minds in the industry and help shape the future of SoC innovation. Show more Show less

As an ASIC Design Engineer specializing in UPF and Low Power Design, you will be responsible for owning and driving RTL design for complex digital blocks with multiple power domains. Your role will involve defining, implementing, and validating power intent using UPF 2.0/3.0 for ASIC and SoC designs. Collaboration with verification and physical design teams will be crucial to ensure correct propagation and verification of power intent across the flow. You will work closely with architecture teams to define low power design strategies including power gating, clock gating, and multi-voltage domains. Additionally, analyzing and debugging power-related issues during RTL and gate-level simulations will be part of your responsibilities. It is essential to develop and maintain design documentation such as micro-architecture specs and power intent specifications. Supporting integration and implementation teams in handling low power design constraints and challenges will also be a key aspect of your role. To be successful in this position, you should hold a Bachelors or Masters degree in Electronics/Electrical Engineering or a related discipline. With a minimum of 7 years of ASIC front-end design experience, including at least 3 years focused on low power/UPF design, you should be proficient in RTL coding using Verilog/SystemVerilog with strong design fundamentals. A deep understanding of low power architecture techniques like power gating, retention, isolation, and voltage scaling is required. Hands-on experience with UPF-based flows and power-aware tools from Synopsys, Cadence, or Mentor is essential. Experience in running LINT, CDC, and synthesis with power intent, along with excellent debugging and problem-solving skills, are also necessary. Preferred skills include exposure to DFT constraints and the impact of power intent on scan/ATPG, familiarity with scripting languages like Python/Perl/TCL for automation, and experience in collaborating across global design and verification teams. A working knowledge of timing closure, clock domain crossing (CDC), and logic equivalence checks (LEC) would be beneficial in this role. Joining BOLTCHIP will offer you the opportunity to be part of a cutting-edge semiconductor design team focused on innovation and quality. You will collaborate with top-tier professionals in the low-power design domain and benefit from competitive compensation and opportunities for growth. If you meet the requirements and are excited about this opportunity, please apply by sending your resume to jasmine.h@boltchip.com.,

Boltchip is a Singapore based Transformation Consulting company setting up Global Capability centres for global clients in ASIA. We are on the lookout for a team of Senior Design Verification engineers for our client in India. Location – India (Bangalore & Ahmedabad ( Onsite only )) Qualification (s) – BE/ BTech/ MTech/MS/ PhD Domain - Electronics, Electrical, Computer Engineering or Computer Science Engineering Experience – 7+ years We are looking for a highly skilled and experienced Design Verification Engineer to join our team. This role is ideal for someone who brings deep technical expertise in verification along with a strong grasp of industry protocols and low-power design techniques. You'll work on advanced IP and SoC subsystems involving both RISC-V and ARM-based architecture, and collaborate closely with our architecture, design, and validation teams. What You'll Do: Own and drive the full verification cycle for IP blocks and subsystems Create detailed verification plans, identify test items, and track coverage Build UVM-based test benches from scratch, including drivers, monitors, and scoreboards Perform low power verification using both UPF and Native Low Power (NLP) methods Develop and run UVM-based test environments for Ethernet and other protocol interfaces Integrate and work with third-party Verification IPs (VIPs) Write and debug assertions and functional coverage models Collaborate with design and architecture teams to close verification cycles efficiently Support silicon bring-up and post-silicon debug when required Mentor junior team members on verification techniques and best practices Key Skills We Are Looking For: UPF / Low Power Verification (UVM expert) Strong understanding of low-power concepts in ASIC design (UPF/NLP) from a verification perspective UVM with Ethernet protocol expertise NLP Testbench Verification with Native Low Power (UVM expert) Strong command over System Verilog , Verilog , and UVM methodology Solid understanding of ASIC design flows and power-aware design concepts Experience with protocols like PCIe, AXI, CHI, Ethernet, USB, NVMe, DDR, and CXL Good working knowledge of System Verilog Assertions (SVA) and formal verification techniques Hands-on experience with scripting ( Python, Perl, Shell, TCL ) Comfortable working in Linux development environments Excellent debugging, problem-solving, and analytical thinking Strong communication and collaboration skills Qualifications: Bachelor’s degree in Electrical Engineering, Electronics and Communications Engineering, Computer Engineering, Computer Science, or related fields Fluent in both written and spoken English Excellent collaborative skills Highly motivated and self-driven individual Strong coding and object-oriented programming skills Excellent debugging, problem solving, and analytical skills Knowledgeable in digital design Minimum 7 years of industry experience in Design Verification roles. A track record of successfully verifying complex IP blocks or subsystems from spec to silicon.

Boltchip is a Talent Transformation company based in Singapore. One of our global client is building their Design teams in India. We are building their entire capability for ASIA. Role : Senior Design Engineer Location : Ahmedabad Qualification (s) – BE / BTech / MTech / MS / PhD Domain - Electronics, Electrical, Computer Engineering or Computer Science Engineering Experience – 7+ years We are looking for a highly skilled and experienced Design Verification Engineer to join our team. This role is ideal for someone who brings deep technical expertise in verification along with a strong grasp of industry protocols and low-power design techniques. You'll work on advanced IP and SoC subsystems involving both RISC-V and ARM-based architecture, and collaborate closely with our architecture, design, and validation teams. What You'll Do: · Own and drive the full verification cycle for IP blocks and subsystems · Create detailed verification plans, identify test items, and track coverage · Build UVM-based test benches from scratch, including drivers, monitors, and scoreboards · Perform low power verification using both UPF and Native Low Power (NLP) methods · Develop and run UVM-based test environments for Ethernet and other protocol interfaces · Integrate and work with third-party Verification IPs (VIPs) · Write and debug assertions and functional coverage models · Collaborate with design and architecture teams to close verification cycles efficiently · Support silicon bring-up and post-silicon debug when required · Mentor junior team members on verification techniques and best practices Key Skills We Are Looking For: · UPF / Low Power Verification (UVM expert) · Strong understanding of low-power concepts in ASIC design (UPF/NLP) from a verification perspective · UVM with Ethernet protocol expertise · NLP Test bench Verification with Native Low Power (UVM expert) · Strong command over System Verilog , Verilog , and UVM methodology · Solid understanding of ASIC design flows and power-aware design concepts · Experience with protocols like PCIe, AXI, CHI, Ethernet, USB, NVMe, DDR, and CXL · Good working knowledge of System Verilog Assertions (SVA) and formal verification techniques · Hands-on experience with scripting ( Python, Perl, Shell, TCL ) · Comfortable working in Linux development environments · Excellent debugging, problem-solving, and analytical thinking · Strong communication and collaboration skills Qualifications: · Bachelor’s degree in Electrical Engineering, Electronics and Communications Engineering, Computer Engineering, Computer Science, or related fields · Fluent in both written and spoken English · Excellent collaborative skills · Highly motivated and self-driven individual · Strong coding and object-oriented programming skills · Excellent debugging, problem solving, and analytical skills · Knowledgeable in digital design · Minimum 7 years of industry experience in Design Verification roles. · A track record of successfully verifying complex IP blocks or subsystems from spec to silicon. Please forward your resume to jasmine.h@boltchip.com