Verification Engineer - Embedded System

As a skilled ASIC/SoC Verification Engineer, you will be responsible for defining and implementing a power-aware verification strategy using UPF (IEEE 1801). Your role will involve integrating power intent into simulation environments, verifying power management features, and developing power-aware test benches and test cases in System Verilog/UVM. You will run simulations, debug failures, and ensure design functionality across power states. Collaboration with RTL designers and architects to ensure correct power domain partitioning and isolation will be a key aspect of your responsibilities. Additionally, you will perform static checks for power intent correctness using tools such as Synopsys VC LP or Cadence Conformal Low Power, and ensure compliance of low-power implementation with overall chip power and performance goals. To excel in this role, you should hold a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, along with a minimum of 5 years of experience in ASIC/SoC verification with a focus on low-power design. A solid understanding of UPF 2.0/2.1/3.0 and power-aware verification methodologies is essential. Proficiency in simulation tools like Synopsys VCS, Cadence Xcelium, and waveform debugging tools is required. Knowledge of System Verilog, UVM, and scripting languages such as Python, Perl, or TCL is crucial for success in this position. An understanding of power management techniques including power gating, clock gating, and multi-voltage domains will further strengthen your candidacy.,