7 Multivoltage Domains Jobs

Qualcomm India Private Limited is seeking a skilled Hardware Engineer to join the Engineering Group. In this role, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to contribute to the development of world-class products. Collaboration with cross-functional teams will be essential to meet performance requirements and drive innovation. The ideal candidate should possess a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with a minimum of 4 years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years of experience or a PhD with 2+ years of experience will also be considered. The successful candidate will have expertise in physical design from product-based/EDA companies, DDRPhy/PCIE-high-speed interface PD, Timing Signoff with SNPS/CDNS tools, PDN IR signoff, and automation skills in languages like python, Perl, or TCL. Experience in RDL-design, Bump Spec understanding, low power design implementation, ASIC design flows, and proficiency in automation for PPA improvements are highly desired. Knowledge of Unified Power Format (UPF), multi-voltage domains, and power gating will be advantageous. Familiarity with working on multiple technology nodes in advanced processes and physical design methodologies is also preferred. It would be beneficial to have design-level knowledge to optimize implementation for PPPA. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please reach out to disability-accommodations@qualcomm.com. Qualcomm expects its employees to adhere to all applicable policies and procedures, including security and confidentiality requirements. For further information about this role, please contact Qualcomm Careers.,

Qualcomm India Private Limited is seeking a skilled Hardware Engineer to join the Engineering Group, specifically within the Hardware Engineering department. In this role, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. Your work will involve a wide range of tasks including bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to facilitate the launch of cutting-edge, world-class products. Collaboration with cross-functional teams is crucial to develop solutions and meet performance requirements effectively. To be considered for this position, you must hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with a minimum of 4 years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years of experience or a PhD with 2+ years of experience will also be considered. Additionally, candidates are expected to possess a degree from a top-tier institute and have 8-14 years of experience in physical design from product-based companies. The ideal candidate should have proven experience in managing complex subsystems and small teams. Proficiency in complete Netlist2GDS, including Floorplan, place and route (PnR), and sign-off convergence, along with experience in lower technology nodes, is essential. Furthermore, expertise in meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems/System on Chips (SoCs), place and route, and IP integration is required. Experience in low power design implementation, familiarity with ASIC design flows and physical design methodologies, and a strong understanding of circuit design, device physics, and deep sub-micron technology are also critical for success in this role. Additionally, the successful candidate should have experience working on multiple technology nodes in advanced processes and proficiency in automation to drive improvements in PPA. The role will involve managing and driving a small team for project execution and PPA targets. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. For accommodation during the application/hiring process, individuals can contact disability-accommodations@qualcomm.com. Qualcomm expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. Staffing and recruiting agencies are advised that Qualcomm's Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Submissions from agencies or individuals represented by agencies will not be considered. Unsolicited resumes or applications will not be accepted. For more information about this role, interested individuals can reach out to Qualcomm Careers.,

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This includes bringing up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems for cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 2+ years of Hardware Engineering or related work experience. - OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 1+ year of Hardware Engineering or related work experience. - OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Qualifications: - Bachelors or Masters degree from a top-tier institute. - 2-5 years of experience in physical design from product-based companies. Experience: - Proven experience in managing complex subsystems and small teams. - Proficiency in synthesis, place and route (PnR), and sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations. Job Requirements: - Expertise in meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems/System on Chips (SoCs), place and route, and IP integration. - Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating. - Familiarity with ASIC design flows and physical design methodologies. - Strong understanding of circuit design, device physics, and deep sub-micron technology. - Experience working on multiple technology nodes in advanced processes. - Proficiency in automation to drive improvements in PPA. Qualcomm is an equal opportunity employer and is committed to providing accessible accommodations for individuals with disabilities during the application/hiring process. Qualcomm expects its employees to adhere to all applicable policies and procedures, including those related to the protection of company confidential information. For more information about this role, please contact Qualcomm Careers.,

As a skilled ASIC/SoC Verification Engineer, you will be responsible for defining and implementing a power-aware verification strategy using UPF (IEEE 1801). Your role will involve integrating power intent into simulation environments, verifying power management features, and developing power-aware test benches and test cases in System Verilog/UVM. You will run simulations, debug failures, and ensure design functionality across power states. Collaboration with RTL designers and architects to ensure correct power domain partitioning and isolation will be a key aspect of your responsibilities. Additionally, you will perform static checks for power intent correctness using tools such as Synopsys VC LP or Cadence Conformal Low Power, and ensure compliance of low-power implementation with overall chip power and performance goals. To excel in this role, you should hold a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, along with a minimum of 5 years of experience in ASIC/SoC verification with a focus on low-power design. A solid understanding of UPF 2.0/2.1/3.0 and power-aware verification methodologies is essential. Proficiency in simulation tools like Synopsys VCS, Cadence Xcelium, and waveform debugging tools is required. Knowledge of System Verilog, UVM, and scripting languages such as Python, Perl, or TCL is crucial for success in this position. An understanding of power management techniques including power gating, clock gating, and multi-voltage domains will further strengthen your candidacy.,

As an ASIC Design Engineer specializing in UPF and Low Power Design, you will be responsible for owning and driving RTL design for complex digital blocks with multiple power domains. Your role will involve defining, implementing, and validating power intent using UPF 2.0/3.0 for ASIC and SoC designs. Collaboration with verification and physical design teams will be crucial to ensure correct propagation and verification of power intent across the flow. You will work closely with architecture teams to define low power design strategies including power gating, clock gating, and multi-voltage domains. Additionally, analyzing and debugging power-related issues during RTL and gate-level simulations will be part of your responsibilities. It is essential to develop and maintain design documentation such as micro-architecture specs and power intent specifications. Supporting integration and implementation teams in handling low power design constraints and challenges will also be a key aspect of your role. To be successful in this position, you should hold a Bachelors or Masters degree in Electronics/Electrical Engineering or a related discipline. With a minimum of 7 years of ASIC front-end design experience, including at least 3 years focused on low power/UPF design, you should be proficient in RTL coding using Verilog/SystemVerilog with strong design fundamentals. A deep understanding of low power architecture techniques like power gating, retention, isolation, and voltage scaling is required. Hands-on experience with UPF-based flows and power-aware tools from Synopsys, Cadence, or Mentor is essential. Experience in running LINT, CDC, and synthesis with power intent, along with excellent debugging and problem-solving skills, are also necessary. Preferred skills include exposure to DFT constraints and the impact of power intent on scan/ATPG, familiarity with scripting languages like Python/Perl/TCL for automation, and experience in collaborating across global design and verification teams. A working knowledge of timing closure, clock domain crossing (CDC), and logic equivalence checks (LEC) would be beneficial in this role. Joining BOLTCHIP will offer you the opportunity to be part of a cutting-edge semiconductor design team focused on innovation and quality. You will collaborate with top-tier professionals in the low-power design domain and benefit from competitive compensation and opportunities for growth. If you meet the requirements and are excited about this opportunity, please apply by sending your resume to jasmine.h@boltchip.com.,

As a Hardware Engineer at Qualcomm India Private Limited, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems. Your responsibilities will include working on a wide range of systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, FPGA, and/or DSP systems to develop cutting-edge products. You will collaborate with cross-functional teams to ensure that the solutions meet performance requirements and contribute to the overall success of the projects. The ideal candidate for this role should possess a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 6 years of experience in Hardware Engineering. Alternatively, a Master's degree with 5+ years or a PhD with 4+ years of relevant work experience will also be considered. It is essential to have expertise in physical design, especially in DDRPhy /PCIE-high speed interface PD or 3DIC, and timing signoff experience with SNPS/CDNS tools. Proficiency in automation skills like python, Perl, or TCL is required to drive improvements in Power, Performance, and Area (PPA). The successful candidate should have a strong background in PDN, IR signoff, Physical verification knowledge, RDL-design, Bump Spec understanding, and experience working on multiple technology nodes in advanced processes. Familiarity with low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating is also desirable. Additionally, knowledge of ASIC design flows and physical design methodologies will be beneficial for this role. Having design-level knowledge to optimize the implementation for Power, Performance, and Area (PPA) will be considered a plus. Qualcomm believes in equal opportunities and is committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please reach out to Qualcomm at disability-accommodations@qualcomm.com or through the toll-free number available on their website.,

Qualcomm India Private Limited is seeking a talented Hardware Engineer to join their Engineering Group under the Hardware Engineering division. As a part of Qualcomm, a leading technology innovator, you will play a crucial role in designing, optimizing, and testing electronic systems to contribute to the development of cutting-edge, world-class products. Collaborating with cross-functional teams, you will work towards creating solutions that meet performance requirements and drive digital transformation in the smart, connected future. To qualify for this position, you should hold a Bachelor's or Master's degree from a prestigious institute and possess a minimum of 6 to 10 years of experience in physical design within product-based companies. The ideal candidate will have proven expertise in managing complex subsystems and small teams, along with proficiency in RTL2GDS, including Floorplan, place and route (PnR), and sign-off convergence. In this role, you will be responsible for meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems and System on Chips (SoCs), as well as low power design implementation. Your tasks will include working on multiple technology nodes in advanced processes, ensuring power gating, and driving improvements in PPA through automation. Additionally, you will be expected to lead a small team for project execution and achieving PPA targets. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, you may contact Qualcomm via email at disability-accommodations@qualcomm.com or through their toll-free number. As an employee of Qualcomm, you are expected to adhere to all applicable policies and procedures, including those related to the protection of confidential information. For more information about this exciting opportunity, please reach out to Qualcomm Careers.,