10 Power Gating Jobs

As a candidate for this position, you should hold a Bachelor's degree in Electronics or Computer Engineering/Science, or possess equivalent practical experience. With a minimum of 8 years of experience in SoC power modeling and analysis, you should also have a solid understanding of SOC architecture and power techniques. A Master's degree or PhD in Electronics, Computer Engineering, or Computer Science would be considered a preferred qualification. Additionally, experience with ASIC design flows and knowledge of low power architecture and power optimization techniques such as multi Vth/power/voltage domain design, clock gating, power gating, and Dynamic Voltage Frequency Scaling would be advantageous. Join a diverse team that is dedicated to pushing boundaries and developing custom silicon solutions to power the future of Google's direct-to-consumer products. Your contribution to the innovation behind products loved by millions worldwide will be crucial. Your expertise will play a significant role in shaping the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. At Google, our mission is to organize the world's information and make it universally accessible and useful. The Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. Through research, design, and development of new technologies and hardware, we aim to enhance user interaction with computing, making it faster, seamless, and more powerful. The Devices & Services team is dedicated to improving people's lives through technology by exploring new ways to capture and sense the world, advancing form factors, and enhancing interaction methods. Your responsibilities in this role will include defining power requirements for an SoC to optimize Power-Performance-Area (PPA) under current and thermal constraints. You will define power KPIs and SoC/IP-level power goals, guide architecture, design, implementation, and software to achieve power goals, and track power throughout the design cycle. Additionally, you will propose and drive power optimizations throughout the design process, perform algorithm development, modeling, and analysis of various power approaches, and lead power-performance trade-off analysis for engineering reviews and product roadmap decisions.,

KEY RESPONSIBLITIES: SoC Design and Microarchitecture Lead Translate high level SoC architecture to microarchitecture details to help SoC implementation and verification Expertise in SoC Chip Pervasive Logic Clock, Reset and Power microarchitecture and design Expertise in SoC Low Power Design Handling voltage and clock domain crossings, Power Gating and Retention, Power States Expertise in industry standard bus protocols - AMBA Understanding of SoC Architecture, Boot flows, Chip initialization, Fuse distribution, power sequence, reset sequence, clock sequence Understanding of SoC RTL Integration Understanding of SoC implementation flows Synthesis and Physical Design ACADEMIC CREDENTIALS: Bachelors orMastersdegree in computer engineering/Electrical Engineering

KEY RESPONSIBLITIES: SoC Design and Microarchitecture Lead Translate high level SoC architecture to microarchitecture details to help SoC implementation and verification Expertise in SoC Chip Pervasive Logic Clock, Reset and Power microarchitecture and design Expertise in SoC Low Power Design Handling voltage and clock domain crossings, Power Gating and Retention, Power States Expertise in industry standard bus protocols - AMBA Understanding of SoC Architecture, Boot flows, Chip initialization, Fuse distribution, power sequence, reset sequence, clock sequence Understanding of SoC RTL Integration Understanding of SoC implementation flows Synthesis and Physical Design ACADEMIC CREDENTIALS: Bachelors orMastersdegree in computer engineering/Electrical Engineering

RTL/Integration- Design Engineer Work Location : Bengaluru, Whitefield Qualification : 5-10 years full-time experience in IP hardware design Mode of interview : Virtual Availability to join: candidates who can join in 30-45 Days are preferred. Normal Working Hours, 5 days a week Work Mode : Work from Office The Project and role : As a member of the Computing and Graphics group , you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. The Person: The ideal candidate will have experience developing RTL for IP or subsystems and understand architectural specifications. Responsibilities include IP and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively with the IP/SoC team. Key Responsibilities: Design of IP and subsystems with integration of AMD and other 3rd party IPs Perform quality checks (lint, CDC, and power rule checks) of power-gated digital designs Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up Preferred Experience: Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs Verilog lint tools (Spyglass) and verilog simulation tools (VCS) Clock domain crossing (CDC) tools Detailed understanding of SoC design flows Understanding of IP/SS/SoC Power Management techniques Power Gating, Clock Gating Experience with embedded processors and data fabric architectures (NoC) Functional Skills Outstanding interaction skills while communicating both written and verbally Ability to work with multi-level functional teams across various geographies Outstanding problem-solving and analytical skills ACADEMIC CREDENTIALS: Bachelors or Masters degree in Computer Engineering/Electrical Engineering

We are seeking a skilled and highly motivated Physical Design Engineer to join our team. The ideal candidate will be responsible for the independent planning and execution of the entire Netlist-to-GDSII flow, demonstrating a strong understanding of all physical design aspects and methodologies. This role requires technical expertise, problem-solving abilities, and the capacity to guide junior engineers. Roles and Responsibilities: Responsible for independent planning and execution of the Netlist-to-GDSII flow. Demonstrate strong exposure to all aspects of design flows, including floor planning, placement, Clock Tree Synthesis (CTS), routing, crosstalk analysis, and physical verification . Possess good exposure to high-frequency design convergence and a solid understanding of physical design methodology . Work independently in all areas of RTL to GDSII implementation . Exhibit the ability to collaborate effectively and resolve issues related to constraints validation, verification, Static Timing Analysis (STA), and overall physical design. Apply knowledge of low power flow concepts such as power gating, multi-VT flow, and power supply management . Possess circuit-level comprehension of time-critical paths within the design. Utilize Tcl/Perl scripting for automation and efficiency. Be willing to handle technical deliveries and provide guidance to a team of engineers. Be well-versed with level timing closure (STA) , various timing closure methodologies , and ECO (Engineering Change Order) generation for predictable convergence. Be well-versed with parasitic extraction, LVS (Layout Versus Schematic)/DRC (Design Rule Checking) , and other Physical Verification checks . Provide clear directions to the team regarding Place & Route (PNR) issues . Understand deep sub-micron design problems and solutions , including leakage power, signal integrity, and DFM (Design For Manufacturability) . Education: B.E/B.Tech or M.E/M.Tech/M.S in Electrical or Electronics engineering.

You should have at least 8 years of experience in Micro-architecture, SoC development, and full-chip design for multi-million gate SoCs. Your expertise should include a strong understanding of the design convergence cycle, encompassing architecture, micro-architecture, Verification, Synthesis, and timing closure. You should also be adept at managing IP dependencies and planning front-end design tasks effectively. Additionally, you should have experience in designing and developing high-speed serial IO protocols. Your skills should cover the implementation of clock rate compensation FIFO, gearbox design for data width, bypass on controller, power gating, and low power modes. Experience in CPU, bus fabrics, or coherence/noncoherent NOC domains would be highly desirable for this role.,

Qualcomm India Private Limited is looking for a passionate STA and Synthesis Engineer to join their Engineering Group in Chennai. As an integral part of the cross-functional engineering teams, you will be engaged in all phases of design and development cycles, specifically focusing on Synthesis, Static Timing Analysis, and LEC of SoC/Cores. Your responsibilities will include full chip and block level timing closure, IO budgeting for blocks, logical equivalence checks between RTL to Netlist and Netlist to Netlist, as well as implementing low-power techniques such as clock gating, power gating, and MV designs. Additionally, you will be involved in ECO timing flow and should be proficient in scripting languages like TCL and Perl. The ideal candidate should possess a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 2+ years of experience in Hardware Engineering. Alternatively, a Master's degree with 1+ year of relevant experience or a PhD in the aforementioned fields is also acceptable. Applicants with 1-5 years of experience are encouraged to apply. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact Qualcomm at disability-accommodations@qualcomm.com or refer to their toll-free number for assistance. Qualcomm also emphasizes the importance of compliance with company policies and procedures, including security measures for protecting confidential information. Staffing and Recruiting Agencies are advised that Qualcomm's Careers Site is exclusively for individuals seeking job opportunities directly with Qualcomm. Agency submissions will be considered unsolicited, and Qualcomm does not accept unsolicited resumes or applications from agencies. For further details about this role, please reach out to Qualcomm Careers.,

As a Hardware Engineer at Qualcomm India Private Limited, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems. Your responsibilities will include working on a wide range of systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, FPGA, and/or DSP systems to develop cutting-edge products. You will collaborate with cross-functional teams to ensure that the solutions meet performance requirements and contribute to the overall success of the projects. The ideal candidate for this role should possess a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 6 years of experience in Hardware Engineering. Alternatively, a Master's degree with 5+ years or a PhD with 4+ years of relevant work experience will also be considered. It is essential to have expertise in physical design, especially in DDRPhy /PCIE-high speed interface PD or 3DIC, and timing signoff experience with SNPS/CDNS tools. Proficiency in automation skills like python, Perl, or TCL is required to drive improvements in Power, Performance, and Area (PPA). The successful candidate should have a strong background in PDN, IR signoff, Physical verification knowledge, RDL-design, Bump Spec understanding, and experience working on multiple technology nodes in advanced processes. Familiarity with low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating is also desirable. Additionally, knowledge of ASIC design flows and physical design methodologies will be beneficial for this role. Having design-level knowledge to optimize the implementation for Power, Performance, and Area (PPA) will be considered a plus. Qualcomm believes in equal opportunities and is committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please reach out to Qualcomm at disability-accommodations@qualcomm.com or through the toll-free number available on their website.,

Qualcomm India Private Limited is seeking a talented Hardware Engineer to join their Engineering Group under the Hardware Engineering division. As a part of Qualcomm, a leading technology innovator, you will play a crucial role in designing, optimizing, and testing electronic systems to contribute to the development of cutting-edge, world-class products. Collaborating with cross-functional teams, you will work towards creating solutions that meet performance requirements and drive digital transformation in the smart, connected future. To qualify for this position, you should hold a Bachelor's or Master's degree from a prestigious institute and possess a minimum of 6 to 10 years of experience in physical design within product-based companies. The ideal candidate will have proven expertise in managing complex subsystems and small teams, along with proficiency in RTL2GDS, including Floorplan, place and route (PnR), and sign-off convergence. In this role, you will be responsible for meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems and System on Chips (SoCs), as well as low power design implementation. Your tasks will include working on multiple technology nodes in advanced processes, ensuring power gating, and driving improvements in PPA through automation. Additionally, you will be expected to lead a small team for project execution and achieving PPA targets. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, you may contact Qualcomm via email at disability-accommodations@qualcomm.com or through their toll-free number. As an employee of Qualcomm, you are expected to adhere to all applicable policies and procedures, including those related to the protection of confidential information. For more information about this exciting opportunity, please reach out to Qualcomm Careers.,

y Low Power UPF Front-End Design Engineer :- Bangalore Founded in 2023,by Industry veterans HQ in California,US We are revolutionizing sustainable AI compute through intuitive software with composable silicon Low Power UPF Front-End Design Engineer :- Job Description: Deep expertise in low-power architecture, UPF-based power intent implementation, and front-end RTL methodologies. This role requires close collaboration with system architects, RTL design engineers, and back-end teams. Technical Requirement: Define and develop low-power architecture and strategies using Unified Power Format (UPF) Drive power intent specification, verification, and validation through all phases of the design lifecycle Collaborate with front-end design teams to ensure power-efficient RTL design, clock gating, power gating, voltage scaling, and retention strategies. Work closely with verification teams to develop power-aware simulation methodologies and tools. Perform power analysis, modeling, and trade-offs at the architectural and RTL level. Guide the synthesis and timing closure process with power intent considerations. Define and drive industry best practices in low-power methodologies, tools, and flows Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"