Synthesis/Physical Synthesis/pre-layout STA

We are seeking a skilled and detail-oriented Engineer specializing in Synthesis, Physical Synthesis, and pre-layout Static Timing Analysis (STA). The ideal candidate will have strong expertise in various aspects of digital design implementation, including UPF generation, synthesis optimizations, and constraint development. This role is crucial for ensuring the functional correctness, performance, and power efficiency of our semiconductor designs.

Key Responsibilities:

• Perform

  Synthesis, Physical Synthesis, and pre-layout Static Timing Analysis (STA)

  for complex digital designs.
• Responsible for

  UPF (Unified Power Format) generation from scratch

  to define power intent for low-power designs.
• Execute

  synthesis

  of RTL code into gate-level netlists.
• Implement

  Multi-Vt (Multi-Threshold Voltage) optimizations

  to achieve power and performance targets.
• Implement and optimize

  Clock Gating

  techniques for power reduction.
• Perform

  Datapath Synthesis

  to ensure efficient data flow implementation.
• Conduct

  Scan Insertion

  for Design For Testability (DFT).
• Ensure designs are

  Multi-supply/Switching aware

  for robust power management.
• Implement and verify

  DVFS (Dynamic Voltage and Frequency Scaling)

  techniques.
• Perform

  Retiming

  to optimize critical paths for timing closure.
• Undertake

  Constraint Development

  , ensuring accurate and comprehensive timing constraints.
• Possess

  IP constraint knowledge

  on interfaces like

  DDR3/4, Multiprotocol SerDes, ARM core and Subsystem, USB3.0

  , which is a significant plus.

Required Skills and Qualifications:

• Strong expertise in digital design

  Synthesis and Physical Synthesis

  .
• Proficient in

  pre-layout Static Timing Analysis (STA)

  .
• Experience with

  UPF generation

  .
• Knowledge of

  Multi-Vt optimizations, Clock Gating, Datapath Synthesis, Scan Insertion, Multi-supply/Switching awareness, DVFS, and Retiming

  .
• Strong skills in

  Constraint Development

  .
• Familiarity with IP constraints on

  DDR3/4, Multiprotocol SerDes, ARM core and Subsystem, USB3.0

  is highly desirable.