3.0 - 7.0 years

0 Lacs

karnataka

On-site

You should have a strong understanding of design power intent at the RTL level and UPF. You should be able to translate power intent into UPF after consulting with the RTL designers. Your responsibilities will include running, debugging, and resolving Static Power Check (VCLP) related issues independently before RTL is handed off to PD. Your tasks will involve UPF generation (yaml creation, running upfgen to create the UPF) and UPF maintenance. As RTL changes, UPF may need adjustments and re-verification. You should also be proficient in running VCLP and integrating it with the top level as well as with the P&R flows. We are looking for a UPF expert with a strong background in low power design. We require UPF expertise as a primary skill, not as a secondary one. It is acceptable to have one back end and one front end with PNR, guided by one consultant. The responsibilities include RTL UPF coding, LP validation, level shifter strategy, and potentially handling UPF within the PNR flows. If the candidate is not familiar with PNR flows, we can fill that gap with a back end UPF person.,

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Synthesis/Physical Synthesis/pre-layout STA Aarna Hr Solutions

4.0 - 7.0 years

4 - 7 Lacs

Bengaluru, Karnataka, India

On-site

We are seeking a skilled and detail-oriented Engineer specializing in Synthesis, Physical Synthesis, and pre-layout Static Timing Analysis (STA). The ideal candidate will have strong expertise in various aspects of digital design implementation, including UPF generation, synthesis optimizations, and constraint development. This role is crucial for ensuring the functional correctness, performance, and power efficiency of our semiconductor designs. Key Responsibilities: Perform Synthesis, Physical Synthesis, and pre-layout Static Timing Analysis (STA) for complex digital designs. Responsible for UPF (Unified Power Format) generation from scratch to define power intent for low-power designs. Execute synthesis of RTL code into gate-level netlists. Implement Multi-Vt (Multi-Threshold Voltage) optimizations to achieve power and performance targets. Implement and optimize Clock Gating techniques for power reduction. Perform Datapath Synthesis to ensure efficient data flow implementation. Conduct Scan Insertion for Design For Testability (DFT). Ensure designs are Multi-supply/Switching aware for robust power management. Implement and verify DVFS (Dynamic Voltage and Frequency Scaling) techniques. Perform Retiming to optimize critical paths for timing closure. Undertake Constraint Development , ensuring accurate and comprehensive timing constraints. Possess IP constraint knowledge on interfaces like DDR3/4, Multiprotocol SerDes, ARM core and Subsystem, USB3.0 , which is a significant plus. Required Skills and Qualifications: Strong expertise in digital design Synthesis and Physical Synthesis . Proficient in pre-layout Static Timing Analysis (STA) . Experience with UPF generation . Knowledge of Multi-Vt optimizations, Clock Gating, Datapath Synthesis, Scan Insertion, Multi-supply/Switching awareness, DVFS, and Retiming . Strong skills in Constraint Development . Familiarity with IP constraints on DDR3/4, Multiprotocol SerDes, ARM core and Subsystem, USB3.0 is highly desirable.

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